misakiotoha/OpenIPC_RTL8812AU_Forword_cpp
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This commit is contained in:
Misaki
2026-09-13 13:30:21 +08:00
commit a6bbd520cf
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3rd/devourer/hal/phydm/halrf/rtl8814a/halhwimg8814a_rf.c
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3rd/devourer/hal/phydm/halrf/rtl8814a/halhwimg8814a_rf.h
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
/*Image2HeaderVersion: R3 1.5.6*/
#if (RTL8814A_SUPPORT == 1)
#ifndef __INC_MP_RF_HW_IMG_8814A_H
#define __INC_MP_RF_HW_IMG_8814A_H
/* Please add following compiler flags definition (#define CONFIG_XXX_DRV_DIS)
* into driver source code to reduce code size if necessary.
* #define CONFIG_8814A_DRV_DIS
* #define CONFIG_8814A_TYPE0_DRV_DIS
* #define CONFIG_8814A_TYPE1_DRV_DIS
* #define CONFIG_8814A_TYPE10_DRV_DIS
* #define CONFIG_8814A_TYPE11_DRV_DIS
* #define CONFIG_8814A_TYPE2_DRV_DIS
* #define CONFIG_8814A_TYPE3_DRV_DIS
* #define CONFIG_8814A_TYPE4_DRV_DIS
* #define CONFIG_8814A_TYPE5_DRV_DIS
* #define CONFIG_8814A_TYPE6_DRV_DIS
* #define CONFIG_8814A_TYPE7_DRV_DIS
* #define CONFIG_8814A_TYPE8_DRV_DIS
* #define CONFIG_8814A_TYPE9_DRV_DIS
*/
#define CONFIG_8814A
#ifdef CONFIG_8814A_DRV_DIS
#undef CONFIG_8814A
#endif
#define CONFIG_8814A_TYPE0
#ifdef CONFIG_8814A_TYPE0_DRV_DIS
#undef CONFIG_8814A_TYPE0
#endif
#define CONFIG_8814A_TYPE1
#ifdef CONFIG_8814A_TYPE1_DRV_DIS
#undef CONFIG_8814A_TYPE1
#endif
#define CONFIG_8814A_TYPE10
#ifdef CONFIG_8814A_TYPE10_DRV_DIS
#undef CONFIG_8814A_TYPE10
#endif
#define CONFIG_8814A_TYPE11
#ifdef CONFIG_8814A_TYPE11_DRV_DIS
#undef CONFIG_8814A_TYPE11
#endif
#define CONFIG_8814A_TYPE2
#ifdef CONFIG_8814A_TYPE2_DRV_DIS
#undef CONFIG_8814A_TYPE2
#endif
#define CONFIG_8814A_TYPE3
#ifdef CONFIG_8814A_TYPE3_DRV_DIS
#undef CONFIG_8814A_TYPE3
#endif
#define CONFIG_8814A_TYPE4
#ifdef CONFIG_8814A_TYPE4_DRV_DIS
#undef CONFIG_8814A_TYPE4
#endif
#define CONFIG_8814A_TYPE5
#ifdef CONFIG_8814A_TYPE5_DRV_DIS
#undef CONFIG_8814A_TYPE5
#endif
#define CONFIG_8814A_TYPE6
#ifdef CONFIG_8814A_TYPE6_DRV_DIS
#undef CONFIG_8814A_TYPE6
#endif
#define CONFIG_8814A_TYPE7
#ifdef CONFIG_8814A_TYPE7_DRV_DIS
#undef CONFIG_8814A_TYPE7
#endif
#define CONFIG_8814A_TYPE8
#ifdef CONFIG_8814A_TYPE8_DRV_DIS
#undef CONFIG_8814A_TYPE8
#endif
#define CONFIG_8814A_TYPE9
#ifdef CONFIG_8814A_TYPE9_DRV_DIS
#undef CONFIG_8814A_TYPE9
#endif
/******************************************************************************
* radioa.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8814a_radioa(struct dm_struct *dm);
u32 odm_get_version_mp_8814a_radioa(void);
/******************************************************************************
* radiob.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8814a_radiob(struct dm_struct *dm);
u32 odm_get_version_mp_8814a_radiob(void);
/******************************************************************************
* radioc.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8814a_radioc(struct dm_struct *dm);
u32 odm_get_version_mp_8814a_radioc(void);
/******************************************************************************
* radiod.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8814a_radiod(struct dm_struct *dm);
u32 odm_get_version_mp_8814a_radiod(void);
/******************************************************************************
* txpowertrack.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8814a_txpowertrack(struct dm_struct *dm);
u32 odm_get_version_mp_8814a_txpowertrack(void);
/******************************************************************************
* txpowertrack_type0.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8814a_txpowertrack_type0(struct dm_struct *dm);
u32 odm_get_version_mp_8814a_txpowertrack_type0(void);
/******************************************************************************
* txpowertrack_type1.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8814a_txpowertrack_type1(struct dm_struct *dm);
u32 odm_get_version_mp_8814a_txpowertrack_type1(void);
/******************************************************************************
* txpowertrack_type10.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8814a_txpowertrack_type10(struct dm_struct *dm);
u32 odm_get_version_mp_8814a_txpowertrack_type10(void);
/******************************************************************************
* txpowertrack_type11.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8814a_txpowertrack_type11(struct dm_struct *dm);
u32 odm_get_version_mp_8814a_txpowertrack_type11(void);
/******************************************************************************
* txpowertrack_type2.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8814a_txpowertrack_type2(struct dm_struct *dm);
u32 odm_get_version_mp_8814a_txpowertrack_type2(void);
/******************************************************************************
* txpowertrack_type3.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8814a_txpowertrack_type3(struct dm_struct *dm);
u32 odm_get_version_mp_8814a_txpowertrack_type3(void);
/******************************************************************************
* txpowertrack_type4.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8814a_txpowertrack_type4(struct dm_struct *dm);
u32 odm_get_version_mp_8814a_txpowertrack_type4(void);
/******************************************************************************
* txpowertrack_type5.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8814a_txpowertrack_type5(struct dm_struct *dm);
u32 odm_get_version_mp_8814a_txpowertrack_type5(void);
/******************************************************************************
* txpowertrack_type6.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8814a_txpowertrack_type6(struct dm_struct *dm);
u32 odm_get_version_mp_8814a_txpowertrack_type6(void);
/******************************************************************************
* txpowertrack_type7.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8814a_txpowertrack_type7(struct dm_struct *dm);
u32 odm_get_version_mp_8814a_txpowertrack_type7(void);
/******************************************************************************
* txpowertrack_type8.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8814a_txpowertrack_type8(struct dm_struct *dm);
u32 odm_get_version_mp_8814a_txpowertrack_type8(void);
/******************************************************************************
* txpowertrack_type9.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8814a_txpowertrack_type9(struct dm_struct *dm);
u32 odm_get_version_mp_8814a_txpowertrack_type9(void);
/******************************************************************************
* txpowertssi.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8814a_txpowertssi(struct dm_struct *dm);
u32 odm_get_version_mp_8814a_txpowertssi(void);
/******************************************************************************
* txpwr_lmt.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8814a_txpwr_lmt(struct dm_struct *dm);
u32 odm_get_version_mp_8814a_txpwr_lmt(void);
/******************************************************************************
* txpwr_lmt_type0.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8814a_txpwr_lmt_type0(struct dm_struct *dm);
u32 odm_get_version_mp_8814a_txpwr_lmt_type0(void);
/******************************************************************************
* txpwr_lmt_type1.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8814a_txpwr_lmt_type1(struct dm_struct *dm);
u32 odm_get_version_mp_8814a_txpwr_lmt_type1(void);
/******************************************************************************
* txpwr_lmt_type10.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8814a_txpwr_lmt_type10(struct dm_struct *dm);
u32 odm_get_version_mp_8814a_txpwr_lmt_type10(void);
/******************************************************************************
* txpwr_lmt_type11.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8814a_txpwr_lmt_type11(struct dm_struct *dm);
u32 odm_get_version_mp_8814a_txpwr_lmt_type11(void);
/******************************************************************************
* txpwr_lmt_type2.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8814a_txpwr_lmt_type2(struct dm_struct *dm);
u32 odm_get_version_mp_8814a_txpwr_lmt_type2(void);
/******************************************************************************
* txpwr_lmt_type3.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8814a_txpwr_lmt_type3(struct dm_struct *dm);
u32 odm_get_version_mp_8814a_txpwr_lmt_type3(void);
/******************************************************************************
* txpwr_lmt_type4.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8814a_txpwr_lmt_type4(struct dm_struct *dm);
u32 odm_get_version_mp_8814a_txpwr_lmt_type4(void);
/******************************************************************************
* txpwr_lmt_type5.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8814a_txpwr_lmt_type5(struct dm_struct *dm);
u32 odm_get_version_mp_8814a_txpwr_lmt_type5(void);
/******************************************************************************
* txpwr_lmt_type6.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8814a_txpwr_lmt_type6(struct dm_struct *dm);
u32 odm_get_version_mp_8814a_txpwr_lmt_type6(void);
/******************************************************************************
* txpwr_lmt_type7.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8814a_txpwr_lmt_type7(struct dm_struct *dm);
u32 odm_get_version_mp_8814a_txpwr_lmt_type7(void);
/******************************************************************************
* txpwr_lmt_type8.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8814a_txpwr_lmt_type8(struct dm_struct *dm);
u32 odm_get_version_mp_8814a_txpwr_lmt_type8(void);
/******************************************************************************
* txpwr_lmt_type9.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8814a_txpwr_lmt_type9(struct dm_struct *dm);
u32 odm_get_version_mp_8814a_txpwr_lmt_type9(void);
#endif
#endif /* end of HWIMG_SUPPORT*/
3rd/devourer/hal/phydm/halrf/rtl8821c/halhwimg8821c_rf.c
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3rd/devourer/hal/phydm/halrf/rtl8822b/halhwimg8822b_rf.c
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3rd/devourer/hal/phydm/halrf/rtl8822c/halhwimg8822c_rf.c
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3rd/devourer/hal/phydm/halrf/rtl8822c/halrf_rfk_init_8822c.h
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3rd/devourer/hal/phydm/halrf/rtl8822e/halhwimg8822e_rf.c
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3rd/devourer/hal/phydm/halrf/rtl8822e/halrf_rfk_init_8822e.h
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3rd/devourer/hal/phydm/rtl8814a/Hal8814_PhyTables.c
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3rd/devourer/hal/phydm/rtl8814a/Hal8814_PhyTables.h
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/* Auto-generated by tools/extract_8814a_phy_tables.py.
* Source: aircrack-ng/rtl8814au v5.8.5.1. */
#ifndef HAL8814_PHYTABLES_H
#define HAL8814_PHYTABLES_H
#include "drv_types.h"
#ifdef __cplusplus
extern "C" {
#endif
extern const u32 array_mp_8814a_agc_tab[];
extern const u32 array_mp_8814a_agc_tab_len;
extern const u32 array_mp_8814a_phy_reg[];
extern const u32 array_mp_8814a_phy_reg_len;
extern const u32 array_mp_8814a_phy_reg_mp[];
extern const u32 array_mp_8814a_phy_reg_mp_len;
extern const u32 array_mp_8814a_phy_reg_pg[];
extern const u32 array_mp_8814a_phy_reg_pg_len;
extern const u32 array_mp_8814a_phy_reg_pg_type0[];
extern const u32 array_mp_8814a_phy_reg_pg_type0_len;
extern const u32 array_mp_8814a_phy_reg_pg_type1[];
extern const u32 array_mp_8814a_phy_reg_pg_type1_len;
extern const u32 array_mp_8814a_phy_reg_pg_type10[];
extern const u32 array_mp_8814a_phy_reg_pg_type10_len;
extern const u32 array_mp_8814a_phy_reg_pg_type11[];
extern const u32 array_mp_8814a_phy_reg_pg_type11_len;
extern const u32 array_mp_8814a_phy_reg_pg_type2[];
extern const u32 array_mp_8814a_phy_reg_pg_type2_len;
extern const u32 array_mp_8814a_phy_reg_pg_type3[];
extern const u32 array_mp_8814a_phy_reg_pg_type3_len;
extern const u32 array_mp_8814a_phy_reg_pg_type4[];
extern const u32 array_mp_8814a_phy_reg_pg_type4_len;
extern const u32 array_mp_8814a_phy_reg_pg_type5[];
extern const u32 array_mp_8814a_phy_reg_pg_type5_len;
extern const u32 array_mp_8814a_phy_reg_pg_type6[];
extern const u32 array_mp_8814a_phy_reg_pg_type6_len;
extern const u32 array_mp_8814a_phy_reg_pg_type7[];
extern const u32 array_mp_8814a_phy_reg_pg_type7_len;
extern const u32 array_mp_8814a_phy_reg_pg_type8[];
extern const u32 array_mp_8814a_phy_reg_pg_type8_len;
extern const u32 array_mp_8814a_phy_reg_pg_type9[];
extern const u32 array_mp_8814a_phy_reg_pg_type9_len;
extern const u32 array_mp_8814a_mac_reg[];
extern const u32 array_mp_8814a_mac_reg_len;
extern const u32 array_mp_8814a_radioa[];
extern const u32 array_mp_8814a_radioa_len;
extern const u32 array_mp_8814a_radiob[];
extern const u32 array_mp_8814a_radiob_len;
extern const u32 array_mp_8814a_radioc[];
extern const u32 array_mp_8814a_radioc_len;
extern const u32 array_mp_8814a_radiod[];
extern const u32 array_mp_8814a_radiod_len;
#ifdef __cplusplus
}
#endif
#endif /* HAL8814_PHYTABLES_H */
3rd/devourer/hal/phydm/rtl8814a/hal8814areg_odm.h
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
/* ************************************************************
* File Name: hal8814areg_odm.h
*
* Description:
*
* This file is for RTL8814A register definition.
*
*
* ************************************************************ */
#ifndef __HAL_8814A_REG_H__
#define __HAL_8814A_REG_H__
/*
* Register Definition
* */
#define TRX_ANTDIV_PATH 0x860
#define RX_ANTDIV_PATH 0xb2c
#define ODM_R_A_AGC_CORE1_8814A 0xc50
/*
* Bitmap Definition
* */
#define BIT_FA_RESET_8814A BIT(0)
#endif
3rd/devourer/hal/phydm/rtl8814a/halhwimg8814a_bb.c
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3rd/devourer/hal/phydm/rtl8814a/halhwimg8814a_bb.h
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
/*Image2HeaderVersion: R3 1.5.6*/
#if (RTL8814A_SUPPORT == 1)
#ifndef __INC_MP_BB_HW_IMG_8814A_H
#define __INC_MP_BB_HW_IMG_8814A_H
/******************************************************************************
* agc_tab.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8814a_agc_tab(struct dm_struct *dm);
u32 odm_get_version_mp_8814a_agc_tab(void);
/******************************************************************************
* phy_reg.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8814a_phy_reg(struct dm_struct *dm);
u32 odm_get_version_mp_8814a_phy_reg(void);
/******************************************************************************
* phy_reg_mp.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8814a_phy_reg_mp(struct dm_struct *dm);
u32 odm_get_version_mp_8814a_phy_reg_mp(void);
/******************************************************************************
* phy_reg_pg.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8814a_phy_reg_pg(struct dm_struct *dm);
u32 odm_get_version_mp_8814a_phy_reg_pg(void);
/******************************************************************************
* phy_reg_pg_type0.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8814a_phy_reg_pg_type0(struct dm_struct *dm);
u32 odm_get_version_mp_8814a_phy_reg_pg_type0(void);
/******************************************************************************
* phy_reg_pg_type1.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8814a_phy_reg_pg_type1(struct dm_struct *dm);
u32 odm_get_version_mp_8814a_phy_reg_pg_type1(void);
/******************************************************************************
* phy_reg_pg_type10.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8814a_phy_reg_pg_type10(struct dm_struct *dm);
u32 odm_get_version_mp_8814a_phy_reg_pg_type10(void);
/******************************************************************************
* phy_reg_pg_type11.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8814a_phy_reg_pg_type11(struct dm_struct *dm);
u32 odm_get_version_mp_8814a_phy_reg_pg_type11(void);
/******************************************************************************
* phy_reg_pg_type2.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8814a_phy_reg_pg_type2(struct dm_struct *dm);
u32 odm_get_version_mp_8814a_phy_reg_pg_type2(void);
/******************************************************************************
* phy_reg_pg_type3.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8814a_phy_reg_pg_type3(struct dm_struct *dm);
u32 odm_get_version_mp_8814a_phy_reg_pg_type3(void);
/******************************************************************************
* phy_reg_pg_type4.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8814a_phy_reg_pg_type4(struct dm_struct *dm);
u32 odm_get_version_mp_8814a_phy_reg_pg_type4(void);
/******************************************************************************
* phy_reg_pg_type5.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8814a_phy_reg_pg_type5(struct dm_struct *dm);
u32 odm_get_version_mp_8814a_phy_reg_pg_type5(void);
/******************************************************************************
* phy_reg_pg_type6.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8814a_phy_reg_pg_type6(struct dm_struct *dm);
u32 odm_get_version_mp_8814a_phy_reg_pg_type6(void);
/******************************************************************************
* phy_reg_pg_type7.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8814a_phy_reg_pg_type7(struct dm_struct *dm);
u32 odm_get_version_mp_8814a_phy_reg_pg_type7(void);
/******************************************************************************
* phy_reg_pg_type8.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8814a_phy_reg_pg_type8(struct dm_struct *dm);
u32 odm_get_version_mp_8814a_phy_reg_pg_type8(void);
/******************************************************************************
* phy_reg_pg_type9.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8814a_phy_reg_pg_type9(struct dm_struct *dm);
u32 odm_get_version_mp_8814a_phy_reg_pg_type9(void);
#endif
#endif /* end of HWIMG_SUPPORT*/
3rd/devourer/hal/phydm/rtl8814a/halhwimg8814a_mac.c
+326
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@@ -0,0 +1,326 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
/*Image2HeaderVersion: R3 1.5.6*/
#include "mp_precomp.h"
#include "../phydm_precomp.h"
#if (RTL8814A_SUPPORT == 1)
static boolean
check_positive(struct dm_struct *dm,
const u32 condition1,
const u32 condition2,
const u32 condition3,
const u32 condition4
)
{
u32 cond1 = condition1, cond2 = condition2,
cond3 = condition3, cond4 = condition4;
u8 cut_version_for_para =
(dm->cut_version == ODM_CUT_A) ? 15 : dm->cut_version;
u8 pkg_type_for_para =
(dm->package_type == 0) ? 15 : dm->package_type;
u32 driver1 = cut_version_for_para << 24 |
(dm->support_interface & 0xF0) << 16 |
dm->support_platform << 16 |
pkg_type_for_para << 12 |
(dm->support_interface & 0x0F) << 8 |
dm->rfe_type;
u32 driver2 = (dm->type_glna & 0xFF) << 0 |
(dm->type_gpa & 0xFF) << 8 |
(dm->type_alna & 0xFF) << 16 |
(dm->type_apa & 0xFF) << 24;
u32 driver3 = 0;
u32 driver4 = (dm->type_glna & 0xFF00) >> 8 |
(dm->type_gpa & 0xFF00) |
(dm->type_alna & 0xFF00) << 8 |
(dm->type_apa & 0xFF00) << 16;
PHYDM_DBG(dm, ODM_COMP_INIT,
"===> %s (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n",
__func__, cond1, cond2, cond3, cond4);
PHYDM_DBG(dm, ODM_COMP_INIT,
"===> %s (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n",
__func__, driver1, driver2, driver3, driver4);
PHYDM_DBG(dm, ODM_COMP_INIT,
" (Platform, Interface) = (0x%X, 0x%X)\n",
dm->support_platform, dm->support_interface);
PHYDM_DBG(dm, ODM_COMP_INIT, " (RFE, Package) = (0x%X, 0x%X)\n",
dm->rfe_type, dm->package_type);
/*============== value Defined Check ===============*/
/*cut version [27:24] need to do value check*/
if (((cond1 & 0x0F000000) != 0) &&
((cond1 & 0x0F000000) != (driver1 & 0x0F000000)))
return false;
/*pkg type [15:12] need to do value check*/
if (((cond1 & 0x0000F000) != 0) &&
((cond1 & 0x0000F000) != (driver1 & 0x0000F000)))
return false;
/*interface [11:8] need to do value check*/
if (((cond1 & 0x00000F00) != 0) &&
((cond1 & 0x00000F00) != (driver1 & 0x00000F00)))
return false;
/*=============== Bit Defined Check ================*/
/* We don't care [31:28] */
cond1 &= 0x000000FF;
driver1 &= 0x000000FF;
if (cond1 == driver1)
return true;
else
return false;
}
/******************************************************************************
* mac_reg.TXT
******************************************************************************/
const u32 array_mp_8814a_mac_reg[] = {
0x010, 0x0000007C,
0x014, 0x000000DB,
0x016, 0x00000002,
0x073, 0x00000010,
0x420, 0x00000080,
0x421, 0x0000000F,
0x428, 0x0000000A,
0x429, 0x00000010,
0x430, 0x00000000,
0x431, 0x00000000,
0x432, 0x00000000,
0x433, 0x00000001,
0x434, 0x00000004,
0x435, 0x00000005,
0x436, 0x00000007,
0x437, 0x00000008,
0x43C, 0x00000004,
0x43D, 0x00000005,
0x43E, 0x00000007,
0x43F, 0x00000008,
0x440, 0x0000005D,
0x441, 0x00000001,
0x442, 0x00000000,
0x444, 0x00000010,
0x445, 0x000000F0,
0x446, 0x00000001,
0x447, 0x000000FE,
0x448, 0x00000000,
0x449, 0x00000000,
0x44A, 0x00000000,
0x44B, 0x00000040,
0x44C, 0x00000010,
0x44D, 0x000000F0,
0x44E, 0x0000003F,
0x44F, 0x00000000,
0x450, 0x00000000,
0x451, 0x00000000,
0x452, 0x00000000,
0x453, 0x00000040,
0x45E, 0x00000004,
0x49C, 0x00000010,
0x49D, 0x000000F0,
0x49E, 0x00000000,
0x49F, 0x00000006,
0x4A0, 0x000000E0,
0x4A1, 0x00000003,
0x4A2, 0x00000000,
0x4A3, 0x00000040,
0x4A4, 0x00000015,
0x4A5, 0x000000F0,
0x4A6, 0x00000000,
0x4A7, 0x00000006,
0x4A8, 0x000000E0,
0x4A9, 0x00000000,
0x4AA, 0x00000000,
0x4AB, 0x00000000,
0x7DA, 0x00000008,
0x1448, 0x00000006,
0x144A, 0x00000006,
0x144C, 0x00000006,
0x144E, 0x00000006,
0x4C8, 0x000000FF,
0x4C9, 0x00000008,
0x4CA, 0x0000003C,
0x4CB, 0x0000003C,
0x4CC, 0x000000FF,
0x4CD, 0x000000FF,
0x4CE, 0x00000001,
0x4CF, 0x00000008,
0x500, 0x00000026,
0x501, 0x000000A2,
0x502, 0x0000002F,
0x503, 0x00000000,
0x504, 0x00000028,
0x505, 0x000000A3,
0x506, 0x0000005E,
0x507, 0x00000000,
0x508, 0x0000002B,
0x509, 0x000000A4,
0x50A, 0x0000005E,
0x50B, 0x00000000,
0x50C, 0x0000004F,
0x50D, 0x000000A4,
0x50E, 0x00000000,
0x50F, 0x00000000,
0x512, 0x0000001C,
0x514, 0x0000000A,
0x516, 0x0000000A,
0x521, 0x0000002F,
0x525, 0x00000047,
0x550, 0x00000010,
0x551, 0x00000010,
0x559, 0x00000002,
0x55C, 0x00000064,
0x55D, 0x000000FF,
0x577, 0x00000003,
0x5BE, 0x00000064,
0x604, 0x00000001,
0x605, 0x00000030,
0x607, 0x00000001,
0x608, 0x0000000E,
0x609, 0x0000002A,
0x60A, 0x00000000,
0x60C, 0x00000018,
0x60D, 0x00000050,
0x6A0, 0x000000FF,
0x6A1, 0x000000FF,
0x6A2, 0x000000FF,
0x6A3, 0x000000FF,
0x6A4, 0x000000FF,
0x6A5, 0x000000FF,
0x6DE, 0x00000084,
0x620, 0x000000FF,
0x621, 0x000000FF,
0x622, 0x000000FF,
0x623, 0x000000FF,
0x624, 0x000000FF,
0x625, 0x000000FF,
0x626, 0x000000FF,
0x627, 0x000000FF,
0x638, 0x00000064,
0x63C, 0x0000000A,
0x63D, 0x0000000A,
0x63E, 0x0000000E,
0x63F, 0x0000000E,
0x640, 0x00000040,
0x642, 0x00000040,
0x643, 0x00000000,
0x652, 0x000000C8,
0x66E, 0x00000005,
0x700, 0x00000021,
0x701, 0x00000043,
0x702, 0x00000065,
0x703, 0x00000087,
0x708, 0x00000021,
0x709, 0x00000043,
0x70A, 0x00000065,
0x70B, 0x00000087,
0x718, 0x00000040,
0x7D5, 0x000000BC,
0x7D8, 0x00000028,
0x7D9, 0x00000000,
0x7DA, 0x0000000B,
};
void
odm_read_and_config_mp_8814a_mac_reg(struct dm_struct *dm)
{
u32 i = 0;
u8 c_cond;
boolean is_matched = true, is_skipped = false;
u32 array_len =
sizeof(array_mp_8814a_mac_reg) / sizeof(u32);
u32 *array = (u32 *)array_mp_8814a_mac_reg;
u32 v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0;
u32 a1 = 0, a2 = 0, a3 = 0, a4 = 0;
PHYDM_DBG(dm, ODM_COMP_INIT, "===> %s\n", __func__);
while ((i + 1) < array_len) {
v1 = array[i];
v2 = array[i + 1];
if (v1 & (BIT(31) | BIT(30))) {/*positive & negative condition*/
if (v1 & BIT(31)) {/* positive condition*/
c_cond =
(u8)((v1 & (BIT(29) | BIT(28))) >> 28);
if (c_cond == COND_ENDIF) {/*end*/
is_matched = true;
is_skipped = false;
PHYDM_DBG(dm, ODM_COMP_INIT, "ENDIF\n");
} else if (c_cond == COND_ELSE) { /*else*/
is_matched = is_skipped ? false : true;
PHYDM_DBG(dm, ODM_COMP_INIT, "ELSE\n");
} else {/*if , else if*/
pre_v1 = v1;
pre_v2 = v2;
PHYDM_DBG(dm, ODM_COMP_INIT,
"IF or ELSE IF\n");
}
} else if (v1 & BIT(30)) { /*negative condition*/
if (!is_skipped) {
a1 = pre_v1; a2 = pre_v2;
a3 = v1; a4 = v2;
if (check_positive(dm,
a1, a2, a3, a4)) {
is_matched = true;
is_skipped = true;
} else {
is_matched = false;
is_skipped = false;
}
} else {
is_matched = false;
}
}
} else {
if (is_matched)
odm_config_mac_8814a(dm, v1, (u8)v2);
}
i = i + 2;
}
}
u32
odm_get_version_mp_8814a_mac_reg(void)
{
return 110;
}
#endif /* end of HWIMG_SUPPORT*/
3rd/devourer/hal/phydm/rtl8814a/halhwimg8814a_mac.h
+42
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@@ -0,0 +1,42 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
/*Image2HeaderVersion: R3 1.5.6*/
#if (RTL8814A_SUPPORT == 1)
#ifndef __INC_MP_MAC_HW_IMG_8814A_H
#define __INC_MP_MAC_HW_IMG_8814A_H
/******************************************************************************
* mac_reg.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8814a_mac_reg(struct dm_struct *dm);
u32 odm_get_version_mp_8814a_mac_reg(void);
#endif
#endif /* end of HWIMG_SUPPORT*/
3rd/devourer/hal/phydm/rtl8814a/phydm_regconfig8814a.c
+244
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@@ -0,0 +1,244 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#include "mp_precomp.h"
#include "../phydm_precomp.h"
#if (RTL8814A_SUPPORT == 1)
void odm_config_rf_reg_8814a(struct dm_struct *dm, u32 addr, u32 data,
enum rf_path rf_path, u32 reg_addr)
{
if (dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) {
if (addr == 0xfe || addr == 0xffe)
phydm_set_reg_by_fw(dm,
PHYDM_HALMAC_CMD_DELAY_MS,
reg_addr,
data,
RFREGOFFSETMASK,
rf_path,
50);
else {
phydm_set_reg_by_fw(dm,
PHYDM_HALMAC_CMD_RF_W,
reg_addr,
data,
RFREGOFFSETMASK,
rf_path,
0);
phydm_set_reg_by_fw(dm,
PHYDM_HALMAC_CMD_DELAY_US,
reg_addr,
data,
RFREGOFFSETMASK,
rf_path,
1);
}
} else {
if (addr == 0xfe || addr == 0xffe) {
#ifdef CONFIG_LONG_DELAY_ISSUE
ODM_sleep_ms(50);
#else
ODM_delay_ms(50);
#endif
} else {
odm_set_rf_reg(dm, rf_path, reg_addr, RFREGOFFSETMASK, data);
/* Add 1us delay between BB/RF register setting. */
ODM_delay_us(1);
}
}
}
void odm_config_rf_radio_a_8814a(struct dm_struct *dm, u32 addr, u32 data)
{
u32 content = 0x1000; /* RF_Content: radioa_txt */
u32 maskfor_phy_set = (u32)(content & 0xE000);
odm_config_rf_reg_8814a(dm, addr, data, RF_PATH_A, addr | maskfor_phy_set);
PHYDM_DBG(dm, ODM_COMP_INIT,
"===> odm_config_rf_with_header_file: [RadioA] %08X %08X\n",
addr, data);
}
void odm_config_rf_radio_b_8814a(struct dm_struct *dm, u32 addr, u32 data)
{
u32 content = 0x1001; /* RF_Content: radiob_txt */
u32 maskfor_phy_set = (u32)(content & 0xE000);
odm_config_rf_reg_8814a(dm, addr, data, RF_PATH_B, addr | maskfor_phy_set);
PHYDM_DBG(dm, ODM_COMP_INIT,
"===> odm_config_rf_with_header_file: [RadioB] %08X %08X\n",
addr, data);
}
void odm_config_rf_radio_c_8814a(struct dm_struct *dm, u32 addr, u32 data)
{
u32 content = 0x1001; /* RF_Content: radiob_txt */
u32 maskfor_phy_set = (u32)(content & 0xE000);
odm_config_rf_reg_8814a(dm, addr, data, RF_PATH_C, addr | maskfor_phy_set);
PHYDM_DBG(dm, ODM_COMP_INIT,
"===> odm_config_rf_with_header_file: [RadioC] %08X %08X\n",
addr, data);
}
void odm_config_rf_radio_d_8814a(struct dm_struct *dm, u32 addr, u32 data)
{
u32 content = 0x1001; /* RF_Content: radiob_txt */
u32 maskfor_phy_set = (u32)(content & 0xE000);
odm_config_rf_reg_8814a(dm, addr, data, RF_PATH_D, addr | maskfor_phy_set);
PHYDM_DBG(dm, ODM_COMP_INIT,
"===> odm_config_rf_with_header_file: [RadioD] %08X %08X\n",
addr, data);
}
void odm_config_mac_8814a(struct dm_struct *dm, u32 addr, u8 data)
{
if (dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD)
phydm_set_reg_by_fw(dm,
PHYDM_HALMAC_CMD_MAC_W8,
addr,
data,
0,
(enum rf_path)0,
0);
else
odm_write_1byte(dm, addr, data);
PHYDM_DBG(dm, ODM_COMP_INIT,
"===> odm_config_mac_with_header_file: [MAC_REG] %08X %08X\n",
addr, data);
}
void odm_config_bb_agc_8814a(struct dm_struct *dm, u32 addr, u32 bitmask,
u32 data)
{
if (dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD)
phydm_set_reg_by_fw(dm,
PHYDM_HALMAC_CMD_BB_W32,
addr,
data,
bitmask,
(enum rf_path)0,
0);
else
odm_set_bb_reg(dm, addr, bitmask, data);
PHYDM_DBG(dm, ODM_COMP_INIT,
"===> odm_config_bb_with_header_file: [AGC_TAB] %08X %08X\n",
addr, data);
}
void odm_config_bb_phy_reg_pg_8814a(struct dm_struct *dm, u32 band, u32 rf_path,
u32 tx_num, u32 addr, u32 bitmask, u32 data)
{
if (addr == 0xfe || addr == 0xffe)
#ifdef CONFIG_LONG_DELAY_ISSUE
ODM_sleep_ms(50);
#else
ODM_delay_ms(50);
#endif
else {
#if (DM_ODM_SUPPORT_TYPE & ODM_CE)
phy_store_tx_power_by_rate(dm->adapter, band, rf_path, tx_num, addr, bitmask, data);
#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
PHY_StoreTxPowerByRate(dm->adapter, band, rf_path, tx_num, addr, bitmask, data);
#endif
}
PHYDM_DBG(dm, ODM_COMP_INIT,
"===> odm_config_bb_with_header_file: [PHY_REG] %08X %08X %08X\n",
addr, bitmask, data);
}
void odm_config_bb_phy_8814a(struct dm_struct *dm, u32 addr, u32 bitmask,
u32 data)
{
if (dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) {
u32 delay_time = 0;
if (addr >= 0xf9 && addr <= 0xfe) {
if (addr == 0xfe || addr == 0xfb)
delay_time = 50;
else if (addr == 0xfd || addr == 0xfa)
delay_time = 5;
else
delay_time = 1;
if (addr >= 0xfc && addr <= 0xfe)
phydm_set_reg_by_fw(dm,
PHYDM_HALMAC_CMD_DELAY_MS,
addr,
data,
bitmask,
(enum rf_path)0,
delay_time);
else
phydm_set_reg_by_fw(dm,
PHYDM_HALMAC_CMD_DELAY_US,
addr,
data,
bitmask,
(enum rf_path)0,
delay_time);
} else
phydm_set_reg_by_fw(dm,
PHYDM_HALMAC_CMD_BB_W32,
addr,
data,
bitmask,
(enum rf_path)0,
0);
} else {
if (addr == 0xfe)
#ifdef CONFIG_LONG_DELAY_ISSUE
ODM_sleep_ms(50);
#else
ODM_delay_ms(50);
#endif
else if (addr == 0xfd)
ODM_delay_ms(5);
else if (addr == 0xfc)
ODM_delay_ms(1);
else if (addr == 0xfb)
ODM_delay_us(50);
else if (addr == 0xfa)
ODM_delay_us(5);
else if (addr == 0xf9)
ODM_delay_us(1);
else
odm_set_bb_reg(dm, addr, bitmask, data);
}
PHYDM_DBG(dm, ODM_COMP_INIT,
"===> odm_config_bb_with_header_file: [PHY_REG] %08X %08X\n",
addr, data);
}
void odm_config_bb_txpwr_lmt_8814a(struct dm_struct *dm, u8 *regulation,
u8 *band, u8 *bandwidth, u8 *rate_section,
u8 *rf_path, u8 *channel, u8 *power_limit)
{
#if (DM_ODM_SUPPORT_TYPE & ODM_CE)
phy_set_tx_power_limit(dm, regulation, band,
bandwidth, rate_section, rf_path, channel, power_limit);
#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
PHY_SetTxPowerLimit(dm, regulation, band,
bandwidth, rate_section, rf_path, channel, power_limit);
#endif
}
#endif
3rd/devourer/hal/phydm/rtl8814a/phydm_regconfig8814a.h
+47
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@@ -0,0 +1,47 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef __INC_ODM_REGCONFIG_H_8814A
#define __INC_ODM_REGCONFIG_H_8814A
#if (RTL8814A_SUPPORT == 1)
void odm_config_rf_reg_8814a(struct dm_struct *dm, u32 addr, u32 data,
enum rf_path rf_path, u32 reg_addr);
void odm_config_rf_radio_a_8814a(struct dm_struct *dm, u32 addr, u32 data);
void odm_config_rf_radio_b_8814a(struct dm_struct *dm, u32 addr, u32 data);
void odm_config_rf_radio_c_8814a(struct dm_struct *dm, u32 addr, u32 data);
void odm_config_rf_radio_d_8814a(struct dm_struct *dm, u32 addr, u32 data);
void odm_config_mac_8814a(struct dm_struct *dm, u32 addr, u8 data);
void odm_config_bb_agc_8814a(struct dm_struct *dm, u32 addr, u32 bitmask,
u32 data);
void odm_config_bb_phy_reg_pg_8814a(struct dm_struct *dm, u32 band, u32 rf_path,
u32 tx_num, u32 addr, u32 bitmask,
u32 data);
void odm_config_bb_phy_8814a(struct dm_struct *dm, u32 addr, u32 bitmask,
u32 data);
void odm_config_bb_txpwr_lmt_8814a(struct dm_struct *dm, u8 *regulation,
u8 *band, u8 *bandwidth, u8 *rate_section,
u8 *rf_path, u8 *channel, u8 *power_limit);
#endif
#endif /* end of SUPPORT */
3rd/devourer/hal/phydm/rtl8814a/phydm_rtl8814a.c
+254
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@@ -0,0 +1,254 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
/* ************************************************************
* include files
* ************************************************************ */
#include "mp_precomp.h"
#include "../phydm_precomp.h"
#if (RTL8814A_SUPPORT == 1)
s8 phydm_cck_rssi_8814a(struct dm_struct *dm, u16 lna_idx, u8 vga_idx)
{
s8 rx_pwr_all = 0;
switch (lna_idx) {
case 7:
rx_pwr_all = -38 - (2 * vga_idx);
break;
case 5:
rx_pwr_all = -28 - (2 * vga_idx);
break;
case 3:
rx_pwr_all = -8 - (2 * vga_idx);
break;
case 2:
rx_pwr_all = -1 - (2 * vga_idx);
break;
default:
break;
}
return rx_pwr_all;
}
u8 phydm_spur_nbi_setting_8814a(struct dm_struct *dm)
{
u8 set_result = 0;
/*dm->channel means central frequency, so we can use 20M as input*/
if (dm->rfe_type == 0 || dm->rfe_type == 1 || dm->rfe_type == 6 ||
dm->rfe_type == 7) {
/*channel asked by RF Jeff*/
if (*dm->channel == 14)
set_result = phydm_nbi_setting(dm, FUNC_ENABLE,
*dm->channel, 40, 2480,
PHYDM_DONT_CARE);
else if (*dm->channel >= 4 && *dm->channel <= 8)
set_result = phydm_nbi_setting(dm, FUNC_ENABLE,
*dm->channel, 40, 2440,
PHYDM_DONT_CARE);
#if 0
else if (*dm->channel == 153)
set_result = phydm_nbi_setting(dm, FUNC_ENABLE,
*dm->channel, 20, 5760,
PHYDM_DONT_CARE);
else if (*dm->channel == 54)
set_result = phydm_nbi_setting(dm, FUNC_ENABLE,
*dm->channel, 40, 5280,
PHYDM_DONT_CARE);
else if (*dm->channel == 118)
set_result = phydm_nbi_setting(dm, FUNC_ENABLE,
*dm->channel, 40, 5600,
PHYDM_DONT_CARE);
else if (*dm->channel == 151)
set_result = phydm_nbi_setting(dm, FUNC_ENABLE,
*dm->channel, 40, 5760,
PHYDM_DONT_CARE);
else if (*dm->channel == 58)
set_result = phydm_nbi_setting(dm, FUNC_ENABLE,
*dm->channel, 80, 5280,
PHYDM_DONT_CARE);
else if (*dm->channel == 122)
set_result = phydm_nbi_setting(dm, FUNC_ENABLE,
*dm->channel, 80, 5600,
PHYDM_DONT_CARE);
else if (*dm->channel == 155)
set_result = phydm_nbi_setting(dm, FUNC_ENABLE,
*dm->channel, 80, 5760,
PHYDM_DONT_CARE);
#endif
else
set_result = phydm_nbi_setting(dm, FUNC_DISABLE,
*dm->channel, 40, 2440,
PHYDM_DONT_CARE);
}
PHYDM_DBG(dm, ODM_COMP_API, "%s, set_result = 0x%x, channel = %d\n",
__func__, set_result, *dm->channel);
dm->nbi_set_result = set_result;
return set_result;
}
void phydm_dynamic_nbi_switch_8814a(struct dm_struct *dm)
{
/*if rssi < 15%, disable nbi notch filter, if rssi > 20%, enable nbi notch filter*/
/*add by YuChen 20160218*/
if (dm->rfe_type == 0 || dm->rfe_type == 1 || dm->rfe_type == 6 || dm->rfe_type == 7) {
if (dm->nbi_set_result == PHYDM_SET_SUCCESS) {
if (dm->rssi_min <= 15)
odm_set_bb_reg(dm, R_0x87c, BIT(13), 0x0);
else if (dm->rssi_min >= 20)
odm_set_bb_reg(dm, R_0x87c, BIT(13), 0x1);
}
PHYDM_DBG(dm, ODM_COMP_API, "%s\n", __func__);
}
}
void phydm_hwsetting_8814a(struct dm_struct *dm)
{
phydm_dynamic_nbi_switch_8814a(dm);
}
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
/*@For normal driver we always use the FW method to configure TX power index to reduce I/O transaction.*/
void odm_set_tx_power_level8814(void *adapter, u8 channel, u8 pwr_lvl)
{
#if (DEV_BUS_TYPE == RT_USB_INTERFACE)
u32 i, j, k = 0;
u32 value[264] = {0};
u32 path = 0, power_index, txagc_table_wd = 0x00801000;
HAL_DATA_TYPE *hal_data = GET_HAL_DATA((PADAPTER)adapter);
u8 jaguar2_rates[][4] = {{MGN_1M, MGN_2M, MGN_5_5M, MGN_11M},
{MGN_6M, MGN_9M, MGN_12M, MGN_18M},
{MGN_24M, MGN_36M, MGN_48M, MGN_54M},
{MGN_MCS0, MGN_MCS1, MGN_MCS2, MGN_MCS3},
{MGN_MCS4, MGN_MCS5, MGN_MCS6, MGN_MCS7},
{MGN_MCS8, MGN_MCS9, MGN_MCS10, MGN_MCS11},
{MGN_MCS12, MGN_MCS13, MGN_MCS14, MGN_MCS15},
{MGN_MCS16, MGN_MCS17, MGN_MCS18, MGN_MCS19},
{MGN_MCS20, MGN_MCS21, MGN_MCS22, MGN_MCS23},
{MGN_VHT1SS_MCS0, MGN_VHT1SS_MCS1, MGN_VHT1SS_MCS2, MGN_VHT1SS_MCS3},
{MGN_VHT1SS_MCS4, MGN_VHT1SS_MCS5, MGN_VHT1SS_MCS6, MGN_VHT1SS_MCS7},
{MGN_VHT2SS_MCS8, MGN_VHT2SS_MCS9, MGN_VHT2SS_MCS0, MGN_VHT2SS_MCS1},
{MGN_VHT2SS_MCS2, MGN_VHT2SS_MCS3, MGN_VHT2SS_MCS4, MGN_VHT2SS_MCS5},
{MGN_VHT2SS_MCS6, MGN_VHT2SS_MCS7, MGN_VHT2SS_MCS8, MGN_VHT2SS_MCS9},
{MGN_VHT3SS_MCS0, MGN_VHT3SS_MCS1, MGN_VHT3SS_MCS2, MGN_VHT3SS_MCS3},
{MGN_VHT3SS_MCS4, MGN_VHT3SS_MCS5, MGN_VHT3SS_MCS6, MGN_VHT3SS_MCS7},
{MGN_VHT3SS_MCS8, MGN_VHT3SS_MCS9, 0, 0}};
for (path = RF_PATH_A; path <= RF_PATH_D; ++path) {
u8 usb_host = UsbModeQueryHubUsbType(adapter);
u8 usb_rfset = UsbModeQueryRfSet(adapter);
u8 usb_rf_type = RT_GetRFType((PADAPTER)adapter);
for (i = 0; i <= 16; i++) {
for (j = 0; j <= 3; j++) {
if (jaguar2_rates[i][j] == 0)
continue;
txagc_table_wd = 0x00801000;
power_index = (u32)PHY_GetTxPowerIndex(adapter, (u8)path, jaguar2_rates[i][j], hal_data->CurrentChannelBW, channel);
/*@for Query bus type to recude tx power.*/
if (usb_host != USB_MODE_U3 && usb_rfset == 1 && IS_HARDWARE_TYPE_8814AU(adapter) && usb_rf_type == RF_3T3R) {
if (channel <= 14) {
if (power_index >= 16)
power_index -= 16;
else
power_index = 0;
} else
power_index = 0;
}
if (pwr_lvl == tx_high_pwr_level_level1) {
if (power_index >= 0x10)
power_index -= 0x10;
else
power_index = 0;
} else if (pwr_lvl == tx_high_pwr_level_level2)
power_index = 0;
txagc_table_wd |= (path << 8) | MRateToHwRate(jaguar2_rates[i][j]) | (power_index << 24);
PHY_SetTxPowerIndexShadow(adapter, (u8)power_index, (u8)path, jaguar2_rates[i][j]);
value[k++] = txagc_table_wd;
}
}
}
if (((PADAPTER)adapter)->MgntInfo.bScanInProgress == false && ((PADAPTER)adapter)->MgntInfo.RegFWOffload == 2)
HalDownloadTxPowerLevel8814(adapter, value);
#endif
}
void odm_dynamic_tx_power_8814a(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
void *adapter = dm->adapter;
PMGNT_INFO mgnt_info = &((PADAPTER)adapter)->MgntInfo;
HAL_DATA_TYPE *hal_data = GET_HAL_DATA((PADAPTER)adapter);
s32 rssi = dm->rssi_min;
PHYDM_DBG(dm, DBG_DYN_TXPWR,
"[%s] Tx_Lv=%d, iot_action=%x DTP_en=%d\n",
__func__, hal_data->DynamicTxHighPowerLvl,
mgnt_info->IOTAction, mgnt_info->bDynamicTxPowerEnable);
/*STA not connected and AP not connected*/
if (!mgnt_info->bMediaConnect &&
hal_data->EntryMinUndecoratedSmoothedPWDB == 0) {
PHYDM_DBG(dm, DBG_DYN_TXPWR,
"Not connected to any reset power lvl\n");
hal_data->DynamicTxHighPowerLvl = tx_high_pwr_level_normal;
return;
}
if (!mgnt_info->bDynamicTxPowerEnable ||
mgnt_info->IOTAction & HT_IOT_ACT_DISABLE_HIGH_POWER) {
hal_data->DynamicTxHighPowerLvl = tx_high_pwr_level_normal;
} else {
/*Should we separate as 2.4G/5G band?*/
PHYDM_DBG(dm, DBG_DYN_TXPWR, "rssi_tmp = %d\n", rssi);
if (rssi >= TX_POWER_NEAR_FIELD_THRESH_LVL2) {
hal_data->DynamicTxHighPowerLvl = tx_high_pwr_level_level2;
} else if ((rssi < (TX_POWER_NEAR_FIELD_THRESH_LVL2 - 3)) &&
(rssi >= TX_POWER_NEAR_FIELD_THRESH_LVL1)) {
hal_data->DynamicTxHighPowerLvl = tx_high_pwr_level_level1;
} else if (rssi < (TX_POWER_NEAR_FIELD_THRESH_LVL1 - 5)) {
hal_data->DynamicTxHighPowerLvl = tx_high_pwr_level_normal;
}
PHYDM_DBG(dm, DBG_DYN_TXPWR, "TxHighPowerLvl = %d\n",
hal_data->DynamicTxHighPowerLvl);
}
if (hal_data->DynamicTxHighPowerLvl != hal_data->LastDTPLvl) {
PHYDM_DBG(dm, DBG_DYN_TXPWR, "channel = %d\n",
hal_data->CurrentChannel);
odm_set_tx_power_level8814(adapter, hal_data->CurrentChannel,
hal_data->DynamicTxHighPowerLvl);
}
PHYDM_DBG(dm, DBG_DYN_TXPWR, "channel = %d TXpower lvl=%d/%d\n",
hal_data->CurrentChannel, hal_data->LastDTPLvl,
hal_data->DynamicTxHighPowerLvl);
hal_data->LastDTPLvl = hal_data->DynamicTxHighPowerLvl;
}
#endif /* #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) */
#endif /* RTL8814A_SUPPORT == 1 */
3rd/devourer/hal/phydm/rtl8814a/phydm_rtl8814a.h
+26
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@@ -0,0 +1,26 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef __ODM_RTL8814A_H__
#define __ODM_RTL8814A_H__
#if (RTL8814A_SUPPORT == 1)
s8 phydm_cck_rssi_8814a(struct dm_struct *dm, u16 lna_idx, u8 vga_idx);
u8 phydm_spur_nbi_setting_8814a(struct dm_struct *dm);
void phydm_hwsetting_8814a(struct dm_struct *dm);
void odm_dynamic_tx_power_8814a(void *dm_void);
#endif
#endif
3rd/devourer/hal/phydm/rtl8814a/version_rtl8814a.h
+34
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@@ -0,0 +1,34 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
/*RTL8814A PHY Parameters*/
/*
[Caution]
Since 01/Aug/2015, the commit rules will be simplified.
You do not need to fill up the version.h anymore,
only the maintenance supervisor fills it before formal release.
*/
#define RELEASE_DATE_8814A 20181211
#define COMMIT_BY_8814A "BB_Dino"
#define RELEASE_VERSION_8814A 110
3rd/devourer/hal/phydm/rtl8821c/Hal8821c_PhyTables.c
+6824
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3rd/devourer/hal/phydm/rtl8821c/Hal8821c_PhyTables.h
+36
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@@ -0,0 +1,36 @@
/* Auto-generated by tools/extract_8822c_phy_tables.py.
* Source: morrownr/8821cu-20210916 (rtl8821c phydm, FW v5.12.0.4). */
#ifndef HAL8821C_PHYTABLES_H
#define HAL8821C_PHYTABLES_H
#include "drv_types.h"
#ifdef __cplusplus
extern "C" {
#endif
extern const u32 array_mp_8821c_agc_tab[];
extern const u32 array_mp_8821c_agc_tab_len;
extern const u32 array_mp_8821c_agc_tab_diff_wlg[];
extern const u32 array_mp_8821c_agc_tab_diff_wlg_len;
extern const u32 array_mp_8821c_agc_tab_diff_btg[];
extern const u32 array_mp_8821c_agc_tab_diff_btg_len;
extern const u32 array_mp_8821c_phy_reg[];
extern const u32 array_mp_8821c_phy_reg_len;
extern const u32 array_mp_8821c_phy_reg_mp[];
extern const u32 array_mp_8821c_phy_reg_mp_len;
extern const u32 array_mp_8821c_phy_reg_pg[];
extern const u32 array_mp_8821c_phy_reg_pg_len;
extern const u32 array_mp_8821c_phy_reg_pg_type0x28[];
extern const u32 array_mp_8821c_phy_reg_pg_type0x28_len;
extern const u32 array_mp_8821c_mac_reg[];
extern const u32 array_mp_8821c_mac_reg_len;
extern const u32 array_mp_8821c_radioa[];
extern const u32 array_mp_8821c_radioa_len;
#ifdef __cplusplus
}
#endif
#endif /* HAL8821C_PHYTABLES_H */
3rd/devourer/hal/phydm/rtl8821c/Hal8821c_TxpwrLmt.h
+162
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@@ -0,0 +1,162 @@
/* Auto-generated by tools/extract_8821c_txpwr_lmt.py — do not hand-edit.
* RTL8821C txpwr_lmt (regulatory TX-power limit), worldwide-min per cell.
* band 0=2.4G/1=5G; bw 0=20/1=40/2=80; sec 0=CCK/1=OFDM/2=HT/3=VHT;
* ntx 1..4; ch = channel; lmt in TXAGC index units (63 = no limit). */
#ifndef HAL8821C_TXPWRLMT_H
#define HAL8821C_TXPWRLMT_H
#include <stdint.h>
struct txpwr_lmt_ent_8821c {
uint8_t band, bw, sec, ntx, ch;
int8_t lmt;
};
static const struct txpwr_lmt_ent_8821c mp_8821c_txpwr_lmt_ww[] = {
{0, 0, 0, 1, 1, 30},
{0, 0, 0, 1, 2, 30},
{0, 0, 0, 1, 3, 30},
{0, 0, 0, 1, 4, 30},
{0, 0, 0, 1, 5, 30},
{0, 0, 0, 1, 6, 30},
{0, 0, 0, 1, 7, 30},
{0, 0, 0, 1, 8, 30},
{0, 0, 0, 1, 9, 30},
{0, 0, 0, 1, 10, 30},
{0, 0, 0, 1, 11, 30},
{0, 0, 0, 1, 12, 24},
{0, 0, 0, 1, 13, 16},
{0, 0, 0, 1, 14, 34},
{0, 0, 1, 1, 1, 30},
{0, 0, 1, 1, 2, 30},
{0, 0, 1, 1, 3, 30},
{0, 0, 1, 1, 4, 30},
{0, 0, 1, 1, 5, 30},
{0, 0, 1, 1, 6, 30},
{0, 0, 1, 1, 7, 30},
{0, 0, 1, 1, 8, 30},
{0, 0, 1, 1, 9, 30},
{0, 0, 1, 1, 10, 30},
{0, 0, 1, 1, 11, 30},
{0, 0, 1, 1, 12, 28},
{0, 0, 1, 1, 13, 16},
{0, 0, 1, 1, 14, 63},
{0, 0, 2, 1, 1, 26},
{0, 0, 2, 1, 2, 30},
{0, 0, 2, 1, 3, 30},
{0, 0, 2, 1, 4, 30},
{0, 0, 2, 1, 5, 30},
{0, 0, 2, 1, 6, 30},
{0, 0, 2, 1, 7, 30},
{0, 0, 2, 1, 8, 30},
{0, 0, 2, 1, 9, 30},
{0, 0, 2, 1, 10, 30},
{0, 0, 2, 1, 11, 28},
{0, 0, 2, 1, 12, 26},
{0, 0, 2, 1, 13, 12},
{0, 0, 2, 1, 14, 63},
{0, 1, 2, 1, 1, 63},
{0, 1, 2, 1, 2, 63},
{0, 1, 2, 1, 3, 26},
{0, 1, 2, 1, 4, 26},
{0, 1, 2, 1, 5, 30},
{0, 1, 2, 1, 6, 30},
{0, 1, 2, 1, 7, 30},
{0, 1, 2, 1, 8, 26},
{0, 1, 2, 1, 9, 26},
{0, 1, 2, 1, 10, 28},
{0, 1, 2, 1, 11, 20},
{0, 1, 2, 1, 12, 63},
{0, 1, 2, 1, 13, 63},
{0, 1, 2, 1, 14, 63},
{1, 0, 1, 1, 36, 27},
{1, 0, 1, 1, 40, 27},
{1, 0, 1, 1, 44, 27},
{1, 0, 1, 1, 48, 27},
{1, 0, 1, 1, 52, 16},
{1, 0, 1, 1, 56, 27},
{1, 0, 1, 1, 60, 27},
{1, 0, 1, 1, 64, 27},
{1, 0, 1, 1, 100, 27},
{1, 0, 1, 1, 104, 27},
{1, 0, 1, 1, 108, 27},
{1, 0, 1, 1, 112, 27},
{1, 0, 1, 1, 116, 27},
{1, 0, 1, 1, 120, 27},
{1, 0, 1, 1, 124, 27},
{1, 0, 1, 1, 128, 27},
{1, 0, 1, 1, 132, 27},
{1, 0, 1, 1, 136, 27},
{1, 0, 1, 1, 140, 27},
{1, 0, 1, 1, 144, 30},
{1, 0, 1, 1, 149, -63},
{1, 0, 1, 1, 153, -63},
{1, 0, 1, 1, 157, -63},
{1, 0, 1, 1, 161, -63},
{1, 0, 1, 1, 165, -63},
{1, 0, 2, 1, 36, 27},
{1, 0, 2, 1, 40, 27},
{1, 0, 2, 1, 44, 27},
{1, 0, 2, 1, 48, 26},
{1, 0, 2, 1, 52, 7},
{1, 0, 2, 1, 56, 27},
{1, 0, 2, 1, 60, 27},
{1, 0, 2, 1, 64, 27},
{1, 0, 2, 1, 100, 27},
{1, 0, 2, 1, 104, 27},
{1, 0, 2, 1, 108, 27},
{1, 0, 2, 1, 112, 27},
{1, 0, 2, 1, 116, 27},
{1, 0, 2, 1, 120, 27},
{1, 0, 2, 1, 124, 27},
{1, 0, 2, 1, 128, 27},
{1, 0, 2, 1, 132, 27},
{1, 0, 2, 1, 136, 27},
{1, 0, 2, 1, 140, 27},
{1, 0, 2, 1, 144, 27},
{1, 0, 2, 1, 149, -63},
{1, 0, 2, 1, 153, -63},
{1, 0, 2, 1, 157, -63},
{1, 0, 2, 1, 161, -63},
{1, 0, 2, 1, 165, -63},
{1, 1, 2, 1, 38, 22},
{1, 1, 2, 1, 46, 27},
{1, 1, 2, 1, 54, 22},
{1, 1, 2, 1, 62, 23},
{1, 1, 2, 1, 102, 21},
{1, 1, 2, 1, 110, 27},
{1, 1, 2, 1, 118, 27},
{1, 1, 2, 1, 126, 27},
{1, 1, 2, 1, 134, 27},
{1, 1, 2, 1, 142, 29},
{1, 1, 2, 1, 151, -63},
{1, 1, 2, 1, 159, -63},
{1, 2, 3, 1, 42, 19},
{1, 2, 3, 1, 58, 22},
{1, 2, 3, 1, 106, 18},
{1, 2, 3, 1, 122, 26},
{1, 2, 3, 1, 138, 28},
{1, 2, 3, 1, 155, -63},
};
static const unsigned mp_8821c_txpwr_lmt_ww_len =
sizeof(mp_8821c_txpwr_lmt_ww) / sizeof(mp_8821c_txpwr_lmt_ww[0]);
/* WW-min limit for (band, bw, sec, ntx, ch): exact channel, else nearest
* channel in the same (band,bw,sec,ntx), else 63 (no limit). */
static inline int hal8821c_txpwr_lmt(uint8_t band, uint8_t bw,
uint8_t sec, uint8_t ntx,
uint8_t ch) {
const struct txpwr_lmt_ent_8821c *t = mp_8821c_txpwr_lmt_ww;
int best = 63, best_d = 255;
for (unsigned i = 0; i < mp_8821c_txpwr_lmt_ww_len; i++) {
if (t[i].band != band || t[i].bw != bw || t[i].sec != sec ||
t[i].ntx != ntx)
continue;
if (t[i].ch == ch) return t[i].lmt;
int d = t[i].ch > ch ? t[i].ch - ch : ch - t[i].ch;
if (d < best_d) { best_d = d; best = t[i].lmt; }
}
return best;
}
#endif /* HAL8821C_TXPWRLMT_H */
3rd/devourer/hal/phydm/rtl8821c/halhwimg8821c_bb.c
+4579
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3rd/devourer/hal/phydm/rtl8821c/halhwimg8821c_mac.c
+321
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@@ -0,0 +1,321 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
/*Image2HeaderVersion: R3 1.5.10.1*/
#include "mp_precomp.h"
#include "../phydm_precomp.h"
#if (RTL8821C_SUPPORT == 1)
static boolean
check_positive(struct dm_struct *dm,
const u32 condition1,
const u32 condition2,
const u32 condition3,
const u32 condition4
)
{
u32 cond1 = condition1, cond2 = condition2,
cond3 = condition3, cond4 = condition4;
u8 cut_version_for_para =
(dm->cut_version == ODM_CUT_A) ? 15 : dm->cut_version;
u8 pkg_type_for_para =
(dm->package_type == 0) ? 15 : dm->package_type;
u32 driver1 = cut_version_for_para << 24 |
(dm->support_interface & 0xF0) << 16 |
dm->support_platform << 16 |
pkg_type_for_para << 12 |
(dm->support_interface & 0x0F) << 8 |
dm->rfe_type;
u32 driver2 = (dm->type_glna & 0xFF) << 0 |
(dm->type_gpa & 0xFF) << 8 |
(dm->type_alna & 0xFF) << 16 |
(dm->type_apa & 0xFF) << 24;
u32 driver3 = 0;
u32 driver4 = (dm->type_glna & 0xFF00) >> 8 |
(dm->type_gpa & 0xFF00) |
(dm->type_alna & 0xFF00) << 8 |
(dm->type_apa & 0xFF00) << 16;
PHYDM_DBG(dm, ODM_COMP_INIT,
"===> %s (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n",
__func__, cond1, cond2, cond3, cond4);
PHYDM_DBG(dm, ODM_COMP_INIT,
"===> %s (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n",
__func__, driver1, driver2, driver3, driver4);
PHYDM_DBG(dm, ODM_COMP_INIT,
" (Platform, Interface) = (0x%X, 0x%X)\n",
dm->support_platform, dm->support_interface);
PHYDM_DBG(dm, ODM_COMP_INIT, " (RFE, Package) = (0x%X, 0x%X)\n",
dm->rfe_type, dm->package_type);
/*============== value Defined Check ===============*/
/*cut version [27:24] need to do value check*/
if (((cond1 & 0x0F000000) != 0) &&
((cond1 & 0x0F000000) != (driver1 & 0x0F000000)))
return false;
/*pkg type [15:12] need to do value check*/
if (((cond1 & 0x0000F000) != 0) &&
((cond1 & 0x0000F000) != (driver1 & 0x0000F000)))
return false;
/*interface [11:8] need to do value check*/
if (((cond1 & 0x00000F00) != 0) &&
((cond1 & 0x00000F00) != (driver1 & 0x00000F00)))
return false;
/*=============== Bit Defined Check ================*/
/* We don't care [31:28] */
cond1 &= 0x000000FF;
driver1 &= 0x000000FF;
if (cond1 == driver1)
return true;
else
return false;
}
/******************************************************************************
* mac_reg.TXT
******************************************************************************/
const u32 array_mp_8821c_mac_reg[] = {
0x010, 0x00000043,
0x025, 0x0000001D,
0x026, 0x000000CE,
0x04F, 0x00000001,
0x029, 0x000000F9,
0x420, 0x00000080,
0x421, 0x0000000F,
0x428, 0x0000000A,
0x429, 0x00000010,
0x430, 0x00000000,
0x431, 0x00000000,
0x432, 0x00000000,
0x433, 0x00000001,
0x434, 0x00000004,
0x435, 0x00000005,
0x436, 0x00000007,
0x437, 0x00000008,
0x43C, 0x00000004,
0x43D, 0x00000005,
0x43E, 0x00000007,
0x43F, 0x00000008,
0x440, 0x0000005D,
0x441, 0x00000001,
0x442, 0x00000000,
0x444, 0x00000010,
0x445, 0x000000F0,
0x446, 0x00000001,
0x447, 0x000000FE,
0x448, 0x00000000,
0x449, 0x00000000,
0x44A, 0x00000000,
0x44B, 0x00000040,
0x44C, 0x00000010,
0x44D, 0x000000F0,
0x44E, 0x0000003F,
0x44F, 0x00000000,
0x450, 0x00000000,
0x451, 0x00000000,
0x452, 0x00000000,
0x453, 0x00000040,
0x455, 0x00000070,
0x45E, 0x00000004,
0x49C, 0x00000010,
0x49D, 0x000000F0,
0x49E, 0x00000000,
0x49F, 0x00000006,
0x4A0, 0x000000E0,
0x4A1, 0x00000003,
0x4A2, 0x00000000,
0x4A3, 0x00000040,
0x4A4, 0x00000015,
0x4A5, 0x000000F0,
0x4A6, 0x00000000,
0x4A7, 0x00000006,
0x4A8, 0x000000E0,
0x4A9, 0x00000000,
0x4AA, 0x00000000,
0x4AB, 0x00000000,
0x7DA, 0x00000008,
0x1448, 0x00000006,
0x144A, 0x00000006,
0x144C, 0x00000006,
0x144E, 0x00000006,
0x4C8, 0x000000FF,
0x4C9, 0x00000008,
0x4CC, 0x000000FF,
0x4CD, 0x000000FF,
0x4CE, 0x00000001,
0x4CF, 0x00000008,
0x500, 0x00000026,
0x501, 0x000000A2,
0x502, 0x0000002F,
0x503, 0x00000000,
0x504, 0x00000028,
0x505, 0x000000A3,
0x506, 0x0000005E,
0x507, 0x00000000,
0x508, 0x0000002B,
0x509, 0x000000A4,
0x50A, 0x0000005E,
0x50B, 0x00000000,
0x50C, 0x0000004F,
0x50D, 0x000000A4,
0x50E, 0x00000000,
0x50F, 0x00000000,
0x512, 0x0000001C,
0x514, 0x0000000A,
0x516, 0x0000000A,
0x521, 0x0000002F,
0x525, 0x0000004F,
0x551, 0x00000010,
0x559, 0x00000002,
0x55C, 0x00000050,
0x55D, 0x000000FF,
0x577, 0x0000000B,
0x578, 0x00000014,
0x579, 0x00000014,
0x57A, 0x00000014,
0x5BE, 0x00000064,
0x605, 0x00000030,
0x608, 0x0000000E,
0x609, 0x00000022,
0x60C, 0x00000018,
0x6A0, 0x000000FF,
0x6A1, 0x000000FF,
0x6A2, 0x000000FF,
0x6A3, 0x000000FF,
0x6A4, 0x000000FF,
0x6A5, 0x000000FF,
0x6DE, 0x00000084,
0x620, 0x000000FF,
0x621, 0x000000FF,
0x622, 0x000000FF,
0x623, 0x000000FF,
0x624, 0x000000FF,
0x625, 0x000000FF,
0x626, 0x000000FF,
0x627, 0x000000FF,
0x638, 0x00000050,
0x63C, 0x0000000A,
0x63D, 0x0000000A,
0x63E, 0x0000000E,
0x63F, 0x0000000E,
0x640, 0x00000040,
0x642, 0x00000040,
0x643, 0x00000000,
0x652, 0x000000C8,
0x66E, 0x00000005,
0x700, 0x00000021,
0x701, 0x00000043,
0x702, 0x00000065,
0x703, 0x00000087,
0x708, 0x00000021,
0x709, 0x00000043,
0x70A, 0x00000065,
0x70B, 0x00000087,
0x718, 0x00000040,
0x7D4, 0x00000098,
};
void
odm_read_and_config_mp_8821c_mac_reg(struct dm_struct *dm)
{
u32 i = 0;
u8 c_cond;
boolean is_matched = true, is_skipped = false;
u32 array_len =
sizeof(array_mp_8821c_mac_reg) / sizeof(u32);
u32 *array = (u32 *)array_mp_8821c_mac_reg;
u32 v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0;
u32 a1 = 0, a2 = 0, a3 = 0, a4 = 0;
PHYDM_DBG(dm, ODM_COMP_INIT, "===> %s\n", __func__);
while ((i + 1) < array_len) {
v1 = array[i];
v2 = array[i + 1];
if (v1 & (BIT(31) | BIT(30))) {/*positive & negative condition*/
if (v1 & BIT(31)) {/* positive condition*/
c_cond =
(u8)((v1 & (BIT(29) | BIT(28))) >> 28);
if (c_cond == COND_ENDIF) {/*end*/
is_matched = true;
is_skipped = false;
PHYDM_DBG(dm, ODM_COMP_INIT, "ENDIF\n");
} else if (c_cond == COND_ELSE) { /*else*/
is_matched = is_skipped ? false : true;
PHYDM_DBG(dm, ODM_COMP_INIT, "ELSE\n");
} else {/*if , else if*/
pre_v1 = v1;
pre_v2 = v2;
PHYDM_DBG(dm, ODM_COMP_INIT,
"IF or ELSE IF\n");
}
} else if (v1 & BIT(30)) { /*negative condition*/
if (!is_skipped) {
a1 = pre_v1; a2 = pre_v2;
a3 = v1; a4 = v2;
if (check_positive(dm,
a1, a2, a3, a4)) {
is_matched = true;
is_skipped = true;
} else {
is_matched = false;
is_skipped = false;
}
} else {
is_matched = false;
}
}
} else {
if (is_matched)
odm_config_mac_8821c(dm, v1, (u8)v2);
}
i = i + 2;
}
}
u32
odm_get_version_mp_8821c_mac_reg(void)
{
return 62;
}
#endif /* end of HWIMG_SUPPORT*/
3rd/devourer/hal/phydm/rtl8822b/Hal8822b_PhyTables.c
+21726
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File diff suppressed because it is too large Load Diff
3rd/devourer/hal/phydm/rtl8822b/Hal8822b_PhyTables.h
+50
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@@ -0,0 +1,50 @@
/* Auto-generated by tools/extract_8822c_phy_tables.py.
* Source: OpenHD/rtl88x2bu (rtl8822b phydm). */
#ifndef HAL8822B_PHYTABLES_H
#define HAL8822B_PHYTABLES_H
#include "drv_types.h"
#ifdef __cplusplus
extern "C" {
#endif
extern const u32 array_mp_8822b_agc_tab[];
extern const u32 array_mp_8822b_agc_tab_len;
extern const u32 array_mp_8822b_phy_reg[];
extern const u32 array_mp_8822b_phy_reg_len;
extern const u32 array_mp_8822b_phy_reg_pg[];
extern const u32 array_mp_8822b_phy_reg_pg_len;
extern const u32 array_mp_8822b_phy_reg_pg_type12[];
extern const u32 array_mp_8822b_phy_reg_pg_type12_len;
extern const u32 array_mp_8822b_phy_reg_pg_type15[];
extern const u32 array_mp_8822b_phy_reg_pg_type15_len;
extern const u32 array_mp_8822b_phy_reg_pg_type16[];
extern const u32 array_mp_8822b_phy_reg_pg_type16_len;
extern const u32 array_mp_8822b_phy_reg_pg_type17[];
extern const u32 array_mp_8822b_phy_reg_pg_type17_len;
extern const u32 array_mp_8822b_phy_reg_pg_type18[];
extern const u32 array_mp_8822b_phy_reg_pg_type18_len;
extern const u32 array_mp_8822b_phy_reg_pg_type19[];
extern const u32 array_mp_8822b_phy_reg_pg_type19_len;
extern const u32 array_mp_8822b_phy_reg_pg_type2[];
extern const u32 array_mp_8822b_phy_reg_pg_type2_len;
extern const u32 array_mp_8822b_phy_reg_pg_type3[];
extern const u32 array_mp_8822b_phy_reg_pg_type3_len;
extern const u32 array_mp_8822b_phy_reg_pg_type4[];
extern const u32 array_mp_8822b_phy_reg_pg_type4_len;
extern const u32 array_mp_8822b_phy_reg_pg_type5[];
extern const u32 array_mp_8822b_phy_reg_pg_type5_len;
extern const u32 array_mp_8822b_mac_reg[];
extern const u32 array_mp_8822b_mac_reg_len;
extern const u32 array_mp_8822b_radioa[];
extern const u32 array_mp_8822b_radioa_len;
extern const u32 array_mp_8822b_radiob[];
extern const u32 array_mp_8822b_radiob_len;
#ifdef __cplusplus
}
#endif
#endif /* HAL8822B_PHYTABLES_H */
3rd/devourer/hal/phydm/rtl8822b/Hal8822b_TxpwrLmt.h
+436
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@@ -0,0 +1,436 @@
/* Auto-generated by tools/extract_8822b_txpwr_lmt.py — do not hand-edit.
* RTL8822B txpwr_lmt (regulatory TX-power limit), worldwide-min per cell.
* band 0=2.4G/1=5G; bw 0=20/1=40/2=80; sec 0=CCK/1=OFDM/2=HT/3=VHT;
* ntx 1..4; ch = channel; lmt in TXAGC index units (63 = no limit). */
#ifndef HAL8822B_TXPWRLMT_H
#define HAL8822B_TXPWRLMT_H
#include <stdint.h>
struct txpwr_lmt_ent {
uint8_t band, bw, sec, ntx, ch;
int8_t lmt;
};
static const struct txpwr_lmt_ent mp_8822b_txpwr_lmt_ww[] = {
{0, 0, 0, 1, 1, 28},
{0, 0, 0, 1, 2, 28},
{0, 0, 0, 1, 3, 28},
{0, 0, 0, 1, 4, 28},
{0, 0, 0, 1, 5, 28},
{0, 0, 0, 1, 6, 28},
{0, 0, 0, 1, 7, 28},
{0, 0, 0, 1, 8, 28},
{0, 0, 0, 1, 9, 28},
{0, 0, 0, 1, 10, 28},
{0, 0, 0, 1, 11, 28},
{0, 0, 0, 1, 12, 26},
{0, 0, 0, 1, 13, 20},
{0, 0, 0, 1, 14, 32},
{0, 0, 1, 1, 1, 26},
{0, 0, 1, 1, 2, 30},
{0, 0, 1, 1, 3, 30},
{0, 0, 1, 1, 4, 30},
{0, 0, 1, 1, 5, 30},
{0, 0, 1, 1, 6, 30},
{0, 0, 1, 1, 7, 30},
{0, 0, 1, 1, 8, 30},
{0, 0, 1, 1, 9, 30},
{0, 0, 1, 1, 10, 30},
{0, 0, 1, 1, 11, 28},
{0, 0, 1, 1, 12, 22},
{0, 0, 1, 1, 13, 14},
{0, 0, 1, 1, 14, 63},
{0, 0, 2, 1, 1, 26},
{0, 0, 2, 1, 2, 30},
{0, 0, 2, 1, 3, 30},
{0, 0, 2, 1, 4, 30},
{0, 0, 2, 1, 5, 30},
{0, 0, 2, 1, 6, 30},
{0, 0, 2, 1, 7, 30},
{0, 0, 2, 1, 8, 30},
{0, 0, 2, 1, 9, 30},
{0, 0, 2, 1, 10, 30},
{0, 0, 2, 1, 11, 26},
{0, 0, 2, 1, 12, 20},
{0, 0, 2, 1, 13, 14},
{0, 0, 2, 1, 14, 63},
{0, 0, 2, 2, 1, 18},
{0, 0, 2, 2, 2, 18},
{0, 0, 2, 2, 3, 18},
{0, 0, 2, 2, 4, 18},
{0, 0, 2, 2, 5, 18},
{0, 0, 2, 2, 6, 18},
{0, 0, 2, 2, 7, 18},
{0, 0, 2, 2, 8, 18},
{0, 0, 2, 2, 9, 18},
{0, 0, 2, 2, 10, 18},
{0, 0, 2, 2, 11, 18},
{0, 0, 2, 2, 12, 18},
{0, 0, 2, 2, 13, 14},
{0, 0, 2, 2, 14, 63},
{0, 1, 2, 1, 1, 63},
{0, 1, 2, 1, 2, 63},
{0, 1, 2, 1, 3, 26},
{0, 1, 2, 1, 4, 26},
{0, 1, 2, 1, 5, 30},
{0, 1, 2, 1, 6, 30},
{0, 1, 2, 1, 7, 30},
{0, 1, 2, 1, 8, 26},
{0, 1, 2, 1, 9, 26},
{0, 1, 2, 1, 10, 20},
{0, 1, 2, 1, 11, 14},
{0, 1, 2, 1, 12, 63},
{0, 1, 2, 1, 13, 63},
{0, 1, 2, 1, 14, 63},
{0, 1, 2, 2, 1, 63},
{0, 1, 2, 2, 2, 63},
{0, 1, 2, 2, 3, 18},
{0, 1, 2, 2, 4, 18},
{0, 1, 2, 2, 5, 18},
{0, 1, 2, 2, 6, 18},
{0, 1, 2, 2, 7, 18},
{0, 1, 2, 2, 8, 18},
{0, 1, 2, 2, 9, 18},
{0, 1, 2, 2, 10, 18},
{0, 1, 2, 2, 11, 14},
{0, 1, 2, 2, 12, 63},
{0, 1, 2, 2, 13, 63},
{0, 1, 2, 2, 14, 63},
{1, 0, 1, 1, 36, 30},
{1, 0, 1, 1, 40, 30},
{1, 0, 1, 1, 44, 30},
{1, 0, 1, 1, 48, 30},
{1, 0, 1, 1, 52, 28},
{1, 0, 1, 1, 56, 28},
{1, 0, 1, 1, 60, 28},
{1, 0, 1, 1, 64, 28},
{1, 0, 1, 1, 100, 26},
{1, 0, 1, 1, 104, 32},
{1, 0, 1, 1, 108, 32},
{1, 0, 1, 1, 112, 32},
{1, 0, 1, 1, 116, 32},
{1, 0, 1, 1, 120, 32},
{1, 0, 1, 1, 124, 32},
{1, 0, 1, 1, 128, 32},
{1, 0, 1, 1, 132, 32},
{1, 0, 1, 1, 136, 32},
{1, 0, 1, 1, 140, 28},
{1, 0, 1, 1, 144, 28},
{1, 0, 1, 1, 149, 32},
{1, 0, 1, 1, 153, 32},
{1, 0, 1, 1, 157, 32},
{1, 0, 1, 1, 161, 32},
{1, 0, 1, 1, 165, 32},
{1, 0, 2, 1, 36, 28},
{1, 0, 2, 1, 40, 28},
{1, 0, 2, 1, 44, 28},
{1, 0, 2, 1, 48, 28},
{1, 0, 2, 1, 52, 28},
{1, 0, 2, 1, 56, 28},
{1, 0, 2, 1, 60, 28},
{1, 0, 2, 1, 64, 28},
{1, 0, 2, 1, 100, 26},
{1, 0, 2, 1, 104, 32},
{1, 0, 2, 1, 108, 32},
{1, 0, 2, 1, 112, 32},
{1, 0, 2, 1, 116, 32},
{1, 0, 2, 1, 120, 32},
{1, 0, 2, 1, 124, 32},
{1, 0, 2, 1, 128, 32},
{1, 0, 2, 1, 132, 32},
{1, 0, 2, 1, 136, 32},
{1, 0, 2, 1, 140, 26},
{1, 0, 2, 1, 144, 26},
{1, 0, 2, 1, 149, 32},
{1, 0, 2, 1, 153, 32},
{1, 0, 2, 1, 157, 32},
{1, 0, 2, 1, 161, 32},
{1, 0, 2, 1, 165, 32},
{1, 0, 2, 2, 36, 20},
{1, 0, 2, 2, 40, 20},
{1, 0, 2, 2, 44, 20},
{1, 0, 2, 2, 48, 20},
{1, 0, 2, 2, 52, 20},
{1, 0, 2, 2, 56, 20},
{1, 0, 2, 2, 60, 20},
{1, 0, 2, 2, 64, 20},
{1, 0, 2, 2, 100, 20},
{1, 0, 2, 2, 104, 20},
{1, 0, 2, 2, 108, 20},
{1, 0, 2, 2, 112, 20},
{1, 0, 2, 2, 116, 20},
{1, 0, 2, 2, 120, 20},
{1, 0, 2, 2, 124, 20},
{1, 0, 2, 2, 128, 20},
{1, 0, 2, 2, 132, 20},
{1, 0, 2, 2, 136, 20},
{1, 0, 2, 2, 140, 20},
{1, 0, 2, 2, 144, 26},
{1, 0, 2, 2, 149, 32},
{1, 0, 2, 2, 153, 32},
{1, 0, 2, 2, 157, 32},
{1, 0, 2, 2, 161, 32},
{1, 0, 2, 2, 165, 32},
{1, 1, 2, 1, 38, 22},
{1, 1, 2, 1, 46, 30},
{1, 1, 2, 1, 54, 30},
{1, 1, 2, 1, 62, 24},
{1, 1, 2, 1, 102, 24},
{1, 1, 2, 1, 110, 30},
{1, 1, 2, 1, 118, 30},
{1, 1, 2, 1, 126, 30},
{1, 1, 2, 1, 134, 30},
{1, 1, 2, 1, 142, 30},
{1, 1, 2, 1, 151, 30},
{1, 1, 2, 1, 159, 30},
{1, 1, 2, 2, 38, 20},
{1, 1, 2, 2, 46, 20},
{1, 1, 2, 2, 54, 20},
{1, 1, 2, 2, 62, 20},
{1, 1, 2, 2, 102, 20},
{1, 1, 2, 2, 110, 20},
{1, 1, 2, 2, 118, 20},
{1, 1, 2, 2, 126, 20},
{1, 1, 2, 2, 134, 20},
{1, 1, 2, 2, 142, 30},
{1, 1, 2, 2, 151, 30},
{1, 1, 2, 2, 159, 30},
{1, 2, 3, 1, 42, 20},
{1, 2, 3, 1, 58, 20},
{1, 2, 3, 1, 106, 20},
{1, 2, 3, 1, 122, 30},
{1, 2, 3, 1, 138, 30},
{1, 2, 3, 1, 155, 30},
{1, 2, 3, 2, 42, 18},
{1, 2, 3, 2, 58, 18},
{1, 2, 3, 2, 106, 20},
{1, 2, 3, 2, 122, 20},
{1, 2, 3, 2, 138, 30},
{1, 2, 3, 2, 155, 30},
};
static const unsigned mp_8822b_txpwr_lmt_ww_len = sizeof(mp_8822b_txpwr_lmt_ww) / sizeof(mp_8822b_txpwr_lmt_ww[0]);
static const struct txpwr_lmt_ent mp_8822b_txpwr_lmt_type3_ww[] = {
{0, 0, 0, 1, 1, 28},
{0, 0, 0, 1, 2, 28},
{0, 0, 0, 1, 3, 28},
{0, 0, 0, 1, 4, 28},
{0, 0, 0, 1, 5, 28},
{0, 0, 0, 1, 6, 28},
{0, 0, 0, 1, 7, 28},
{0, 0, 0, 1, 8, 28},
{0, 0, 0, 1, 9, 28},
{0, 0, 0, 1, 10, 28},
{0, 0, 0, 1, 11, 28},
{0, 0, 0, 1, 12, 26},
{0, 0, 0, 1, 13, 20},
{0, 0, 0, 1, 14, 32},
{0, 0, 1, 1, 1, 26},
{0, 0, 1, 1, 2, 30},
{0, 0, 1, 1, 3, 30},
{0, 0, 1, 1, 4, 30},
{0, 0, 1, 1, 5, 30},
{0, 0, 1, 1, 6, 30},
{0, 0, 1, 1, 7, 30},
{0, 0, 1, 1, 8, 30},
{0, 0, 1, 1, 9, 30},
{0, 0, 1, 1, 10, 30},
{0, 0, 1, 1, 11, 28},
{0, 0, 1, 1, 12, 22},
{0, 0, 1, 1, 13, 14},
{0, 0, 1, 1, 14, 63},
{0, 0, 2, 1, 1, 26},
{0, 0, 2, 1, 2, 30},
{0, 0, 2, 1, 3, 30},
{0, 0, 2, 1, 4, 30},
{0, 0, 2, 1, 5, 30},
{0, 0, 2, 1, 6, 30},
{0, 0, 2, 1, 7, 30},
{0, 0, 2, 1, 8, 30},
{0, 0, 2, 1, 9, 30},
{0, 0, 2, 1, 10, 30},
{0, 0, 2, 1, 11, 26},
{0, 0, 2, 1, 12, 20},
{0, 0, 2, 1, 13, 14},
{0, 0, 2, 1, 14, 63},
{0, 0, 2, 2, 1, 18},
{0, 0, 2, 2, 2, 18},
{0, 0, 2, 2, 3, 18},
{0, 0, 2, 2, 4, 18},
{0, 0, 2, 2, 5, 18},
{0, 0, 2, 2, 6, 18},
{0, 0, 2, 2, 7, 18},
{0, 0, 2, 2, 8, 18},
{0, 0, 2, 2, 9, 18},
{0, 0, 2, 2, 10, 18},
{0, 0, 2, 2, 11, 18},
{0, 0, 2, 2, 12, 18},
{0, 0, 2, 2, 13, 14},
{0, 0, 2, 2, 14, 63},
{0, 1, 2, 1, 1, 63},
{0, 1, 2, 1, 2, 63},
{0, 1, 2, 1, 3, 26},
{0, 1, 2, 1, 4, 26},
{0, 1, 2, 1, 5, 30},
{0, 1, 2, 1, 6, 30},
{0, 1, 2, 1, 7, 30},
{0, 1, 2, 1, 8, 26},
{0, 1, 2, 1, 9, 26},
{0, 1, 2, 1, 10, 20},
{0, 1, 2, 1, 11, 14},
{0, 1, 2, 1, 12, 63},
{0, 1, 2, 1, 13, 63},
{0, 1, 2, 1, 14, 63},
{0, 1, 2, 2, 1, 63},
{0, 1, 2, 2, 2, 63},
{0, 1, 2, 2, 3, 18},
{0, 1, 2, 2, 4, 18},
{0, 1, 2, 2, 5, 18},
{0, 1, 2, 2, 6, 18},
{0, 1, 2, 2, 7, 18},
{0, 1, 2, 2, 8, 18},
{0, 1, 2, 2, 9, 18},
{0, 1, 2, 2, 10, 18},
{0, 1, 2, 2, 11, 14},
{0, 1, 2, 2, 12, 63},
{0, 1, 2, 2, 13, 63},
{0, 1, 2, 2, 14, 63},
{1, 0, 1, 1, 36, 30},
{1, 0, 1, 1, 40, 30},
{1, 0, 1, 1, 44, 30},
{1, 0, 1, 1, 48, 30},
{1, 0, 1, 1, 52, 28},
{1, 0, 1, 1, 56, 28},
{1, 0, 1, 1, 60, 28},
{1, 0, 1, 1, 64, 28},
{1, 0, 1, 1, 100, 26},
{1, 0, 1, 1, 104, 32},
{1, 0, 1, 1, 108, 32},
{1, 0, 1, 1, 112, 32},
{1, 0, 1, 1, 116, 32},
{1, 0, 1, 1, 120, 32},
{1, 0, 1, 1, 124, 32},
{1, 0, 1, 1, 128, 32},
{1, 0, 1, 1, 132, 32},
{1, 0, 1, 1, 136, 32},
{1, 0, 1, 1, 140, 28},
{1, 0, 1, 1, 144, 28},
{1, 0, 1, 1, 149, 32},
{1, 0, 1, 1, 153, 32},
{1, 0, 1, 1, 157, 32},
{1, 0, 1, 1, 161, 32},
{1, 0, 1, 1, 165, 32},
{1, 0, 2, 1, 36, 28},
{1, 0, 2, 1, 40, 28},
{1, 0, 2, 1, 44, 28},
{1, 0, 2, 1, 48, 28},
{1, 0, 2, 1, 52, 28},
{1, 0, 2, 1, 56, 28},
{1, 0, 2, 1, 60, 28},
{1, 0, 2, 1, 64, 28},
{1, 0, 2, 1, 100, 26},
{1, 0, 2, 1, 104, 32},
{1, 0, 2, 1, 108, 32},
{1, 0, 2, 1, 112, 32},
{1, 0, 2, 1, 116, 32},
{1, 0, 2, 1, 120, 32},
{1, 0, 2, 1, 124, 32},
{1, 0, 2, 1, 128, 32},
{1, 0, 2, 1, 132, 32},
{1, 0, 2, 1, 136, 32},
{1, 0, 2, 1, 140, 26},
{1, 0, 2, 1, 144, 26},
{1, 0, 2, 1, 149, 32},
{1, 0, 2, 1, 153, 32},
{1, 0, 2, 1, 157, 32},
{1, 0, 2, 1, 161, 32},
{1, 0, 2, 1, 165, 32},
{1, 0, 2, 2, 36, 20},
{1, 0, 2, 2, 40, 20},
{1, 0, 2, 2, 44, 20},
{1, 0, 2, 2, 48, 20},
{1, 0, 2, 2, 52, 20},
{1, 0, 2, 2, 56, 20},
{1, 0, 2, 2, 60, 20},
{1, 0, 2, 2, 64, 20},
{1, 0, 2, 2, 100, 20},
{1, 0, 2, 2, 104, 20},
{1, 0, 2, 2, 108, 20},
{1, 0, 2, 2, 112, 20},
{1, 0, 2, 2, 116, 20},
{1, 0, 2, 2, 120, 20},
{1, 0, 2, 2, 124, 20},
{1, 0, 2, 2, 128, 20},
{1, 0, 2, 2, 132, 20},
{1, 0, 2, 2, 136, 20},
{1, 0, 2, 2, 140, 20},
{1, 0, 2, 2, 144, 26},
{1, 0, 2, 2, 149, 32},
{1, 0, 2, 2, 153, 32},
{1, 0, 2, 2, 157, 32},
{1, 0, 2, 2, 161, 32},
{1, 0, 2, 2, 165, 32},
{1, 1, 2, 1, 38, 22},
{1, 1, 2, 1, 46, 30},
{1, 1, 2, 1, 54, 30},
{1, 1, 2, 1, 62, 24},
{1, 1, 2, 1, 102, 24},
{1, 1, 2, 1, 110, 30},
{1, 1, 2, 1, 118, 30},
{1, 1, 2, 1, 126, 30},
{1, 1, 2, 1, 134, 30},
{1, 1, 2, 1, 142, 30},
{1, 1, 2, 1, 151, 30},
{1, 1, 2, 1, 159, 30},
{1, 1, 2, 2, 38, 20},
{1, 1, 2, 2, 46, 20},
{1, 1, 2, 2, 54, 20},
{1, 1, 2, 2, 62, 20},
{1, 1, 2, 2, 102, 20},
{1, 1, 2, 2, 110, 20},
{1, 1, 2, 2, 118, 20},
{1, 1, 2, 2, 126, 20},
{1, 1, 2, 2, 134, 20},
{1, 1, 2, 2, 142, 30},
{1, 1, 2, 2, 151, 30},
{1, 1, 2, 2, 159, 30},
{1, 2, 3, 1, 42, 20},
{1, 2, 3, 1, 58, 20},
{1, 2, 3, 1, 106, 20},
{1, 2, 3, 1, 122, 30},
{1, 2, 3, 1, 138, 30},
{1, 2, 3, 1, 155, 30},
{1, 2, 3, 2, 42, 18},
{1, 2, 3, 2, 58, 18},
{1, 2, 3, 2, 106, 20},
{1, 2, 3, 2, 122, 20},
{1, 2, 3, 2, 138, 30},
{1, 2, 3, 2, 155, 30},
};
static const unsigned mp_8822b_txpwr_lmt_type3_ww_len = sizeof(mp_8822b_txpwr_lmt_type3_ww) / sizeof(mp_8822b_txpwr_lmt_type3_ww[0]);
/* Lookup the WW-min limit for (rfe_type, band, bw, sec, ntx, ch). Falls
* back to the nearest channel in the same (band,bw,sec,ntx), then to 63
* (no limit) if the cell is absent. rfe_type 3 uses the type3 table; all
* others use the base table (matches phydm_hwconfig.c dispatch). */
static inline int hal8822b_txpwr_lmt(uint8_t rfe_type, uint8_t band,
uint8_t bw, uint8_t sec, uint8_t ntx,
uint8_t ch) {
const struct txpwr_lmt_ent *t = mp_8822b_txpwr_lmt_ww;
unsigned n = mp_8822b_txpwr_lmt_ww_len;
if (rfe_type == 3) { t = mp_8822b_txpwr_lmt_type3_ww;
n = mp_8822b_txpwr_lmt_type3_ww_len; }
int best = 63, best_d = 255;
for (unsigned i = 0; i < n; i++) {
if (t[i].band != band || t[i].bw != bw || t[i].sec != sec ||
t[i].ntx != ntx)
continue;
if (t[i].ch == ch) return t[i].lmt;
int d = t[i].ch > ch ? t[i].ch - ch : ch - t[i].ch;
if (d < best_d) { best_d = d; best = t[i].lmt; }
}
return best;
}
#endif /* HAL8822B_TXPWRLMT_H */
3rd/devourer/hal/phydm/rtl8822b/halhwimg8822b_bb.c
+13389
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3rd/devourer/hal/phydm/rtl8822b/halhwimg8822b_mac.c
+308
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@@ -0,0 +1,308 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
/*Image2HeaderVersion: R3 1.5.10*/
#include "mp_precomp.h"
#include "../phydm_precomp.h"
#if (RTL8822B_SUPPORT == 1)
static boolean
check_positive(struct dm_struct *dm,
const u32 condition1,
const u32 condition2,
const u32 condition3,
const u32 condition4
)
{
u32 cond1 = condition1, cond2 = condition2,
cond3 = condition3, cond4 = condition4;
u8 cut_version_for_para =
(dm->cut_version == ODM_CUT_A) ? 15 : dm->cut_version;
u8 pkg_type_for_para =
(dm->package_type == 0) ? 15 : dm->package_type;
u32 driver1 = cut_version_for_para << 24 |
(dm->support_interface & 0xF0) << 16 |
dm->support_platform << 16 |
pkg_type_for_para << 12 |
(dm->support_interface & 0x0F) << 8 |
dm->rfe_type;
u32 driver2 = (dm->type_glna & 0xFF) << 0 |
(dm->type_gpa & 0xFF) << 8 |
(dm->type_alna & 0xFF) << 16 |
(dm->type_apa & 0xFF) << 24;
u32 driver3 = 0;
u32 driver4 = (dm->type_glna & 0xFF00) >> 8 |
(dm->type_gpa & 0xFF00) |
(dm->type_alna & 0xFF00) << 8 |
(dm->type_apa & 0xFF00) << 16;
PHYDM_DBG(dm, ODM_COMP_INIT,
"===> %s (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n",
__func__, cond1, cond2, cond3, cond4);
PHYDM_DBG(dm, ODM_COMP_INIT,
"===> %s (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n",
__func__, driver1, driver2, driver3, driver4);
PHYDM_DBG(dm, ODM_COMP_INIT,
" (Platform, Interface) = (0x%X, 0x%X)\n",
dm->support_platform, dm->support_interface);
PHYDM_DBG(dm, ODM_COMP_INIT, " (RFE, Package) = (0x%X, 0x%X)\n",
dm->rfe_type, dm->package_type);
/*============== value Defined Check ===============*/
/*cut version [27:24] need to do value check*/
if (((cond1 & 0x0F000000) != 0) &&
((cond1 & 0x0F000000) != (driver1 & 0x0F000000)))
return false;
/*pkg type [15:12] need to do value check*/
if (((cond1 & 0x0000F000) != 0) &&
((cond1 & 0x0000F000) != (driver1 & 0x0000F000)))
return false;
/*interface [11:8] need to do value check*/
if (((cond1 & 0x00000F00) != 0) &&
((cond1 & 0x00000F00) != (driver1 & 0x00000F00)))
return false;
/*=============== Bit Defined Check ================*/
/* We don't care [31:28] */
cond1 &= 0x000000FF;
driver1 &= 0x000000FF;
if (cond1 == driver1)
return true;
else
return false;
}
/******************************************************************************
* mac_reg.TXT
******************************************************************************/
const u32 array_mp_8822b_mac_reg[] = {
0x029, 0x000000F9,
0x420, 0x00000080,
0x421, 0x0000001F,
0x428, 0x0000000A,
0x429, 0x00000010,
0x430, 0x00000000,
0x431, 0x00000000,
0x432, 0x00000000,
0x433, 0x00000001,
0x434, 0x00000004,
0x435, 0x00000005,
0x436, 0x00000007,
0x437, 0x00000008,
0x43C, 0x00000004,
0x43D, 0x00000005,
0x43E, 0x00000007,
0x43F, 0x00000008,
0x440, 0x0000005D,
0x441, 0x00000001,
0x442, 0x00000000,
0x444, 0x00000010,
0x445, 0x000000F0,
0x446, 0x00000001,
0x447, 0x000000FE,
0x448, 0x00000000,
0x449, 0x00000000,
0x44A, 0x00000000,
0x44B, 0x00000040,
0x44C, 0x00000010,
0x44D, 0x000000F0,
0x44E, 0x0000003F,
0x44F, 0x00000000,
0x450, 0x00000000,
0x451, 0x00000000,
0x452, 0x00000000,
0x453, 0x00000040,
0x455, 0x00000070,
0x45E, 0x00000004,
0x49C, 0x00000010,
0x49D, 0x000000F0,
0x49E, 0x00000000,
0x49F, 0x00000006,
0x4A0, 0x000000E0,
0x4A1, 0x00000003,
0x4A2, 0x00000000,
0x4A3, 0x00000040,
0x4A4, 0x00000015,
0x4A5, 0x000000F0,
0x4A6, 0x00000000,
0x4A7, 0x00000006,
0x4A8, 0x000000E0,
0x4A9, 0x00000000,
0x4AA, 0x00000000,
0x4AB, 0x00000000,
0x7DA, 0x00000008,
0x1448, 0x00000006,
0x144A, 0x00000006,
0x144C, 0x00000006,
0x144E, 0x00000006,
0x4C8, 0x000000FF,
0x4C9, 0x00000008,
0x4CA, 0x00000020,
0x4CB, 0x00000020,
0x4CC, 0x000000FF,
0x4CD, 0x000000FF,
0x4CE, 0x00000001,
0x4CF, 0x00000008,
0x500, 0x00000026,
0x501, 0x000000A2,
0x502, 0x0000002F,
0x503, 0x00000000,
0x504, 0x00000028,
0x505, 0x000000A3,
0x506, 0x0000005E,
0x507, 0x00000000,
0x508, 0x0000002B,
0x509, 0x000000A4,
0x50A, 0x0000005E,
0x50B, 0x00000000,
0x50C, 0x0000004F,
0x50D, 0x000000A4,
0x50E, 0x00000000,
0x50F, 0x00000000,
0x512, 0x0000001C,
0x514, 0x0000000A,
0x516, 0x0000000A,
0x521, 0x0000002F,
0x525, 0x0000004F,
0x551, 0x00000010,
0x559, 0x00000002,
0x55C, 0x00000050,
0x55D, 0x000000FF,
0x577, 0x0000000B,
0x5BE, 0x00000064,
0x605, 0x00000030,
0x608, 0x0000000E,
0x609, 0x00000022,
0x60C, 0x00000018,
0x6A0, 0x000000FF,
0x6A1, 0x000000FF,
0x6A2, 0x000000FF,
0x6A3, 0x000000FF,
0x6A4, 0x000000FF,
0x6A5, 0x000000FF,
0x6DE, 0x00000084,
0x620, 0x000000FF,
0x621, 0x000000FF,
0x622, 0x000000FF,
0x623, 0x000000FF,
0x624, 0x000000FF,
0x625, 0x000000FF,
0x626, 0x000000FF,
0x627, 0x000000FF,
0x638, 0x00000050,
0x63C, 0x0000000A,
0x63D, 0x0000000A,
0x63E, 0x0000000E,
0x63F, 0x0000000E,
0x640, 0x00000040,
0x642, 0x00000040,
0x643, 0x00000000,
0x652, 0x000000C8,
0x66E, 0x00000005,
0x718, 0x00000040,
0x7D4, 0x00000098,
};
void
odm_read_and_config_mp_8822b_mac_reg(struct dm_struct *dm)
{
u32 i = 0;
u8 c_cond;
boolean is_matched = true, is_skipped = false;
u32 array_len =
sizeof(array_mp_8822b_mac_reg) / sizeof(u32);
u32 *array = (u32 *)array_mp_8822b_mac_reg;
u32 v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0;
u32 a1 = 0, a2 = 0, a3 = 0, a4 = 0;
PHYDM_DBG(dm, ODM_COMP_INIT, "===> %s\n", __func__);
while ((i + 1) < array_len) {
v1 = array[i];
v2 = array[i + 1];
if (v1 & (BIT(31) | BIT(30))) {/*positive & negative condition*/
if (v1 & BIT(31)) {/* positive condition*/
c_cond =
(u8)((v1 & (BIT(29) | BIT(28))) >> 28);
if (c_cond == COND_ENDIF) {/*end*/
is_matched = true;
is_skipped = false;
PHYDM_DBG(dm, ODM_COMP_INIT, "ENDIF\n");
} else if (c_cond == COND_ELSE) { /*else*/
is_matched = is_skipped ? false : true;
PHYDM_DBG(dm, ODM_COMP_INIT, "ELSE\n");
} else {/*if , else if*/
pre_v1 = v1;
pre_v2 = v2;
PHYDM_DBG(dm, ODM_COMP_INIT,
"IF or ELSE IF\n");
}
} else if (v1 & BIT(30)) { /*negative condition*/
if (!is_skipped) {
a1 = pre_v1; a2 = pre_v2;
a3 = v1; a4 = v2;
if (check_positive(dm,
a1, a2, a3, a4)) {
is_matched = true;
is_skipped = true;
} else {
is_matched = false;
is_skipped = false;
}
} else {
is_matched = false;
}
}
} else {
if (is_matched)
odm_config_mac_8822b(dm, v1, (u8)v2);
}
i = i + 2;
}
}
u32
odm_get_version_mp_8822b_mac_reg(void)
{
return 117;
}
#endif /* end of HWIMG_SUPPORT*/
3rd/devourer/hal/phydm/rtl8822c/Hal8822c_IqkNctl.c
+1806
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3rd/devourer/hal/phydm/rtl8822c/Hal8822c_IqkNctl.h
+11
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#ifndef HAL8822C_IQK_NCTL_H
#define HAL8822C_IQK_NCTL_H
#include "basic_types.h"
/* GENERATED by tools/extract_8822c_iqk_nctl.py from the rtl88x2cu
* _iqk_nctl_8822c() — IQK NCTL microcode. {addr, mask, val}. */
struct iqk_nctl_write { u16 addr; u32 mask; u32 val; };
extern const struct iqk_nctl_write array_mp_8822c_iqk_nctl[];
extern const unsigned array_mp_8822c_iqk_nctl_len;
#endif
3rd/devourer/hal/phydm/rtl8822c/Hal8822c_PhyTables.c
+42360
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3rd/devourer/hal/phydm/rtl8822c/Hal8822c_PhyTables.h
+30
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@@ -0,0 +1,30 @@
/* Auto-generated by tools/extract_8822c_phy_tables.py.
* Source: libc0607/rtl88x2cu-20230728 (rtl8822c phydm). */
#ifndef HAL8822C_PHYTABLES_H
#define HAL8822C_PHYTABLES_H
#include "drv_types.h"
#ifdef __cplusplus
extern "C" {
#endif
extern const u32 array_mp_8822c_agc_tab[];
extern const u32 array_mp_8822c_agc_tab_len;
extern const u32 array_mp_8822c_phy_reg[];
extern const u32 array_mp_8822c_phy_reg_len;
extern const u32 array_mp_8822c_phy_reg_pg[];
extern const u32 array_mp_8822c_phy_reg_pg_len;
extern const u32 array_mp_8822c_radioa[];
extern const u32 array_mp_8822c_radioa_len;
extern const u32 array_mp_8822c_radiob[];
extern const u32 array_mp_8822c_radiob_len;
extern const u32 array_mp_8822c_cal_init[];
extern const u32 array_mp_8822c_cal_init_len;
#ifdef __cplusplus
}
#endif
#endif /* HAL8822C_PHYTABLES_H */
3rd/devourer/hal/phydm/rtl8822c/halhwimg8822c_bb.c
+3736
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3rd/devourer/hal/phydm/rtl8822e/Hal8822e_PhyTables.c
+20014
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3rd/devourer/hal/phydm/rtl8822e/Hal8822e_PhyTables.h
+32
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/* Auto-generated by tools/extract_8822c_phy_tables.py.
* Source: OpenHD/rtl88x2eu (rtl8822e phydm, FW v5.15.0.1-197). */
#ifndef HAL8822E_PHYTABLES_H
#define HAL8822E_PHYTABLES_H
#include "drv_types.h"
#ifdef __cplusplus
extern "C" {
#endif
extern const u32 array_mp_8822e_agc_tab[];
extern const u32 array_mp_8822e_agc_tab_len;
extern const u32 array_mp_8822e_phy_reg[];
extern const u32 array_mp_8822e_phy_reg_len;
extern const u32 array_mp_8822e_phy_reg_pg[];
extern const u32 array_mp_8822e_phy_reg_pg_len;
extern const u32 array_mp_8822e_phy_reg_pg_type5[];
extern const u32 array_mp_8822e_phy_reg_pg_type5_len;
extern const u32 array_mp_8822e_radioa[];
extern const u32 array_mp_8822e_radioa_len;
extern const u32 array_mp_8822e_radiob[];
extern const u32 array_mp_8822e_radiob_len;
extern const u32 array_mp_8822e_cal_init[];
extern const u32 array_mp_8822e_cal_init_len;
#ifdef __cplusplus
}
#endif
#endif /* HAL8822E_PHYTABLES_H */
3rd/devourer/hal/phydm/rtl8822e/halhwimg8822e_bb.c
+9222
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