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3rd/devourer/hal/halrf/g6/kestrel_halrf_glue.c

@@ -0,0 +1,208 @@
+/* C glue: owns an rf_info and drives the vendored halrf-G6 RF cals for both
+ * Kestrel chips. Compiled as C behind the shared shim. See the header. */
+#include "halrf_precomp.h"      /* full rf_info + halrf types + cal functions */
+#include "kestrel_halrf_glue.h"
+
+struct kestrel_halrf_ctx {
+  struct rf_info rf;
+  struct rtw_hal_com_t hal;
+  struct rtw_phl_com_t phl;
+};
+
+struct kestrel_halrf_ctx *kestrel_halrf_create(struct kestrel_halbb_bridge *br,
+                                               enum kestrel_chip chip,
+                                               unsigned char cut,
+                                               unsigned char rfe_type) {
+  struct kestrel_halrf_ctx *c =
+      (struct kestrel_halrf_ctx *)malloc(sizeof(struct kestrel_halrf_ctx));
+  if (!c)
+    return 0;
+  _os_mem_set(0, c, 0, sizeof(*c));
+
+  c->hal.drv_priv = br;          /* -> kestrel_halbb_bridge (BB + RF planes) */
+  c->hal.cv = cut;
+  /* halrf_cmn_info_self_init keys on chip_id: it derives rf->ic_type and
+   * wires the per-chip rfk ops + backup-register tables (rf_iqk_ops,
+   * rfk_iqk_info, backup_*_reg) the per-channel cals dereference. */
+  c->hal.chip_id =
+      chip == KESTREL_CHIP_8852B ? CHIP_WIFI6_8852B : CHIP_WIFI6_8852C;
+  c->phl.dev_cap.rfe_type = rfe_type;
+
+  c->rf.hal_com = &c->hal;
+  c->rf.phl_com = &c->phl;
+  c->rf.ic_type = chip == KESTREL_CHIP_8852B ? RF_RTL8852B : RF_RTL8852C;
+  halrf_cmn_info_self_init(&c->rf);
+  /* Enable the one-shot cals (LCK/RCK/DACK/RXDCK/IQK) but CLEAR the ongoing
+   * TX-power-TRACKING servos and the TSSI/DPK family: devourer runs a fixed
+   * BB dBm (halbb_set_txpwr_dbm), and the servos fight it. EVM-settled on the
+   * 8832CU (MCS7 data via streamtx, 8822CU monitor, matched RSSI ~78):
+   * TSSI+DPK enabled pulled on-air duty 74% -> 43% and medEVM -70 -> -59 —
+   * they degrade TX under the fixed-power model, so the gate is permanent
+   * until a TSSI-referenced power model exists. */
+  c->rf.support_ability = 0xffffffffu &
+      ~(HAL_RF_TX_PWR_TRACK | HAL_RF_TSSI_TRK | HAL_RF_DPK_TRACK |
+        HAL_RF_RXDCK_TRACK);
+  return c;
+}
+
+/* Defined in the vendored halrf_init.c but not declared in any halrf header. */
+void halrf_rfk_self_init(struct rf_info *rf);
+
+void kestrel_halrf_rfk_init(struct kestrel_halrf_ctx *ctx) {
+  if (!ctx)
+    return;
+  struct rf_info *rf = &ctx->rf;
+  /* Mirror the halrf_dm_init cal prologue that must run before the per-
+   * channel IQK. Loads the per-chip NCTL microcode into the one-shot cal
+   * engine (signals 0x55 @ 0xbff8 on cal completion), resets the per-cal RFK
+   * sub-state, runs the HW/SW SI reset (real a-die work on the 8852B via the
+   * bridge XSI plane; the dispatcher has no 8852C case), then the synth/
+   * filter cals (LCK/RCK) the per-channel cals depend on and the efuse
+   * trim/TSSI data. */
+  halrf_config_nctl_reg(rf);
+  halrf_rfk_self_init(rf);
+  halrf_si_reset(rf);
+  halrf_lck_trigger(rf);
+  halrf_rck_trigger(rf, HW_PHY_0);
+  /* Thermal / PA-bias / TSSI trim from efuse (kfree subsystem) — this is what
+   * TSSI's accuracy depends on. NOT halrf_tssi_get_efuse_ex: that loads the
+   * regulatory TX-power-LIMIT switch (mac_ax pwr-limit ops), a subsystem
+   * devourer deliberately omits (fixed-dBm txpwr, no regulatory enforcement)
+   * and whose absence does not affect the TSSI calibration's operation. */
+  halrf_get_efuse_trim(rf, HW_PHY_0);
+  /* Load the TSSI DE (differential-error) power targets from efuse — with the
+   * efuse_get_info bridge wired this populates tssi_info->tssi_efuse[] so a
+   * TSSI-referenced consumer reads real corrections. The mac_ax pwr-limit
+   * tail of halrf_tssi_get_efuse_EX is skipped by calling the per-chip loader
+   * directly. */
+  if (rf->ic_type == RF_RTL8852B) {
+#ifdef RF_8852B_SUPPORT
+    halrf_tssi_get_efuse_8852b(rf, HW_PHY_0);
+#endif
+  } else {
+#ifdef RF_8852C_SUPPORT
+    halrf_tssi_get_efuse_8852c(rf, HW_PHY_0);
+#endif
+  }
+}
+
+/* Apply the built-in radio A/B register tables via the vendor's own loader
+ * (halrf_config_radio: per-chip walk with the check-positive engine; each
+ * a-die write rides the bridge RF plane, d-die the BB window) and send the
+ * accumulated radio pages to the fw (classes 8/9 through the bridge
+ * send_h2c). Returns nonzero on success. */
+int kestrel_halrf_config_radio(struct kestrel_halrf_ctx *ctx) {
+  if (!ctx)
+    return 0;
+  return halrf_config_radio(&ctx->rf, HW_PHY_0) ? 1 : 0;
+}
+
+void kestrel_halrf_dac_cal(struct kestrel_halrf_ctx *ctx, unsigned char force) {
+  if (!ctx)
+    return;
+  /* Direct per-chip calls (the halrf_dack_trigger wrapper adds chlk_map/
+   * rfk-ops gates that can silently skip the cal at bring-up). */
+  if (ctx->rf.ic_type == RF_RTL8852B) {
+#ifdef RF_8852B_SUPPORT
+    halrf_dac_cal_8852b(&ctx->rf, force ? true : false);
+#endif
+  } else {
+#ifdef RF_8852C_SUPPORT
+    halrf_dac_cal_8852c(&ctx->rf, force ? true : false);
+#endif
+  }
+}
+
+void kestrel_halrf_rx_dck(struct kestrel_halrf_ctx *ctx) {
+  if (!ctx)
+    return;
+  if (ctx->rf.ic_type == RF_RTL8852B) {
+#ifdef RF_8852B_SUPPORT
+    halrf_rx_dck_8852b(&ctx->rf, HW_PHY_0, false);
+#endif
+  } else {
+#ifdef RF_8852C_SUPPORT
+    halrf_rx_dck_8852c(&ctx->rf, HW_PHY_0, false);
+#endif
+  }
+}
+
+void kestrel_halrf_set_ch(struct kestrel_halrf_ctx *ctx, unsigned char center_ch,
+                          unsigned char band, unsigned char bw) {
+  if (!ctx)
+    return;
+  struct rtw_chan_def *cd = &ctx->hal.band[HW_PHY_0].cur_chandef;
+  cd->center_ch = center_ch;
+  cd->chan = center_ch;
+  cd->band = (enum band_type)band;
+  cd->bw = (enum channel_width)bw;
+}
+
+void kestrel_halrf_ctl_band_ch_bw(struct kestrel_halrf_ctx *ctx,
+                                  unsigned char band, unsigned char central_ch,
+                                  unsigned char bw) {
+  if (!ctx)
+    return;
+  if (ctx->rf.ic_type == RF_RTL8852B) {
+    /* The core generics dispatch to halrf_ctrl_ch_8852b / halrf_ctrl_bw_8852b
+     * (halrf_ctl_band_ch_bw has no 8852B case); the 8852B's synth lock rides
+     * inside its ctrl_ch (s0_arfc18 relock priming). */
+    halrf_ctl_ch(&ctx->rf, HW_PHY_0, central_ch, (enum band_type)band);
+    halrf_ctl_bw(&ctx->rf, HW_PHY_0, (enum channel_width)bw);
+  } else {
+#ifdef RF_8852C_SUPPORT
+    halrf_ctl_band_ch_bw_8852c(&ctx->rf, HW_PHY_0, (enum band_type)band,
+                               central_ch, (enum channel_width)bw);
+#endif
+  }
+}
+
+void kestrel_halrf_lck(struct kestrel_halrf_ctx *ctx) {
+  /* 8852C-only synth relock; the 8852B locks inside its ctrl_ch. */
+#ifdef RF_8852C_SUPPORT
+  if (ctx && ctx->rf.ic_type == RF_RTL8852C)
+    halrf_lck_8852c(&ctx->rf);
+#else
+  (void)ctx;
+#endif
+}
+
+unsigned int kestrel_halrf_read_rf(struct kestrel_halrf_ctx *ctx,
+                                   unsigned char path, unsigned int addr) {
+  if (!ctx)
+    return 0;
+  return halrf_rrf(&ctx->rf, path, addr, MASKRF);
+}
+
+void kestrel_halrf_iqk(struct kestrel_halrf_ctx *ctx) {
+  if (ctx)
+    halrf_iqk(&ctx->rf, HW_PHY_0, true);
+}
+
+int kestrel_halrf_efuse_get_info(struct kestrel_halrf_ctx *ctx,
+                                 unsigned char *efuse_map, unsigned int id,
+                                 void *value, unsigned int size,
+                                 unsigned char autoload) {
+  if (!ctx || !efuse_map)
+    return 0;
+  bool ok = false;
+  if (ctx->rf.ic_type == RF_RTL8852B) {
+#ifdef RF_8852B_SUPPORT
+    ok = halrf_get_efuse_info_8852b(&ctx->rf, efuse_map,
+                                    (enum rtw_efuse_info)id, value, size,
+                                    autoload);
+#endif
+  } else {
+#ifdef RF_8852C_SUPPORT
+    ok = halrf_get_efuse_info_8852c(&ctx->rf, efuse_map,
+                                    (enum rtw_efuse_info)id, value, size,
+                                    autoload);
+#endif
+  }
+  return ok ? 1 : 0;
+}
+
+void kestrel_halrf_destroy(struct kestrel_halrf_ctx *ctx) {
+  if (ctx)
+    free(ctx);
+}

3rd/devourer/hal/halrf/g6/kestrel_halrf_glue.h

@@ -0,0 +1,98 @@
+/* C/C++ boundary for the vendored halrf-G6 RF calibrations (both Kestrel
+ * chips).
+ *
+ * Mirrors hal/halbb/g6/kestrel_halbb_glue.h: the vendored halrf C owns the
+ * full struct rf_info and the RF cal functions; this exposes an opaque handle
+ * so devourer's C++ can drive them without including any halrf header. Chip
+ * dispatch is the vendor core's own runtime switch (halrf_cmn_info_self_init
+ * wires the per-chip rfk ops/backup tables from hal_com->chip_id); the glue
+ * forks only the entry points that have no generic dispatcher. Register/RF
+ * access is routed back through the SAME kestrel_halbb_bridge (its read_rf /
+ * write_rf callbacks reach devourer's 3-wire RF path; read_xsi/write_xsi
+ * reach the XTAL-SI plane the 8852B's a-die SI reset needs).
+ */
+#ifndef KESTREL_HALRF_GLUE_H
+#define KESTREL_HALRF_GLUE_H
+
+#include "../../halbb/g6/shim/halbb_bridge.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct kestrel_halrf_ctx; /* opaque; owns an rf_info + hal_com/phl_com */
+
+struct kestrel_halrf_ctx *kestrel_halrf_create(struct kestrel_halbb_bridge *br,
+                                               enum kestrel_chip chip,
+                                               unsigned char cut,
+                                               unsigned char rfe_type);
+void kestrel_halrf_destroy(struct kestrel_halrf_ctx *ctx);
+
+/* One-time RFK bring-up — the halrf_dm_init cal prologue: load the NCTL
+ * one-shot micro-engine table (halrf_config_nctl_reg, per-chip image), reset
+ * the RFK sub-state (halrf_rfk_self_init), the HW/SW SI reset (halrf_si_reset
+ * — real work on the 8852B via the bridge XSI plane; its dispatch has no
+ * 8852C case), then the synth/filter cals (LCK/RCK) the per-channel cals
+ * depend on and the efuse trim/TSSI-DE data. Without the NCTL engine loaded,
+ * IQK's 0xbff8 one-shot-done poll never completes. Call once after create(),
+ * before the per-channel cals. */
+void kestrel_halrf_rfk_init(struct kestrel_halrf_ctx *ctx);
+
+/* Parse one logical-efuse field via the vendored per-chip map
+ * (halrf_get_efuse_info_<chip>). efuse_map = devourer's parsed logical efuse
+ * (>=0x600 bytes); id = enum rtw_efuse_info; autoload!=0 reads efuse (0 =
+ * defaults). Writes `size` bytes to value; returns nonzero on success. Wired
+ * to the shim's rtw_hal_efuse_get_info via the efuse_get_info bridge callback
+ * so the halrf TSSI-DE + thermal-trim efuse reads resolve. */
+int kestrel_halrf_efuse_get_info(struct kestrel_halrf_ctx *ctx,
+                                 unsigned char *efuse_map, unsigned int id,
+                                 void *value, unsigned int size,
+                                 unsigned char autoload);
+
+/* Apply the built-in radio A/B tables via the vendor loader
+ * (halrf_config_radio) + send the radio pages to the fw (bridge send_h2c,
+ * classes 8/9). Returns nonzero on success. Run after
+ * kestrel_halbb_init_reg. */
+int kestrel_halrf_config_radio(struct kestrel_halrf_ctx *ctx);
+
+/* DAC calibration (halrf_dac_cal_<chip>). force!=0 re-runs even if done. */
+void kestrel_halrf_dac_cal(struct kestrel_halrf_ctx *ctx, unsigned char force);
+
+/* RX DC calibration (halrf_rx_dck_<chip>), HW_PHY_0, non-AFE. */
+void kestrel_halrf_rx_dck(struct kestrel_halrf_ctx *ctx);
+
+/* Set the operating channel in rf_info (the per-channel cals — IQK/DPK/TSSI —
+ * read hal_com->band[HW_PHY_0].cur_chandef). band 0=2.4G,1=5G,2=6G; bw is
+ * enum channel_width. Call before kestrel_halrf_iqk. */
+void kestrel_halrf_set_ch(struct kestrel_halrf_ctx *ctx, unsigned char center_ch,
+                          unsigned char band, unsigned char bw);
+
+/* Vendored RF channel/band/bw tune. 8852C: halrf_ctl_band_ch_bw_8852c writes
+ * RF18 (DAV+DDV, both paths) for band(0=2.4/1=5/2=6G)+central_ch+bw incl. the
+ * path-B CAV workaround — follow with kestrel_halrf_lck to relock the synth
+ * (6 GHz VCO needs it). 8852B: the core's halrf_ctl_ch + halrf_ctl_bw
+ * generics (its synth lock rides inside halrf_ctrl_ch_8852b). */
+void kestrel_halrf_ctl_band_ch_bw(struct kestrel_halrf_ctx *ctx,
+                                  unsigned char band, unsigned char central_ch,
+                                  unsigned char bw);
+
+/* Synth relock (halrf_lck_8852c): sets RF 0x0[mode]=3 + 0x5=0 on both paths,
+ * runs the 0xd3-hold set_ch_lck on the current RF18, restores. 8852C-only —
+ * the 8852B locks inside its ctrl_ch. */
+void kestrel_halrf_lck(struct kestrel_halrf_ctx *ctx);
+
+/* Diagnostic: read a 20-bit RF register (halrf_rrf, MASKRF) on the given path
+ * via the vendored RF plane. Used to read the true synth-lock state after a
+ * tune — RF 0xb7[8] (LCK-done, 0=locked) and the RF18 readback — which the
+ * unreliable BB 0xc5[15] "synthLock" bit does not reflect. */
+unsigned int kestrel_halrf_read_rf(struct kestrel_halrf_ctx *ctx,
+                                   unsigned char path, unsigned int addr);
+
+/* IQ imbalance calibration (halrf_iqk core dispatcher), HW_PHY_0, forced.
+ * Per-channel; depends on the NCTL engine (kestrel_halrf_rfk_init). */
+void kestrel_halrf_iqk(struct kestrel_halrf_ctx *ctx);
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* KESTREL_HALRF_GLUE_H */

3rd/devourer/hal/halrf/g6/kestrel_halrf_helpers.c

@@ -0,0 +1,191 @@
+/* Stubs for the deferred halrf TX-power-limit subsystem (halrf_pwr_table.c /
+ * halrf_set_pwr_table_8852c.c are not vendored). Registering the 8852C RFK ops
+ * (rf_set_ops_8852c via halrf_cmn_info_self_init) makes --gc-sections keep the
+ * DPK/TSSI functions, which reference these power-limit lookups — even though
+ * only DACK/RX-DCK/IQK are actually driven. Return a benign default so linking
+ * succeeds; these paths are not executed. Compiled as C behind the shim. */
+#include "halrf_precomp.h"
+
+s8 halrf_get_power_limit(struct rf_info *rf, enum phl_phy_idx phy, u8 path,
+                         u16 rate, u8 bw, u8 bf, u8 ph, u8 ch) {
+  (void)rf; (void)phy; (void)path; (void)rate; (void)bw; (void)bf; (void)ph;
+  (void)ch;
+  return 40 * 4; /* ~40 dBm in the s(,2) unit — unused (DPK not run) */
+}
+
+/* halrf_init.c's halrf_init/halrf_dm_init reference the debug command parser
+ * and dbg-defaults init (halrf_dbg_cmd.c / halrf_dbg.c, not vendored). Neither
+ * entry point is called — devourer drives halrf through the glue exports — but
+ * linkers that resolve archive members before dead-stripping (MinGW ld, MSVC)
+ * still demand the symbols. Link-only no-ops. */
+void halrf_cmd_parser_init(struct rf_info *rf) { (void)rf; }
+void halrf_dbg_setting_init(struct rf_info *rf) { (void)rf; }
+
+/* ---- Link-only stubs for the un-vendored halrf subsystems ----------------
+ *
+ * The verbatim vendor TUs reference entry points that live in halrf .c files
+ * we deliberately do NOT vendor. No runtime path reaches them (the callers
+ * are un-driven vendor entry points kept verbatim), and GNU --gc-sections
+ * dead-strips the references on Linux — but MSVC and MinGW ld resolve
+ * archive members before dead-stripping, so the symbols must exist at link.
+ * Signatures match the vendored header prototypes exactly (this TU includes
+ * them via halrf_precomp.h). */
+
+/* Regulatory power tables (halrf_pwr_table.c, not vendored): the vendor's
+ * per-regulation power-by-rate / power-limit / power-limit-RU store + apply
+ * plane. Devourer's fixed-dBm TXAGC owns TX power instead. */
+bool halrf_set_power(struct rf_info *rf, enum phl_phy_idx phy,
+                     enum phl_pwr_table pwr_table) {
+  (void)rf; (void)phy; (void)pwr_table;
+  return false;
+}
+bool halrf_get_efuse_power_table_switch(struct rf_info *rf,
+                                        enum phl_phy_idx phy_idx) {
+  (void)rf; (void)phy_idx;
+  return false;
+}
+void halrf_power_by_rate_store_to_array(struct rf_info *rf,
+                                        u32 band, u32 tx_num, u32 rate_id,
+                                        u32 data) {
+  (void)rf; (void)band; (void)tx_num; (void)rate_id; (void)data;
+}
+void halrf_power_limit_store_to_array(struct rf_info *rf,
+                                      u8 regulation, u8 band, u8 bandwidth,
+                                      u8 rate, u8 tx_num, u8 beamforming,
+                                      u8 chnl, s8 val) {
+  (void)rf; (void)regulation; (void)band; (void)bandwidth; (void)rate;
+  (void)tx_num; (void)beamforming; (void)chnl; (void)val;
+}
+void halrf_power_limit_ru_store_to_array(struct rf_info *rf,
+                                         u8 band, u8 bandwidth, u8 tx_num,
+                                         u8 rate, u8 regulation, u8 chnl,
+                                         s8 val) {
+  (void)rf; (void)band; (void)bandwidth; (void)tx_num; (void)rate;
+  (void)regulation; (void)chnl; (void)val;
+}
+void halrf_power_limit_set_worldwide(struct rf_info *rf) { (void)rf; }
+void halrf_power_limit_ru_set_worldwide(struct rf_info *rf) { (void)rf; }
+void halrf_power_limit_set_ext_pwr_limit_table(struct rf_info *rf,
+                                               enum phl_phy_idx phy) {
+  (void)rf; (void)phy;
+}
+void halrf_power_limit_set_ext_pwr_limit_ru_table(struct rf_info *rf,
+                                                  enum phl_phy_idx phy) {
+  (void)rf; (void)phy;
+}
+void halrf_set_scan_power_table_to_fw_no_6g(struct rf_info *rf) { (void)rf; }
+void halrf_set_tpe_control(struct rf_info *rf) { (void)rf; }
+
+/* Per-chip power-table appliers (halrf_set_pwr_table_8852b.c /
+ * halrf_set_pwr_table_8852c.c, not vendored) — the MAC-side consumers of the
+ * regulatory tables above. */
+void halrf_set_fix_power_to_struct_8852b(struct rf_info *rf,
+                                         enum phl_phy_idx phy, s8 dbm) {
+  (void)rf; (void)phy; (void)dbm;
+}
+void halrf_set_ref_power_to_struct_8852b(struct rf_info *rf,
+                                         enum phl_phy_idx phy) {
+  (void)rf; (void)phy;
+}
+void halrf_set_tx_shape_8852b(struct rf_info *rf, u8 tx_shape_idx) {
+  (void)rf; (void)tx_shape_idx;
+}
+void halrf_pwr_by_rate_info_8852b(struct rf_info *rf, char input[][16],
+                                  u32 *_used, char *output, u32 *_out_len) {
+  (void)rf; (void)input; (void)_used; (void)output; (void)_out_len;
+}
+void halrf_pwr_limit_info_8852b(struct rf_info *rf, char input[][16],
+                                u32 *_used, char *output, u32 *_out_len) {
+  (void)rf; (void)input; (void)_used; (void)output; (void)_out_len;
+}
+void halrf_pwr_limit_ru_info_8852b(struct rf_info *rf, char input[][16],
+                                   u32 *_used, char *output, u32 *_out_len) {
+  (void)rf; (void)input; (void)_used; (void)output; (void)_out_len;
+}
+void halrf_set_fix_power_to_struct_8852c(struct rf_info *rf,
+                                         enum phl_phy_idx phy, s8 dbm) {
+  (void)rf; (void)phy; (void)dbm;
+}
+void halrf_set_ref_power_to_struct_8852c(struct rf_info *rf,
+                                         enum phl_phy_idx phy) {
+  (void)rf; (void)phy;
+}
+bool halrf_set_power_8852c(struct rf_info *rf, enum phl_phy_idx phy,
+                           enum phl_pwr_table pwr_table) {
+  (void)rf; (void)phy; (void)pwr_table;
+  return false;
+}
+void halrf_set_tx_shape_8852c(struct rf_info *rf, u8 tx_shape_idx) {
+  (void)rf; (void)tx_shape_idx;
+}
+void halrf_pwr_by_rate_info_8852c(struct rf_info *rf, char input[][16],
+                                  u32 *_used, char *output, u32 *_out_len,
+                                  enum phl_phy_idx phy) {
+  (void)rf; (void)input; (void)_used; (void)output; (void)_out_len; (void)phy;
+}
+void halrf_pwr_limit_info_8852c(struct rf_info *rf, char input[][16],
+                                u32 *_used, char *output, u32 *_out_len,
+                                enum phl_phy_idx phy) {
+  (void)rf; (void)input; (void)_used; (void)output; (void)_out_len; (void)phy;
+}
+void halrf_pwr_limit_ru_info_8852c(struct rf_info *rf, char input[][16],
+                                   u32 *_used, char *output, u32 *_out_len,
+                                   enum phl_phy_idx phy) {
+  (void)rf; (void)input; (void)_used; (void)output; (void)_out_len; (void)phy;
+}
+void halrf_set_bw_power_by_rate_offset_8852c(struct rf_info *rf,
+                                             u32 pwr_by_rate_bw_ofst) {
+  (void)rf; (void)pwr_by_rate_bw_ofst;
+}
+s8 halrf_get_pwr_by_rate_bw_control_8852c(struct rf_info *rf,
+                                          enum phl_phy_idx phy, u16 rate,
+                                          u32 band, s8 pwr_by_rate) {
+  (void)rf; (void)phy; (void)rate; (void)band;
+  return pwr_by_rate; /* identity — no BW offset applied */
+}
+
+/* PSD spectrum measurement (halrf_psd_8852b.c / halrf_psd_8852c.c, not
+ * vendored): the vendor MP-tool power-spectral-density capture. */
+void halrf_psd_init_8852b(struct rf_info *rf, enum phl_phy_idx phy,
+                          u8 path, u8 iq_path, u32 avg, u32 fft) {
+  (void)rf; (void)phy; (void)path; (void)iq_path; (void)avg; (void)fft;
+}
+void halrf_psd_restore_8852b(struct rf_info *rf, enum phl_phy_idx phy) {
+  (void)rf; (void)phy;
+}
+u32 halrf_psd_get_point_data_8852b(struct rf_info *rf, enum phl_phy_idx phy,
+                                   s32 point) {
+  (void)rf; (void)phy; (void)point;
+  return 0;
+}
+void halrf_psd_query_8852b(struct rf_info *rf, enum phl_phy_idx phy,
+                           u32 point, u32 start_point, u32 stop_point,
+                           u32 *outbuf) {
+  (void)rf; (void)phy; (void)point; (void)start_point; (void)stop_point;
+  (void)outbuf;
+}
+void halrf_psd_init_8852c(struct rf_info *rf, enum phl_phy_idx phy,
+                          u8 path, u8 iq_path, u32 avg, u32 fft) {
+  (void)rf; (void)phy; (void)path; (void)iq_path; (void)avg; (void)fft;
+}
+void halrf_psd_restore_8852c(struct rf_info *rf, enum phl_phy_idx phy) {
+  (void)rf; (void)phy;
+}
+u32 halrf_psd_get_point_data_8852c(struct rf_info *rf, enum phl_phy_idx phy,
+                                   s32 point) {
+  (void)rf; (void)phy; (void)point;
+  return 0;
+}
+void halrf_psd_query_8852c(struct rf_info *rf, enum phl_phy_idx phy,
+                           u32 point, u32 start_point, u32 stop_point,
+                           u32 *outbuf) {
+  (void)rf; (void)phy; (void)point; (void)start_point; (void)stop_point;
+  (void)outbuf;
+}
+
+/* TAS — time-averaged SAR (halrf_tas.c, not vendored). */
+void halrf_tas_pause(struct rf_info *rf, bool is_stop) {
+  (void)rf; (void)is_stop;
+}
+void halrf_tas_set_oft_scan_end(struct rf_info *rf) { (void)rf; }
+void halrf_tas_set_oft_to_zero_scan_start(struct rf_info *rf) { (void)rf; }

3rd/devourer/hal/halrf/g6/vendor/halrf.h

@@ -0,0 +1,498 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2020  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#ifndef __HALRF_H__
+#define __HALRF_H__
+
+/*@--------------------------[Define] ---------------------------------------*/
+
+#define HALRF_DZ_LOG
+#define HALRF_DBG_CNSL_CMD
+#define HALRF_KIP_CR_CHECK
+#define HALRF_EVENT_DUMP_LOG
+// #define HALRF_FT 
+// #define HALRF_MBIST 
+#define HALRF_MCC_DBCC
+
+/*H2C cmd ID*/
+/*Class 8*/
+/*Class 9*/
+/*Class a*/
+#define FWCMD_H2C_BACKUP_RFK 0
+#define FWCMD_H2C_RELOAD_RFK 1
+#define FWCMD_H2C_GET_MCCCH 2
+#define FWCMD_H2C_DPK_OFFLOAD 3
+#define FWCMD_H2C_IQK_OFFLOAD 4
+#define FWCMD_H2C_PWR_TBL_OFFLOAD 5
+#define FWCMD_H2C_FT_RFQ 8
+#define FWCMD_H2C_LPS_CFG 9
+#define FWCMD_H2C_RF_REG_FCS 0xA
+#define FWCMD_H2C_BB_REG_FCS 0xB
+#define FWCMD_H2C_KIP_REG_FCS 0xC
+#define FWCMD_H2C_RF_INIT_CFG 0xE
+
+/*C2H classid*/
+enum halrf_c2h_classid {
+	HALRF_C2H_RFK_LOG		= 0x8,
+	HALRF_MAX_C2HCMD
+};
+
+/*@-------------------------- Thermal protected threshold --------------------------*/
+
+#define THER_PROTECTED_THRESHOLD_AX 0x32
+#define THER_PROTECTED_RANGE_AX 0x2
+
+/*@--------------------------[Enum]------------------------------------------*/
+
+enum halrf_diag_event_level {
+	HALRF_DIAG_EVT_LVL_FATAL = 0,
+	HALRF_DIAG_EVT_LVL_CRITICAL = 1,
+	HALRF_DIAG_EVT_LVL_ERROR = 2
+};
+
+enum halrf_func_idx {
+	RF00_PWR_TRK = 0,
+	RF01_IQK = 1,
+	RF02_LCK = 2,
+	RF03_DPK = 3,
+	RF04_TXGAPK = 4,
+	RF05_DACK = 5,
+	RF06_DPK_TRK = 6,
+	RF07_2GBAND_SHIFT = 7,
+	RF08_RXDCK = 8,
+	RF09_RFK = 9,
+	RF10_RF_INIT = 10,
+	RF11_RF_POWER = 11,
+	RF12_RXGAINK = 12,
+	RF13_THER_TRIM = 13,
+	RF14_PABIAS_TRIM = 14,
+	RF15_TSSI_TRIM = 15,
+	RF16_PSD = 16,
+	RF17_TSSI_TRK = 17,
+	RF18_XTAL_TRK = 18,
+	RF19_TX_SHAPE = 19,
+	RF20_OP5K_TRK = 20,
+	RF21_OP5K = 21,
+	RF22_TPE_CTRL = 22,
+	RF23_RXDCK_TRK = 23,
+	RF26_RF_TAS = 26,
+	RF31_WATCHDOG = 31
+};
+
+enum halrf_rf_mode {
+	RF_SHUT_DOWN = 0x0,
+	RF_STANDBY = 0x1,
+	RF_TX = 0x2,
+	RF_RX = 0x3,
+	RF_TXIQK = 0x4,
+	RF_DPK = 0x5,
+	RF_RXK1 = 0x6,
+	RF_RXK2 = 0x7
+};
+
+enum halrf_rfe_src_sel {
+	HALRF_PAPE_RFM		= 0,
+	HALRF_GNT_BT_INV	= 1,
+	HALRF_LNA0N		= 2,
+	HALRF_LNAON_RFM		= 3,
+	HALRF_TRSW_RFM		= 4,
+	HALRF_TRSW_RFM_B	= 5,
+	HALRF_GNT_BT		= 6,
+	HALRF_ZERO		= 7,
+	HALRF_ANTSEL_0		= 8,
+	HALRF_ANTSEL_1		= 9,
+	HALRF_ANTSEL_2		= 0xa,
+	HALRF_ANTSEL_3		= 0xb,
+	HALRF_ANTSEL_4		= 0xc,
+	HALRF_ANTSEL_5		= 0xd,
+	HALRF_ANTSEL_6		= 0xe,
+	HALRF_ANTSEL_7		= 0xf
+};
+
+/*@=[HALRF supportability]=======================================*/
+enum halrf_ability {
+	HAL_RF_TX_PWR_TRACK = BIT(RF00_PWR_TRK),
+	HAL_RF_IQK = BIT(RF01_IQK),
+	HAL_RF_LCK = BIT(RF02_LCK),
+	HAL_RF_DPK = BIT(RF03_DPK),
+	HAL_RF_TXGAPK = BIT(RF04_TXGAPK),
+	HAL_RF_DACK = BIT(RF05_DACK),
+	HAL_RF_DPK_TRACK = BIT(RF06_DPK_TRK),
+	HAL_2GBAND_SHIFT = BIT(RF07_2GBAND_SHIFT),
+	HAL_RF_RXDCK = BIT(RF08_RXDCK),
+	HAL_RF_RXGAINK = BIT(RF12_RXGAINK),
+	HAL_RF_THER_TRIM = BIT(RF13_THER_TRIM),
+	HAL_RF_PABIAS_TRIM = BIT(RF14_PABIAS_TRIM),
+	HAL_RF_TSSI_TRIM = BIT(RF15_TSSI_TRIM),
+	HAL_RF_TSSI_TRK = BIT(RF17_TSSI_TRK),
+	HAL_RF_XTAL_TRACK = BIT(RF18_XTAL_TRK),
+	HAL_RF_TX_SHAPE = BIT(RF19_TX_SHAPE),
+	HAL_RF_OP5K_TRACK = BIT(RF20_OP5K_TRK),
+	HAL_RF_OP5K = BIT(RF21_OP5K),
+	HAL_RF_TPE_CTRL = BIT(RF22_TPE_CTRL),
+	HAL_RF_RXDCK_TRACK = BIT(RF23_RXDCK_TRK),
+	HAL_RF_TAS = BIT(RF26_RF_TAS),
+	HAL_RF_WATCHDOG = BIT(RF31_WATCHDOG),
+};
+
+/*@=[HALRF Debug Component]=====================================*/
+enum halrf_dbg_comp {
+	DBG_RF_TX_PWR_TRACK = BIT(RF00_PWR_TRK),
+	DBG_RF_IQK = BIT(RF01_IQK),
+	DBG_RF_LCK = BIT(RF02_LCK),
+	DBG_RF_DPK = BIT(RF03_DPK),
+	DBG_RF_TXGAPK = BIT(RF04_TXGAPK),
+	DBG_RF_DACK = BIT(RF05_DACK),
+	DBG_RF_DPK_TRACK = BIT(RF06_DPK_TRK),
+	DBG_RF_RXDCK = BIT(RF08_RXDCK),
+	DBG_RF_RFK = BIT(RF09_RFK),
+	DBG_RF_INIT = BIT(RF10_RF_INIT),
+	DBG_RF_POWER = BIT(RF11_RF_POWER),
+	DBG_RF_RXGAINK = BIT(RF12_RXGAINK),
+	DBG_RF_THER_TRIM = BIT(RF13_THER_TRIM),
+	DBG_RF_PABIAS_TRIM = BIT(RF14_PABIAS_TRIM),
+	DBG_RF_TSSI_TRIM = BIT(RF15_TSSI_TRIM),
+	DBG_RF_PSD = BIT(RF16_PSD),
+	DBG_RF_XTAL_TRACK = BIT(RF18_XTAL_TRK),
+	DBG_RF_OP5K_TRACK = BIT(RF20_OP5K_TRK),
+	DBG_RF_OP5K = BIT(RF21_OP5K),
+	DBG_RF_TAS = BIT(RF26_RF_TAS),
+	DBG_RF_FW = BIT(28),
+	DBG_RF_MP = BIT(29),
+	DBG_RF_TMP = BIT(30),
+	DBG_RF_CHK = BIT(31)
+};
+
+ 
+/*@--------------------------[Structure]-------------------------------------*/
+
+struct rfk_location {
+	enum band_type cur_band;
+	enum channel_width cur_bw;
+	u8 cur_ch;
+};
+
+#define OP5K_RESET_CNT_DATA	16
+#define OP5K_RESET_CNT_ZERO_IDX	2
+#define	OP5K_THERMAL_NUM	2
+#define	OP5K_AVG_THERMAL_NUM	2
+#define OP5K_THER_THRESHOLD	8
+
+#ifdef HALRF_OP5K_SUPPORT
+struct halrf_op5k_info {
+	u32 rst_cnt[MAX_RF_PATH][OP5K_RESET_CNT_DATA];
+	u32 rst_cnt_zero[MAX_RF_PATH][OP5K_RESET_CNT_ZERO_IDX];
+	u32 rst_cnt_final[MAX_RF_PATH];
+	u32 op5k_backup[MAX_RF_PATH];
+	u8 thermal_op5k[MAX_RF_PATH];
+	u8 thermal_op5k_avg[MAX_RF_PATH][OP5K_THERMAL_NUM];
+	u8 thermal_op5k_avg_index;
+	bool op5k_progress;
+	u8 record_bw;
+};
+#endif
+
+#if 1 /* all rf operation usage (header) */
+
+/* clang-format on */
+#define RF_PATH_MAX_NUM (8)
+#define RF_TASK_RECORD_MAX_TIMES (16)
+#define RF_BACKUP_MAC_REG_MAX_NUM (16)
+#define RF_BACKUP_BB_REG_MAX_NUM (16)
+#define RF_BACKUP_RF_REG_MAX_NUM (16)
+#define RF_BACKUP_KIP_REG_MAX_NUM (16)
+
+#define RF_FCS_NUM 20
+#ifdef CONFIG_PHL_RFK_FCS_SUPPPORT
+#define HALRF_FCS_SUPPORT
+#endif
+// #ifdef HALRF_FCS_SUPPORT
+// #define RF_FCS_NUM MAX_RFK_FCS_NUMBER
+// #endif
+
+#define HALRF_FCS_FW_RELOAD 0
+
+#if defined(RF_8852C_SUPPORT) 
+#define RFK_REG 3136
+#elif defined (RF_8852B_SUPPORT)
+#define RFK_REG 2560
+#else
+#define RFK_REG 1	//TBD
+#endif
+
+#define FCS_TO_FW_DATA_SIZE 400
+
+struct halrf_iqk_ops {
+	u8 (*iqk_kpath)(struct rf_info *rf, enum phl_phy_idx phy_idx);	
+	bool (*iqk_mcc_page_sel)(struct rf_info *rf, enum phl_phy_idx phy,  u8 path);
+	void (*iqk_get_ch_info)(struct rf_info *rf, enum phl_phy_idx phy,  u8 path);	
+	void (*iqk_preset)(struct rf_info *rf, u8 path);	
+	void (*iqk_macbb_setting)(struct rf_info *rf, enum phl_phy_idx phy_idx, u8 path);
+	void (*iqk_start_iqk)(struct rf_info *rf, enum phl_phy_idx phy_idx, u8 path);
+	void (*iqk_restore)(struct rf_info *rf, u8 path);
+	void (*iqk_afebb_restore)(struct rf_info *rf, enum phl_phy_idx phy_idx, u8 path);
+};
+
+#ifdef HALRF_FCS_SUPPORT
+struct halrf_fcs_info {
+	u32	bkp_index;
+	u32 rst_index;
+	u32	fcs_ch[RF_FCS_NUM]; // ch
+	u32 lok1[RF_FCS_NUM][2]; // 0x5C ch/path
+	u32 lok2[RF_FCS_NUM][2]; // 0x58 ch/path	
+	u32 lok3[RF_FCS_NUM][2]; // 0x55 ch/path	
+	u32 rf_reg[RF_FCS_NUM][RFK_REG]; // ch/reg
+};
+#endif
+
+struct rfk_iqk_info {
+	struct halrf_iqk_ops *rf_iqk_ops;
+	u8 rf_max_path_num;
+	u32 rf_iqk_version;
+	u8 rf_iqk_ch_num;
+	u8 rf_iqk_path_num;
+
+	const u32 *backup_mac_reg;
+	u32 backup_mac_reg_num;
+	const u32 *backup_bb_reg;
+	u32 backup_bb_reg_num;
+	const u32 *backup_rf_reg;
+	u32 backup_rf_reg_num;
+};
+/* clang-format off */
+#endif /* all rf operation usage (header) */
+
+struct halrf_rx_dck_info {
+	bool is_afe;
+	bool is_rxdck_track_en;
+	struct rfk_location loc[KPATH]; /*max RF path*/
+	u32 rxdck_time;
+	bool is_auto_res;
+	u8 ther_rxdck[KPATH];
+	u8 rek_cnt[KPATH];
+};
+
+#ifdef HALRF_MCC_DBCC
+struct halrf_mcc_info {
+	u8 ch[2];  
+	u8 band[2];  
+	u8 table_idx;  
+	
+	bool is_init;
+};
+#endif
+
+struct halrf_dbcc_info {
+	u8 ch[2][2]; /*idx : path*/  
+	u8 band[2][2];  
+	u8 table_idx;  
+	bool prek_is_dbcc;
+	bool is_free[2];
+};
+
+struct halrf_rfk_ops {
+	void (*ops_rx_dck)(struct rf_info *rf, enum phl_phy_idx phy, bool is_afe);
+	void (*ops_do_txgapk)(struct rf_info *rf, enum phl_phy_idx phy);
+	void (*ops_tssi_disable)(struct rf_info *rf, enum phl_phy_idx phy);
+	void (*ops_do_tssi)(struct rf_info *rf, enum phl_phy_idx phy, bool hwtx_en);
+	void (*ops_dpk)(struct rf_info *rf, enum phl_phy_idx phy, bool force);
+	void (*ops_dack)(struct rf_info *rf, bool force);
+	void (*ops_lck)(struct rf_info *rf);
+	void (*ops_lck_tracking)(struct rf_info *rf);
+	void (*ops_lo_test)(struct rf_info *rf, bool is_on, enum rf_path path);
+	void (*ops_config_radio_to_fw)(struct rf_info *rf);
+	void (*ops_txgapk_w_table_default)(struct rf_info *rf, enum phl_phy_idx phy);
+	void (*ops_txgapk_enable)(struct rf_info *rf, enum phl_phy_idx phy);
+	void (*ops_txgapk_init)(struct rf_info *rf);
+	void (*ops_adie_pow_ctrl)(struct rf_info *rf, bool rf_off, bool others_off);
+	void (*ops_afe_pow_ctrl)(struct rf_info *rf, bool adda_off, bool pll_off);
+	void (*ops_set_gpio_by_ch)(struct rf_info *rf, enum phl_phy_idx phy, enum band_type band);
+	bool (*ops_chlk_reload_check)(struct rf_info *rf, enum phl_phy_idx phy);
+	void (*ops_long_pkt_comp)(struct rf_info *rf, enum phl_phy_idx phy);	
+};
+
+
+struct halrf_do_ops_info {
+	bool is_do_ops_rxdck;
+	bool is_do_ops_txgapk;
+	bool is_do_ops_tssi_disable;
+	bool is_do_ops_tssi;
+	bool is_do_ops_dpk;
+	bool is_do_ops_dack;
+	bool is_do_ops_lck;
+	bool is_do_ops_lck_trk;
+	bool is_do_ops_lo_test;
+	bool is_do_ops_radio_to_fw;
+	bool is_do_ops_txgapk_default;
+	bool is_do_ops_txgapk_en;
+	bool is_do_ops_txgapk_init;
+	bool is_do_ops_adie_pow_ctrl;
+	bool is_do_ops_afe_pow_ctrl;
+	bool is_do_ops_set_gpio_by_ch;
+	bool is_do_ops_chlk_reload_chk;
+	bool is_do_ops_get_thermal;
+    	bool is_do_ops_dack_sft_rest;
+};
+
+//===========
+
+struct halrf_rfk_ver  {
+	u8 dack_ver;
+	u8 rxdck_ver;
+	u8 txgapk_ver;
+	u8 tssi_ver;
+	u8 dpk_ver;
+};
+struct rf_info {
+	struct rtw_phl_com_t	*phl_com;
+	struct rtw_hal_com_t	*hal_com;
+	/*[Common Info]*/
+	u32			ic_type;
+	u8			num_rf_path;
+	u16 		sub_did;
+	bool		use_sub_did;
+	/*[System Info]*/
+	bool			rf_init_ready;
+	u32			rf_sys_up_time;
+	bool			rf_watchdog_en;
+	bool			rf_ic_api_en;
+	/*[DM Info]*/
+	u32			support_ability;
+	u32			hw_rf_ability;
+	u32			manual_support_ability;
+	/*[FW Info]*/
+	u32			fw_dbg_component;
+	/*[Drv Dbg Info]*/
+	u32			dbg_component;
+	u8			cmn_dbg_msg_period;
+	u8			cmn_dbg_msg_cnt;
+	/*[BTC / RFK Info ]*/
+	bool 			rfk_is_processing;
+	u32				psd_progress;
+	bool			is_bt_iqk_timeout;
+	bool			is_chl_rfk;
+	u32			rfk_total_time;
+	/*[initial]*/
+	u8 		pre_rxbb_bw[KPATH];
+	/*[TSSI Info]*/
+	bool		is_tssi_mode[MAX_RF_PATH]; /*S0/S1*/
+	u8		tssi_slope_type[MAX_RF_PATH];
+	/*[Thermal]*/
+	bool		is_thermal_trigger;
+	u8		cur_ther_s0;
+	u8		cur_ther_s1;
+	u8		is_set_thermal;
+	u8		thermal_test[MAX_RF_PATH];
+	/*LCK*/
+	u8		lck_ther_s0;
+	u8		lck_ther_s1;
+	u32		lck_times;
+	/*[Do Coex]*/
+	bool		is_coex;
+	/*[watchdog]*/
+	bool		is_watchdog_stop;
+	/*[thermal rek indictor]*/	
+	bool rfk_do_thr_rek;
+#ifdef HALRF_KIP_CR_CHECK
+	/*reg check*/
+	u32	rfk_reg[KIP_REG];
+	u32	rfc_reg[2][10];
+	u32	rfk_check_fail_count;
+#endif
+	/*fast channel switch*/
+	u8	ther_init;
+	u32	fcs_rfk_ok_map;
+	u8	pre_chl_idx;
+	u8	pre_ther_idx;
+	/* [Check NCTL Done status Read Times] */
+	u32 nctl_ck_times[2];  /* 0xbff8 0x80fc*/
+	u32	fw_ofld_enable;
+	u32	fw_ofld_start;
+	/*IO/FW offload count*/
+	u32	w_count;
+	u32	r_count;
+	u32	fw_w_count;
+	u32	fw_r_count;
+	u32	sw_trigger_count;
+	u32	pre_fw_w_count;
+	u32 fw_delay_us_count;
+	u32 init_rf_reg_time;
+	u32 set_ch_bw_time;
+
+	_os_mutex	rf_lock;
+	u32 chlk_map;
+	u32 kip_table[2][4];	
+	/*@=== [HALRF Structure] ============================================*/
+	struct halrf_pwr_track_info	pwr_track;
+	struct halrf_tssi_info		tssi;
+	struct halrf_xtal_info		xtal_track;
+	struct halrf_iqk_info		iqk;
+	struct halrf_dpk_info	dpk;
+	struct halrf_rx_dck_info rx_dck;
+	struct halrf_dack_info	dack;
+	struct halrf_gapk_info	gapk;
+	struct halrf_pwr_info	pwr_info;
+	struct halrf_fw_scan_pwr_info pwr_fw_info;
+	struct halrf_radio_info	radio_info;
+	struct halrf_fem_info	fem;
+	struct rf_dbg_cmd_info	rf_dbg_cmd_i;
+	struct halrf_kfree_info	kfree_info;
+#ifdef HALRF_PSD_SUPPORT	
+	struct halrf_psd_data	psd;
+#endif	/*HALRF_PSD_SUPPORT*/
+	struct rfk_location		iqk_loc[2];	/*S0/S1*/
+	struct rfk_location		dpk_loc[2];	/*S0/S1*/
+	struct rfk_location		gapk_loc[2];	/*S0/S1*/
+	struct rfk_iqk_info	*rfk_iqk_info;
+#ifdef HALRF_OP5K_SUPPORT
+	struct halrf_op5k_info op5k_info;
+#endif
+#ifdef HALRF_MCC_DBCC
+	struct halrf_mcc_info mcc_info;
+#endif
+	struct halrf_dbcc_info dbcc_info;
+	struct halrf_rfk_ops *rf_rfk_ops;
+	struct halrf_do_ops_info ops_info;
+#ifdef HALRF_DZ_LOG
+	struct halrf_rt_rpt rf_rt_rpt;
+	struct halrf_rfk_dz_rpt rfk_dz_rpt;
+	struct halrf_ex_dz_info ex_dz_info;
+#endif
+#ifdef HALRF_FCS_SUPPORT
+	struct halrf_fcs_info	fcs_info;
+#endif
+#ifdef PHL_PLATFORM_WINDOWS
+#ifdef HALRF_TAS_SUPPORT
+	struct halrf_tas_info tas_info;
+#endif
+#endif
+};
+
+/*@--------------------------[Prptotype]-------------------------------------*/
+void halrf_si_reset(struct rf_info *rf);
+void halrf_bb_reset_trigger(struct rf_info *rf, enum phl_phy_idx phy_idx);
+
+#endif
+

3rd/devourer/hal/halrf/g6/vendor/halrf_8852b/halrf_8852b.h

@@ -0,0 +1,65 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2020  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+#ifndef __HALRF_8852B_H__
+#define __HALRF_8852B_H__
+#ifdef RF_8852B_SUPPORT
+
+#define RXDCK_VER_8852B 0x2
+#define RCK_VER_8852B 0x3
+
+void halrf_lo_test_8852b(struct rf_info *rf, bool is_on, enum rf_path path);
+u8 halrf_kpath_8852b(struct rf_info *rf, enum phl_phy_idx phy_idx);
+void halrf_set_rx_dck_8852b(struct rf_info *rf, enum phl_phy_idx phy, enum rf_path path, bool is_afe);
+void halrf_rx_dck_8852b(struct rf_info *rf, enum phl_phy_idx phy, bool is_afe);
+void halrf_rx_dck_onoff_8852b(struct rf_info *rf, bool is_enable);
+void halrf_rck_8852b(struct rf_info *rf, enum rf_path path);
+void halrf_rf_direct_cntrl_8852b(struct rf_info *rf, enum rf_path path, bool is_bybb);
+void halrf_drf_direct_cntrl_8852b(struct rf_info *rf, enum rf_path path, bool is_bybb);
+void halrf_bf_config_rf_8852b(struct rf_info *rf);
+extern struct rfk_iqk_info rf_iqk_hwspec_8852b;
+void halrf_dpk_init_8852b(struct rf_info *rf);
+bool halrf_ctrl_ch_8852b(struct rf_info *rf,  u8 central_ch);
+bool halrf_ctrl_bw_8852b(struct rf_info *rf, enum channel_width bw);
+void halrf_rxbb_bw_8852b(struct rf_info *rf, enum phl_phy_idx phy, enum channel_width bw);
+void halrf_fw_ntfy_8852b(struct rf_info *rf, enum phl_phy_idx phy_idx); 
+void halrf_disconnect_notify_8852b(struct rf_info *rf, struct rtw_chan_def *chandef  ) ;
+bool halrf_check_mcc_ch_8852b(struct rf_info *rf, struct rtw_chan_def *chandef) ;
+void halrf_quick_checkrf_8852b(struct rf_info *rf);
+
+void halrf_before_one_shot_enable_8852b(struct rf_info *rf);
+bool halrf_one_shot_nctl_done_check_8852b(struct rf_info *rf, enum rf_path path);
+void halrf_adc_fifo_rst_8852b(struct rf_info *rf, enum phl_phy_idx phy_idx, u8 path);
+
+void halrf_fcs_backup_8852b(struct rf_info *rf, u32 chl_index);
+void halrf_fcs_drv_reload_8852b(struct rf_info *rf, u32 chl_index);
+void halrf_fcs_fw_reload_8852b(struct rf_info *rf, u32 chl_index);
+bool halrf_rfk_reg_check_fail_8852b(struct rf_info *rf);
+void halrf_rfk_reg_backup_8852b(struct rf_info *rf);
+void halrf_rfk_reg_reload_8852b(struct rf_info *rf);
+bool halrf_check_ft_result_8852b(struct rf_info *rf);
+bool halrf_SRAM_MBIST_normal_8852b(struct rf_info *rf);
+bool halrf_SRAM_MBIST_DS_8852b(struct rf_info *rf);
+#endif
+#endif /*  __HALRF_8852b_H__ */

3rd/devourer/hal/halrf/g6/vendor/halrf_8852b/halrf_8852b_api.c

@@ -0,0 +1,529 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2020  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+#include "../halrf_precomp.h"
+#ifdef RF_8852B_SUPPORT
+
+u8 halrf_get_thermal_8852b(struct rf_info *rf, enum rf_path rf_path)
+{
+	halrf_wrf(rf, rf_path, 0x42, BIT(19), 0x1);
+	halrf_wrf(rf, rf_path, 0x42, BIT(19), 0x0);
+	halrf_wrf(rf, rf_path, 0x42, BIT(19), 0x1);
+
+	halrf_delay_us(rf, 200);
+
+	return (u8)halrf_rrf(rf, rf_path, 0x42, 0x0007e);
+}
+
+u32 halrf_mac_get_pwr_reg_8852b(struct rf_info *rf, enum phl_phy_idx phy,
+	u32 addr, u32 mask)
+{
+	struct rtw_hal_com_t *hal = rf->hal_com;
+	u32 result, ori_val, bit_shift, reg_val;
+
+	result = rtw_hal_mac_get_pwr_reg(hal, phy, addr, &ori_val);
+	if (result)
+		RF_WARNING("=======>%s Get MAC(0x%x) fail, error code=%d\n",
+			__func__, addr, result);
+	else
+		RF_DBG(rf, DBG_RF_POWER, "Get MAC(0x%x) ok!!! 0x%08x\n",
+			addr, ori_val);
+
+	bit_shift = halrf_cal_bit_shift(mask);
+	reg_val = (ori_val & mask) >> bit_shift;
+
+	return reg_val;
+}
+
+u32 halrf_mac_set_pwr_reg_8852b(struct rf_info *rf, enum phl_phy_idx phy,
+	u32 addr, u32 mask, u32 val)
+{
+	struct rtw_hal_com_t *hal = rf->hal_com;
+	u32 result;
+
+	result = rtw_hal_mac_write_msk_pwr_reg(hal, phy, addr, mask, val);
+	if (result) {
+		RF_WARNING("=======>%s Set MAC(0x%x[0x%08x]) fail, error code=%d\n",
+			__func__, addr, mask, result);
+		return false;
+	} else
+		RF_DBG(rf, DBG_RF_POWER, "Set MAC(0x%x[0x%08x])=0x%08x ok!!! \n",
+			addr, mask, val);
+
+	return result;
+}
+
+void halrf_wlan_tx_power_control_8852b(struct rf_info *rf,
+	enum phl_phy_idx phy, enum phl_pwr_ctrl pwr_ctrl_idx,
+	u32 tx_power_val, bool enable)
+{
+	u32 phy_tmp;
+
+	RF_DBG(rf, DBG_RF_POWER, "[Pwr Ctrl] ==>%s phy=%d pwr_ctrl_idx=%d tx_power_val=%d enable=%d\n",
+		__func__, phy, pwr_ctrl_idx, tx_power_val, enable);
+
+	if (rf->hal_com->dbcc_en)
+		phy_tmp = phy;
+	else
+		phy_tmp = HW_PHY_0;
+
+	if (enable == false) {
+		if (pwr_ctrl_idx == ALL_TIME_CTRL) {
+			/*all-time control Disable*/
+			halrf_mac_set_pwr_reg_8852b(rf, phy_tmp, 0xd200, 0x3ff, 0x0);
+		} else if (pwr_ctrl_idx == GNT_TIME_CTRL) {
+			/*GNT_BT control Disable*/
+			halrf_mac_set_pwr_reg_8852b(rf, phy_tmp, 0xd220, BIT(1), 0x0);
+			halrf_mac_set_pwr_reg_8852b(rf, phy_tmp, 0xd220, 0xff8, 0x0);
+		}
+	} else {
+		if (pwr_ctrl_idx == ALL_TIME_CTRL) {
+			halrf_mac_set_pwr_reg_8852b(rf, phy_tmp, 0xd200, 0x3ff,
+				((tx_power_val & 0x1ff) | BIT(9)));
+		} else if (pwr_ctrl_idx == GNT_TIME_CTRL) {
+			halrf_mac_set_pwr_reg_8852b(rf, phy_tmp, 0xd220, BIT(1), 0x1);
+			halrf_mac_set_pwr_reg_8852b(rf, phy_tmp, 0xd220, 0xff8, tx_power_val & 0x1ff);
+		} else {
+			RF_WARNING("[Pwr Ctrl] ==>%s (pwr_ctrl_idx = %d) don't exist !!!\n",
+				__func__, pwr_ctrl_idx);
+		}
+	}
+}
+
+bool halrf_wl_tx_power_control_8852b(struct rf_info *rf, u32 tx_power_val)
+{
+	struct halrf_pwr_info *pwr = &rf->pwr_info;
+	u32 result; 
+	s32 tmp_pwr;
+	u8 phy = 0;
+	u32 all_time_control = 0;
+	u32 gnt_bt_control = 0;
+
+	RF_DBG(rf, DBG_RF_POWER, "=======>%s\n", __func__);
+
+	all_time_control = tx_power_val & 0xffff;
+	gnt_bt_control = (tx_power_val & 0xffff0000) >> 16;
+
+	RF_DBG(rf, DBG_RF_POWER, "[Pwr Ctrl]tx_power_val=0x%x   all_time_control=0x%x   gnt_bt_control=0x%x\n",
+		tx_power_val, all_time_control, gnt_bt_control);
+
+	if (all_time_control == 0xffff) {
+		/*Coex Disable*/
+		pwr->coex_pwr_ctl_enable = false;
+		pwr->coex_pwr = 0;
+		RF_DBG(rf, DBG_RF_POWER, "[Pwr Ctrl] Coex Disable all_time_control=0xffff!!!\n");
+	} else if (all_time_control == 0xeeee) {
+		/*DPK Disable*/
+		pwr->dpk_pwr_ctl_enable = false;
+		pwr->dpk_pwr = 0;
+		RF_DBG(rf, DBG_RF_POWER, "[Pwr Ctrl] DPK Disable all_time_control=0xeeee\n");
+	} else {
+		if (all_time_control & BIT(15)) {
+			/*DPK*/
+			pwr->dpk_pwr_ctl_enable = true;
+			pwr->dpk_pwr = all_time_control & 0x1ff;
+
+			RF_DBG(rf, DBG_RF_POWER, "[Pwr Ctrl] DPK Enable Set pwr->dpk_pwr = %d\n",
+				pwr->dpk_pwr);
+		} else {
+			/*Coex*/
+			pwr->coex_pwr_ctl_enable = true;
+			pwr->coex_pwr = all_time_control & 0x1ff;
+
+			RF_DBG(rf, DBG_RF_POWER, "[Pwr Ctrl] Coex Enable Set pwr->coex_pwr = %d\n",
+				pwr->coex_pwr);
+		}
+	}
+
+	if (pwr->coex_pwr_ctl_enable == true && pwr->dpk_pwr_ctl_enable == false) {
+		tmp_pwr = pwr->coex_pwr;
+
+		RF_DBG(rf, DBG_RF_POWER, "[Pwr Ctrl] coex_pwr_ctl_enable=true dpk_pwr_ctl_enable=false tmp_pwr=%d\n",
+			tmp_pwr);
+	} else if (pwr->coex_pwr_ctl_enable == false && pwr->dpk_pwr_ctl_enable == true) {
+		tmp_pwr = pwr->dpk_pwr;
+
+		RF_DBG(rf, DBG_RF_POWER, "[Pwr Ctrl] coex_pwr_ctl_enable=false dpk_pwr_ctl_enable=true tmp_pwr=%d\n",
+			tmp_pwr);
+	} else if (pwr->coex_pwr_ctl_enable == true && pwr->dpk_pwr_ctl_enable == true) {
+		if (pwr->coex_pwr > pwr->dpk_pwr)
+			tmp_pwr = pwr->dpk_pwr;
+		else
+			tmp_pwr = pwr->coex_pwr;
+
+		RF_DBG(rf, DBG_RF_POWER, "[Pwr Ctrl] coex_pwr_ctl_enable=true dpk_pwr_ctl_enable=true tmp_pwr=%d\n",
+			tmp_pwr);
+	} else
+		tmp_pwr = 0;
+
+	if (pwr->coex_pwr_ctl_enable == false && pwr->dpk_pwr_ctl_enable == false) {
+		/*all-time control Disable*/
+		result = halrf_mac_set_pwr_reg_8852b(rf, phy, 0xd200, 0x3ff, 0x0);
+
+		if (result) {
+			RF_WARNING("=======>%s Set MAC(0xd200) fail, error code=%d\n",
+				__func__, result);
+			return false;
+		} else {
+			RF_DBG(rf, DBG_RF_POWER, "Set MAC(0xd200) ok!!!\n");
+			rf->is_coex = false;
+		}
+	} else {
+		/*all-time control*/
+		result = halrf_mac_set_pwr_reg_8852b(rf, phy, 0xd200, 0x3ff, ((tmp_pwr & 0x1ff) | BIT(9)));
+		if (result) {
+			RF_WARNING("=======>%s Set MAC(0xd200) fail, error code=%d\n",
+				__func__, result);
+			return false;
+		} else {
+			RF_DBG(rf, DBG_RF_POWER, "Set MAC(0xd200) ok!!!\n");
+			rf->is_coex = true;
+		}
+	}
+
+	if (gnt_bt_control == 0xffff) {
+		/*GNT_BT control*/
+
+		RF_DBG(rf, DBG_RF_POWER, "=======>%s   gnt_bt_control = 0x%x\n",
+			__func__, gnt_bt_control);
+
+		result = halrf_mac_set_pwr_reg_8852b(rf, phy, 0xd220, BIT(1), 0x0);
+		result = halrf_mac_set_pwr_reg_8852b(rf, phy, 0xd220, 0xff8, 0x0);
+		if (result) {
+			RF_WARNING("=======>%s Set MAC(0xd220) fail, error code=%d\n",
+				__func__, result);
+			return false;
+		} else {
+			RF_DBG(rf, DBG_RF_POWER, "Set MAC(0xd220) ok!!!\n");
+			rf->is_coex = false;
+		}
+	} else {
+		/*GNT_BT control*/
+
+		RF_DBG(rf, DBG_RF_POWER, "=======>%s   gnt_bt_control = 0x%x\n",
+			__func__, gnt_bt_control);
+
+		result = halrf_mac_set_pwr_reg_8852b(rf, phy, 0xd220, BIT(1), 0x1);
+		result = halrf_mac_set_pwr_reg_8852b(rf, phy, 0xd220, 0xff8, gnt_bt_control & 0x1ff);
+		if (result) {
+			RF_WARNING("=======>%s Set MAC(0xd220) fail, error code=%d\n",
+				__func__, result);
+			return false;
+		} else {
+			RF_DBG(rf, DBG_RF_POWER, "Set MAC(0xd220) ok!!!\n");
+			rf->is_coex = true;
+		}
+	}
+
+	return true;
+}
+
+#ifdef HALRF_THERMAL_PROTECT_SUPPORT
+s8 halrf_get_ther_protected_threshold_8852b(struct rf_info *rf)
+{
+	u8 tmp_a, tmp_b, tmp;
+	u8 therml_max = 0x32;
+
+	tmp_a = rf->cur_ther_s0;
+	tmp_b = rf->cur_ther_s1;
+
+	if (rf->phl_com->dev_sw_cap.thermal_threshold != 0xff)
+		therml_max = rf->phl_com->dev_sw_cap.thermal_threshold;
+
+	if (tmp_a > tmp_b)
+		tmp = tmp_a;
+	else
+		tmp = tmp_b;
+
+	if (tmp > therml_max)
+		return -1;	/*Tx duty reduce*/
+	else if (tmp < therml_max - 2)
+		return 1;	/*Tx duty up*/
+	else 
+		return 0;	/*Tx duty the same*/
+}
+#endif	/*HALRF_THERMAL_PROTECT_SUPPORT*/
+
+s8 halrf_xtal_tracking_offset_8852b(struct rf_info *rf,
+					enum phl_phy_idx phy)
+{
+	struct halrf_xtal_info *xtal_trk = &rf->xtal_track;
+	u8 thermal_a = 0xff, thermal_b = 0xff;
+	u8 tmp_a, tmp_b, tmp;
+	s8 xtal_ofst = 0;
+
+	RF_DBG(rf, DBG_RF_XTAL_TRACK, "======>%s   phy=%d\n",
+		__func__, phy);
+
+	tmp_a = rf->cur_ther_s0;
+	tmp_b = rf->cur_ther_s1;
+	halrf_efuse_get_info(rf, EFUSE_INFO_RF_THERMAL_A, &thermal_a, 1);
+	halrf_efuse_get_info(rf, EFUSE_INFO_RF_THERMAL_B, &thermal_b, 1);
+
+	if (thermal_a == 0xff || thermal_b == 0xff ||
+		thermal_a == 0x0 || thermal_b == 0x0) {
+		RF_DBG(rf, DBG_RF_XTAL_TRACK, "======>%s PG ThermalA=%d ThermalB=%d\n",
+			__func__, thermal_a, thermal_b);
+		return 0;
+	}
+
+	if (tmp_a > tmp_b) {
+		if (tmp_a > thermal_a) {
+			tmp = tmp_a - thermal_a;
+			if (tmp >= DELTA_SWINGIDX_SIZE)
+				tmp = DELTA_SWINGIDX_SIZE - 1;
+			xtal_ofst = xtal_trk->delta_swing_xtal_table_idx_p[tmp];
+		} else {
+			tmp = thermal_a - tmp_a;
+			if (tmp >= DELTA_SWINGIDX_SIZE)
+				tmp = DELTA_SWINGIDX_SIZE - 1;
+			xtal_ofst = xtal_trk->delta_swing_xtal_table_idx_n[tmp];
+		}
+	} else {
+		if (tmp_b > thermal_b) {
+			tmp = tmp_b - thermal_b;
+			if (tmp >= DELTA_SWINGIDX_SIZE)
+				tmp = DELTA_SWINGIDX_SIZE - 1;
+			xtal_ofst = xtal_trk->delta_swing_xtal_table_idx_p[tmp];
+		} else {
+			tmp = thermal_b - tmp_b;
+			if (tmp >= DELTA_SWINGIDX_SIZE)
+				tmp = DELTA_SWINGIDX_SIZE - 1;
+			xtal_ofst = xtal_trk->delta_swing_xtal_table_idx_n[tmp];
+		}
+	}
+
+	RF_DBG(rf, DBG_RF_XTAL_TRACK, "PG ThermalA=%d   ThermalA=%d\n",
+		thermal_a, tmp_a);
+
+	RF_DBG(rf, DBG_RF_XTAL_TRACK, "PG ThermalB=%d   ThermalB=%d\n",
+		thermal_b, tmp_b);
+
+	RF_DBG(rf, DBG_RF_XTAL_TRACK, "xtal_ofst[%d]=%d\n",
+		tmp, xtal_ofst);
+
+	return xtal_ofst;
+}
+
+void halrf_rfe_ant_num_chk_8852b(struct rf_info *rf)
+{
+	struct phy_hw_cap_t *phy_hw = rf->hal_com->phy_hw_cap;
+	u8 rfe_type;
+
+	if (phl_is_mp_mode(rf->phl_com))
+		rfe_type = rf->phl_com->dev_sw_cap.rfe_type;
+	else
+		rfe_type = rf->hal_com->dev_hw_cap.rfe_type;
+
+	if (phy_hw[0].tx_num == 1 && phy_hw[0].tx_path_num == 2 &&
+		phy_hw[0].rx_num == 1 && phy_hw[0].rx_path_num == 2) {
+
+		if (rfe_type == 41) {
+			RF_DBG(rf, DBG_RF_INIT, "%s: rfe_type: %d set to 1T1R\n", __func__, rfe_type);
+			phy_hw[0].tx_path_num = 1;
+			phy_hw[0].rx_path_num = 1;
+		} else if (rfe_type == 43) {
+			RF_DBG(rf, DBG_RF_INIT, "%s: rfe_type: %d set to 1T2R\n", __func__, rfe_type);
+			phy_hw[0].tx_path_num = 2;
+			phy_hw[0].rx_path_num = 2;
+		}
+	}
+}
+
+void halrf_txck_force_8852b(struct rf_info *rf, enum rf_path path, bool force, enum dac_ck ck)
+{
+	halrf_wreg(rf, 0x12a0 | (path <<13), BIT(15), 0x0);
+
+	if (!force)
+		return;
+
+	halrf_wreg(rf, 0x12a0 | (path <<13), 0x7000, ck);
+	halrf_wreg(rf, 0x12a0 | (path <<13), BIT(15), 0x1);
+}
+
+
+void halrf_rxck_force_8852b(struct rf_info *rf, enum rf_path path, bool force, enum adc_ck ck)
+{
+
+	halrf_wreg(rf, 0x12a0 | (path <<13), BIT(19), 0x0);
+	if (!force)
+		return;
+	halrf_wreg(rf, 0x12a0 | (path <<13), 0x70000, ck);
+	halrf_wreg(rf, 0x12a0 | (path <<13), BIT(19), 0x1);
+}
+
+
+void halrf_arfc_si_reset_8852b(struct rf_info *rf, bool is_reset)
+{
+	u8 val;
+
+	/*reset adie HW/SW SI*/
+	if (is_reset) {
+		rtw_hal_mac_get_xsi((rf)->hal_com, 0x81, &val);
+		val &= (~0xc0);
+		rtw_hal_mac_set_xsi((rf)->hal_com, 0x81, val);
+
+		rtw_hal_mac_get_xsi((rf)->hal_com, 0x80, &val);
+		val &= (~0xc0);
+		rtw_hal_mac_set_xsi((rf)->hal_com, 0x80, val);
+	} else {
+		rtw_hal_mac_get_xsi((rf)->hal_com, 0x81, &val);
+		val |= 0xc0;
+		rtw_hal_mac_set_xsi((rf)->hal_com, 0x81, val);
+
+		rtw_hal_mac_get_xsi((rf)->hal_com, 0x80, &val);
+		val |= 0xc0;
+		rtw_hal_mac_set_xsi((rf)->hal_com, 0x80, val);
+	}
+}
+
+void halrf_si_reset_8852b(struct rf_info *rf)
+{
+        /*disable hwsi trigger*/
+        halrf_wreg(rf, 0x1200, 0x70000000, 0x7);
+        halrf_wreg(rf, 0x3200, 0x70000000, 0x7);
+        halrf_delay_us(rf, 1);
+        /*reset A die HW SI*/
+        halrf_arfc_si_reset_8852b(rf, true);
+        // reset D die HW SI*/
+        halrf_wreg(rf, 0x12ac, BIT(0), 0x0);
+        halrf_wreg(rf, 0x32ac, BIT(0), 0x0);
+        /*release A die HW SI*/
+        halrf_arfc_si_reset_8852b(rf, false);
+        /*enable hwsi trigger*/
+        halrf_wreg(rf, 0x1200, 0x70000000, 0x0);
+        halrf_wreg(rf, 0x3200, 0x70000000, 0x0);
+        /*release D die HW SI*/   
+        halrf_wreg(rf, 0x12ac, BIT(0), 0x1);
+        halrf_wreg(rf, 0x32ac, BIT(0), 0x1);
+}
+
+#ifdef HALRF_MCC_DBCC
+bool halrf_chlk_reload_check_8852b(struct rf_info *rf, enum phl_phy_idx phy)
+{
+	struct halrf_dbcc_info *dbcc_info = &rf->dbcc_info;
+	struct halrf_mcc_info *mcc_info = &rf->mcc_info;
+	u8 path, i, j, idx, kpath, kch, kband;
+	bool reload = false;
+	u8 get_empty_table = false;
+
+	RF_DBG(rf, DBG_RF_RFK, "[DBCC]======> %s \n", __func__);
+	kpath = halrf_kpath(rf, phy);
+	kch = rf->hal_com->band[phy].cur_chandef.center_ch;
+	kband = rf->hal_com->band[phy].cur_chandef.band;
+	idx = dbcc_info->table_idx;
+	RF_DBG(rf, DBG_RF_RFK, "[DBCC]dbcc_en=%d  prek_is_dbcc=%d\n", rf->hal_com->dbcc_en, dbcc_info->prek_is_dbcc);
+	if (rf->hal_com->dbcc_en || dbcc_info->prek_is_dbcc) {
+		//try reload
+		for(i = 0; i < 2; i++) {
+			if (kpath == RF_AB) {
+				if (kch == dbcc_info->ch[i][1] && kband == dbcc_info->band[i][1] &&
+					kch == dbcc_info->ch[i][0] && kband == dbcc_info->band[i][0]) {
+					idx = i;
+					reload = true;
+				}
+			} else {
+				if (kpath == RF_A)
+					path = 0;
+				else
+					path = 1;
+				if (kch == dbcc_info->ch[i][path] && kband == dbcc_info->band[i][path]) {
+					idx = i;
+					reload = true;
+				}
+			}
+		}
+		if (reload) {
+			halrf_chlk_reload_dbcc(rf, phy, idx);
+			rf->chlk_map = 0xffffffff & (~HAL_RF_IQK) & (~HAL_RF_DPK);
+			RF_DBG(rf, DBG_RF_RFK, "[DBCC]reload kpath=%d, index=%d\n", kpath, idx);
+			RF_DBG(rf, DBG_RF_RFK, "[DBCC]table0 S0 ch=%5d S1 ch=%5d\n", dbcc_info->ch[0][0], dbcc_info->ch[0][1]);
+			RF_DBG(rf, DBG_RF_RFK, "[DBCC]table1 S0 ch=%5d S1 ch=%5d\n", dbcc_info->ch[1][0], dbcc_info->ch[1][1]);
+			RF_DBG(rf, DBG_RF_RFK, "[DBCC]table0 S0 band =%5d S1 band =%5d\n", dbcc_info->band[0][0], dbcc_info->band[0][1]);
+			RF_DBG(rf, DBG_RF_RFK, "[DBCC]table1 S0 band =%5d S1 band =%5d\n", dbcc_info->band[1][0], dbcc_info->band[1][1]);
+			return reload;
+		}
+	}
+	//force K
+	for  (i = 0;  i < 2; i++){
+		if (((dbcc_info->ch[i][0] == 0) && (dbcc_info->ch[i][1] == 0)) ||
+			((dbcc_info->ch[i][0] == kch) && (dbcc_info->band[i][0] == kband)))
+			break;
+	}
+	
+	if (i < 2) {
+		idx = i;
+	} else {
+		if ((kpath == RF_A) && !rf->hal_com->dbcc_en) {
+			halrf_mcc_info_init(rf, phy);
+			//get channel info
+			for  (idx = 0;  idx < 2; idx++) {
+				if (mcc_info->ch[idx] == 0) {
+					get_empty_table = true;
+					break;
+				}
+			}
+
+			if (false == get_empty_table) {
+				idx = mcc_info->table_idx + 1;
+				if (idx > 1) {
+					idx = 0;
+				}
+			}
+		}
+		else {
+			for  (j = 0;  j < 2; j++)
+				if (dbcc_info->ch[j][0] != dbcc_info->ch[j][1] ||
+					dbcc_info->band[j][0] != dbcc_info->band[j][1])
+					break;
+			if (j == 2) {
+				idx++;
+				if (idx > 1)
+					idx = 0;
+			} else {
+				idx = j;
+			}
+		}
+	}
+	rf->chlk_map = 0xffffffff;
+	dbcc_info->prek_is_dbcc = rf->hal_com->dbcc_en;
+	dbcc_info->table_idx = idx;
+	mcc_info->table_idx = idx;
+	for (path = 0; path < 2; path++) {
+		if (kpath & BIT(path)) {
+			dbcc_info->ch[idx][path] = kch;
+			dbcc_info->band[idx][path] = kband;
+		}
+	}
+	RF_DBG(rf, DBG_RF_RFK, "[DBCC]foreK kpath=%d, index=%d\n", kpath, idx);
+	RF_DBG(rf, DBG_RF_RFK, "[DBCC]ch00=%d ch01=%d ch10=%d ch11=%d\n",
+		dbcc_info->ch[0][0], dbcc_info->ch[0][1], dbcc_info->ch[1][0], dbcc_info->ch[1][1]);
+	RF_DBG(rf, DBG_RF_RFK, "[DBCC]band00=%d band01=%d band10=%d band10=%d\n",
+		dbcc_info->band[0][0], dbcc_info->band[0][1], dbcc_info->band[1][0], dbcc_info->band[1][1]);
+	RF_DBG(rf, DBG_RF_RFK, "[DBCC] mcc_info->table_idx=%d\n", mcc_info->table_idx);
+	return reload;
+}
+#endif
+
+#endif

3rd/devourer/hal/halrf/g6/vendor/halrf_8852b/halrf_8852b_api.h

@@ -0,0 +1,58 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2020  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+#ifndef __HALRF_8852B_API_H__
+#define __HALRF_8852B_API_H__
+#ifdef RF_8852B_SUPPORT
+
+u8 halrf_get_thermal_8852b(struct rf_info *rf, enum rf_path rf_path);
+
+u32 halrf_mac_get_pwr_reg_8852b(struct rf_info *rf, enum phl_phy_idx phy,
+	u32 addr, u32 mask);
+
+u32 halrf_mac_set_pwr_reg_8852b(struct rf_info *rf, enum phl_phy_idx phy,
+	u32 addr, u32 mask, u32 val);
+
+void halrf_wlan_tx_power_control_8852b(struct rf_info *rf,
+	enum phl_phy_idx phy, enum phl_pwr_ctrl pwr_ctrl_idx,
+	u32 tx_power_val, bool enable);
+
+bool halrf_wl_tx_power_control_8852b(struct rf_info *rf, u32 tx_power_val);
+#ifdef HALRF_THERMAL_PROTECT_SUPPORT
+s8 halrf_get_ther_protected_threshold_8852b(struct rf_info *rf);
+#endif
+s8 halrf_xtal_tracking_offset_8852b(struct rf_info *rf, enum phl_phy_idx phy);
+
+void halrf_rfe_ant_num_chk_8852b(struct rf_info *rf);
+
+void halrf_txck_force_8852b(struct rf_info *rf, enum rf_path path, bool force, enum dac_ck ck);
+
+void halrf_rxck_force_8852b(struct rf_info *rf, enum rf_path path, bool force, enum adc_ck ck);
+
+void halrf_si_reset_8852b(struct rf_info *rf);
+#ifdef HALRF_MCC_DBCC
+bool halrf_chlk_reload_check_8852b(struct rf_info *rf, enum phl_phy_idx phy);
+#endif
+#endif
+#endif /*  __INC_PHYDM_API_H_8852B__ */

3rd/devourer/hal/halrf/g6/vendor/halrf_8852b/halrf_8852b_api_ex.h

@@ -0,0 +1,30 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2020  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+#ifndef __HALRF_8852B_API_EX_H__
+#define __HALRF_8852B_API_EX_H__
+#ifdef RF_8852B_SUPPORT
+
+#endif
+#endif /*  __INC_PHYDM_API_H_8852B__ */

3rd/devourer/hal/halrf/g6/vendor/halrf_8852b/halrf_dack_8852b.h

@@ -0,0 +1,38 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2020  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+#ifndef __HALRF_DACK_8852B_H__
+#define __HALRF_DACK_8852B_H__
+#ifdef RF_8852B_SUPPORT
+
+#define DACK_VER_8852B 0x8
+
+void halrf_dack_recover_8852b(struct rf_info *rf,
+			      u8 offset,
+			      enum rf_path path,
+			      u32 val,
+			      bool reload);
+void halrf_dac_cal_8852b(struct rf_info *rf, bool force);
+#endif
+#endif /*  __INC_PHYDM_API_H_8852A__ */

3rd/devourer/hal/halrf/g6/vendor/halrf_8852b/halrf_dpk_8852b.h

@@ -0,0 +1,52 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2020  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+#ifndef __HALRF_DPK_8852BH__
+#define __HALRF_DPK_8852BH__
+#ifdef RF_8852B_SUPPORT
+/*--------------------------Define Parameters-------------------------------*/
+#define DPK_VER_8852B 0x16
+#define DPK_RF_PATH_MAX_8852B 2
+#define DPK_KIP_REG_NUM_8852B 3
+#define DPK_BB_REG_NUM_8852B 3
+#define DPK_RF_REG_NUM_8852B 8
+#define DPK_PATH_A_8852B 1
+#define DPK_PATH_B_8852B 1
+#define PATH_OFST_8852B 0x100
+#define CH_OFST_8852B 0x4
+#define PHY_OFST_8852B 0x80
+#define DPK_BY_NCTL_8852B 1
+#define DPK_RELOAD_EN_8852B 0
+#define DPK_REG_DBG 0
+
+/*---------------------------End Define Parameters----------------------------*/
+
+void halrf_dpk_8852b(struct rf_info *rf, enum phl_phy_idx phy_idx, bool force);
+
+void halrf_dpk_onoff_8852b(struct rf_info *rf, enum rf_path path, bool off);
+
+void halrf_dpk_track_8852b(struct rf_info *rf);
+
+#endif
+#endif /*  __HALRF_DPK_8852BH__ */

3rd/devourer/hal/halrf/g6/vendor/halrf_8852b/halrf_efuse_8852b.c

@@ -0,0 +1,337 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2020  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+#include "../halrf_precomp.h"
+
+#ifdef RF_8852B_SUPPORT
+
+bool halrf_get_efuse_info_8852b(struct rf_info *rf, u8 *efuse_map,
+		       enum rtw_efuse_info id, void *value, u32 length,
+		       u8 autoload_status)
+{
+	struct rtw_hal_com_t *hal = rf->hal_com;
+
+	u32 offset = 0;
+	u8 default_value = 0;
+
+	if (length != 1)
+		return false;
+
+	switch (id) {
+		case EFUSE_INFO_RF_PKG_TYPE:
+			offset = 0;
+			default_value = 0;
+			break;
+		case EFUSE_INFO_RF_PA:
+			offset = 0;
+			default_value = 0;
+			break;
+		case EFUSE_INFO_RF_VALID_PATH:
+			offset = 0;
+			default_value = 0;
+			break;
+		case EFUSE_INFO_RF_RFE:
+			offset = EFUSE_INFO_RF_RFE_8852B_ADDR;
+			default_value = EFUSE_INFO_RF_RFE_8852B_VALUE;
+			break;
+		case EFUSE_INFO_RF_TXPWR:
+			offset = 0;
+			default_value = 0;
+			break;
+		case EFUSE_INFO_RF_BOARD_OPTION:
+			offset = EFUSE_INFO_RF_BOARD_OPTION_8852B_ADDR;
+			default_value = EFUSE_INFO_RF_BOARD_OPTION_8852B_VALUE;
+			break;
+		case EFUSE_INFO_RF_CHAN_PLAN:
+			offset = EFUSE_INFO_RF_CHAN_PLAN_8852B_ADDR;
+			default_value = EFUSE_INFO_RF_CHAN_PLAN_8852B_VALUE;
+			break;
+		case EFUSE_INFO_RF_COUNTRY:
+			offset = 0;
+			default_value = 0;
+			break;
+		/*TSSI DE PathA CCK*/
+		case EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_1:
+			offset = EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_1_8852B_ADDR;
+			default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
+			break;
+		case EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_2:
+			offset = EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_2_8852B_ADDR;
+			default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
+			break;
+		case EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_3:
+			offset = EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_3_8852B_ADDR;
+			default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
+			break;
+		case EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_4:
+			offset = EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_4_8852B_ADDR;
+			default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
+			break;
+		case EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_5:
+			offset = EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_5_8852B_ADDR;
+			default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
+			break;
+		case EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_6:
+			offset = EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_6_8852B_ADDR;
+			default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
+			break;
+
+		/*TSSI DE PathA 2G MCS7 BW40M*/
+		case EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_1:
+			offset = EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_1_8852B_ADDR;
+			default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
+			break;
+		case EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_2:
+			offset = EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_2_8852B_ADDR;
+			default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
+			break;
+		case EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_3:
+			offset = EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_3_8852B_ADDR;
+			default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
+			break;
+		case EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_4:
+			offset = EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_4_8852B_ADDR;
+			default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
+			break;
+		case EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_5:
+			offset = EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_5_8852B_ADDR;
+			default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
+			break;
+
+		/*TSSI DE PathA 5G MCS7 BW40M*/
+		case EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_1:
+			offset = EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_1_8852B_ADDR;
+			default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
+			break;
+		case EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_2:
+			offset = EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_2_8852B_ADDR;
+			default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
+			break;
+		case EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_3:
+			offset = EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_3_8852B_ADDR;
+			default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
+			break;
+		case EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_4:
+			offset = EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_4_8852B_ADDR;
+			default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
+			break;
+		case EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_5:
+			offset = EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_5_8852B_ADDR;
+			default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
+			break;
+		case EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_6:
+			offset = EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_6_8852B_ADDR;
+			default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
+			break;
+		case EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_7:
+			offset = EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_7_8852B_ADDR;
+			default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
+			break;
+		case EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_8:
+			offset = EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_8_8852B_ADDR;
+			default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
+			break;
+		case EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_9:
+			offset = EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_9_8852B_ADDR;
+			default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
+			break;
+		case EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_10:
+			offset = EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_10_8852B_ADDR;
+			default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
+			break;
+		case EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_11:
+			offset = EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_11_8852B_ADDR;
+			default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
+			break;
+		case EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_12:
+			offset = EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_12_8852B_ADDR;
+			default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
+			break;
+		case EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_13:
+			offset = EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_13_8852B_ADDR;
+			default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
+			break;
+		case EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_14:
+			offset = EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_14_8852B_ADDR;
+			default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
+			break;
+
+		/*TSSI DE PathB CCK*/
+		case EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_1:
+			offset = EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_1_8852B_ADDR;
+			default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
+			break;
+		case EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_2:
+			offset = EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_2_8852B_ADDR;
+			default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
+			break;
+		case EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_3:
+			offset = EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_3_8852B_ADDR;
+			default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
+			break;
+		case EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_4:
+			offset = EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_4_8852B_ADDR;
+			default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
+			break;
+		case EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_5:
+			offset = EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_5_8852B_ADDR;
+			default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
+			break;
+		case EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_6:
+			offset = EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_6_8852B_ADDR;
+			default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
+			break;
+
+		/*TSSI DE PathB 2G MCS7 BW40M*/
+		case EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_1:
+			offset = EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_1_8852B_ADDR;
+			default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
+			break;
+		case EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_2:
+			offset = EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_2_8852B_ADDR;
+			default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
+			break;
+		case EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_3:
+			offset = EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_3_8852B_ADDR;
+			default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
+			break;
+		case EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_4:
+			offset = EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_4_8852B_ADDR;
+			default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
+			break;
+		case EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_5:
+			offset = EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_5_8852B_ADDR;
+			default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
+			break;
+
+		/*TSSI DE PathB 5G MCS7 BW40M*/
+		case EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_1:
+			offset = EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_1_8852B_ADDR;
+			default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
+			break;
+		case EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_2:
+			offset = EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_2_8852B_ADDR;
+			default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
+			break;
+		case EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_3:
+			offset = EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_3_8852B_ADDR;
+			default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
+			break;
+		case EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_4:
+			offset = EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_4_8852B_ADDR;
+			default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
+			break;
+		case EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_5:
+			offset = EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_5_8852B_ADDR;
+			default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
+			break;
+		case EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_6:
+			offset = EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_6_8852B_ADDR;
+			default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
+			break;
+		case EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_7:
+			offset = EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_7_8852B_ADDR;
+			default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
+			break;
+		case EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_8:
+			offset = EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_8_8852B_ADDR;
+			default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
+			break;
+		case EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_9:
+			offset = EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_9_8852B_ADDR;
+			default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
+			break;
+		case EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_10:
+			offset = EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_10_8852B_ADDR;
+			default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
+			break;
+		case EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_11:
+			offset = EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_11_8852B_ADDR;
+			default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
+			break;
+		case EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_12:
+			offset = EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_12_8852B_ADDR;
+			default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
+			break;
+		case EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_13:
+			offset = EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_13_8852B_ADDR;
+			default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
+			break;
+		case EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_14:
+			offset = EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_14_8852B_ADDR;
+			default_value = EFUSE_INFO_RF_TSSI_DE_8852B_VALUE;
+			break;
+
+		case EFUSE_INFO_RF_RX_GAIN_K_A_2G_CCK:
+			offset = EFUSE_INFO_RF_RX_GAIN_K_A_2G_CCK_8852B_ADDR;
+			default_value = EFUSE_INFO_RF_RX_GAIN_K_8852B_VALUE;
+			break;
+		case EFUSE_INFO_RF_RX_GAIN_K_A_2G_OFMD:
+			offset = EFUSE_INFO_RF_RX_GAIN_K_A_2G_OFMD_8852B_ADDR;
+			default_value = EFUSE_INFO_RF_RX_GAIN_K_8852B_VALUE;
+			break;
+		case EFUSE_INFO_RF_RX_GAIN_K_A_5GL:
+			offset = EFUSE_INFO_RF_RX_GAIN_K_A_5GL_8852B_ADDR;
+			default_value = EFUSE_INFO_RF_RX_GAIN_K_8852B_VALUE;
+			break;
+		case EFUSE_INFO_RF_RX_GAIN_K_A_5GM:
+			offset = EFUSE_INFO_RF_RX_GAIN_K_A_5GM_8852B_ADDR;
+			default_value = EFUSE_INFO_RF_RX_GAIN_K_8852B_VALUE;
+			break;
+		case EFUSE_INFO_RF_RX_GAIN_K_A_5GH:
+			offset = EFUSE_INFO_RF_RX_GAIN_K_A_5GH_8852B_ADDR;
+			default_value = EFUSE_INFO_RF_RX_GAIN_K_8852B_VALUE;
+			break;
+		/*Thermal*/
+		case EFUSE_INFO_RF_THERMAL_A:
+			offset = EFUSE_INFO_RF_THERMAL_A_8852B_ADDR;
+			default_value = EFUSE_INFO_RF_THERMAL_A_8852B_VALUE;
+			break;
+		case EFUSE_INFO_RF_THERMAL_B:
+			offset = EFUSE_INFO_RF_THERMAL_B_8852B_ADDR;
+			default_value = EFUSE_INFO_RF_THERMAL_B_8852B_VALUE;
+			break;
+		case EFUSE_INFO_RF_XTAL:
+			offset = EFUSE_INFO_RF_XTAL_8852B_ADDR;
+			default_value = EFUSE_INFO_RF_XTAL_8852B_VALUE;
+			break;
+		default:
+			return false;
+	}
+
+	if (autoload_status == 0)
+		hal_mem_cpy(hal, value, &default_value, 1);
+	else {
+		hal_mem_cpy(hal, value, efuse_map + offset, length);
+
+		if (id == EFUSE_INFO_RF_XTAL) {
+			if (*((u8 *)value) == 0xff)
+				hal_mem_set(hal, value, 0x3f, 1);
+		}	
+	}
+
+	return true;
+}
+
+#endif	/*#ifdef RF_8852B_SUPPORT*/

3rd/devourer/hal/halrf/g6/vendor/halrf_8852b/halrf_efuse_8852b.h

@@ -0,0 +1,111 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2020  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+#ifndef _HALRF_EFUSE_8852B_H_
+#define _HALRF_EFUSE_8852B_H_
+
+#ifdef RF_8852B_SUPPORT
+
+enum halrf_efsue_info_8852b_offset {
+	EFUSE_INFO_RF_BOARD_OPTION_8852B_ADDR	= 0x2c1,
+	EFUSE_INFO_RF_RFE_8852B_ADDR		= 0x2ca,
+	EFUSE_INFO_RF_CHAN_PLAN_8852B_ADDR	= 0x2b8,
+	EFUSE_INFO_RF_XTAL_8852B_ADDR		= 0x2b9,
+	EFUSE_INFO_RF_THERMAL_A_8852B_ADDR	= 0x2d0,
+	EFUSE_INFO_RF_THERMAL_B_8852B_ADDR	= 0x2d1,
+	EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_1_8852B_ADDR	= 0x210,
+	EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_2_8852B_ADDR	= 0x211,
+	EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_3_8852B_ADDR	= 0x212,
+	EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_4_8852B_ADDR	= 0x213,
+	EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_5_8852B_ADDR	= 0x214,
+	EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_6_8852B_ADDR	= 0x215,
+	EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_1_8852B_ADDR	= 0x216,
+	EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_2_8852B_ADDR	= 0x217,
+	EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_3_8852B_ADDR	= 0x218,
+	EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_4_8852B_ADDR	= 0x219,
+	EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_5_8852B_ADDR	= 0x21a,
+	EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_1_8852B_ADDR	= 0x222,
+	EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_2_8852B_ADDR	= 0x223,
+	EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_3_8852B_ADDR	= 0x224,
+	EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_4_8852B_ADDR	= 0x225,
+	EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_5_8852B_ADDR	= 0x226,
+	EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_6_8852B_ADDR	= 0x227,
+	EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_7_8852B_ADDR	= 0x228,
+	EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_8_8852B_ADDR	= 0x229,
+	EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_9_8852B_ADDR	= 0x22a,
+	EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_10_8852B_ADDR	= 0x22b,
+	EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_11_8852B_ADDR	= 0x22c,
+	EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_12_8852B_ADDR	= 0x22d,
+	EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_13_8852B_ADDR	= 0x22e,
+	EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_14_8852B_ADDR	= 0x22f,
+	EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_1_8852B_ADDR	= 0x23a,
+	EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_2_8852B_ADDR	= 0x23b,
+	EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_3_8852B_ADDR	= 0x23c,
+	EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_4_8852B_ADDR	= 0x23d,
+	EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_5_8852B_ADDR	= 0x23e,
+	EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_6_8852B_ADDR	= 0x23f,
+	EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_1_8852B_ADDR	= 0x240,
+	EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_2_8852B_ADDR	= 0x241,
+	EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_3_8852B_ADDR	= 0x242,
+	EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_4_8852B_ADDR	= 0x243,
+	EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_5_8852B_ADDR	= 0x244,
+	EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_1_8852B_ADDR	= 0x24c,
+	EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_2_8852B_ADDR	= 0x24d,
+	EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_3_8852B_ADDR	= 0x24e,
+	EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_4_8852B_ADDR	= 0x24f,
+	EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_5_8852B_ADDR	= 0x250,
+	EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_6_8852B_ADDR	= 0x251,
+	EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_7_8852B_ADDR	= 0x252,
+	EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_8_8852B_ADDR	= 0x253,
+	EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_9_8852B_ADDR	= 0x254,
+	EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_10_8852B_ADDR	= 0x255,
+	EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_11_8852B_ADDR	= 0x256,
+	EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_12_8852B_ADDR	= 0x257,
+	EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_13_8852B_ADDR	= 0x258,
+	EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_14_8852B_ADDR	= 0x259,
+	EFUSE_INFO_RF_RX_GAIN_K_A_2G_CCK_8852B_ADDR	= 0x2d6,
+	EFUSE_INFO_RF_RX_GAIN_K_A_2G_OFMD_8852B_ADDR	= 0x2d4,
+	EFUSE_INFO_RF_RX_GAIN_K_A_5GL_8852B_ADDR	= 0x2d8,
+	EFUSE_INFO_RF_RX_GAIN_K_A_5GM_8852B_ADDR	= 0x2da,
+	EFUSE_INFO_RF_RX_GAIN_K_A_5GH_8852B_ADDR	= 0x2dc
+};
+
+enum halrf_efsue_default_value_8852b {
+	EFUSE_INFO_RF_RFE_8852B_VALUE		= 0x1,
+	EFUSE_INFO_RF_CHAN_PLAN_8852B_VALUE	= 0x7f,
+	EFUSE_INFO_RF_XTAL_8852B_VALUE	= 0x3f,
+	EFUSE_INFO_RF_THERMAL_A_8852B_VALUE	= 0x22,
+	EFUSE_INFO_RF_THERMAL_B_8852B_VALUE	= 0x22,
+	EFUSE_INFO_RF_TSSI_DE_8852B_VALUE	= 0x0,
+	EFUSE_INFO_RF_RX_GAIN_K_8852B_VALUE	= 0xf,
+	EFUSE_INFO_RF_BOARD_OPTION_8852B_VALUE	= 0x1
+};
+
+bool halrf_get_efuse_info_8852b(struct rf_info *rf, u8 *efuse_map,
+		       enum rtw_efuse_info id, void *value, u32 length,
+		       u8 autoload_status);
+
+#endif	/*RF_8852B_SUPPORT*/
+#endif	/*_HALRF_EFUSE_8852B_H_*/
+

3rd/devourer/hal/halrf/g6/vendor/halrf_8852b/halrf_hwimg_8852b.h

@@ -0,0 +1,86 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2020  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+#ifndef _HALRF_HW_IMG_8852B_H_
+#define _HALRF_HW_IMG_8852B_H_
+#ifdef RF_8852B_SUPPORT
+
+#define DONT_CARE_8852B	0xff
+
+#define IF_8852B	0x8
+#define ELSE_IF_8852B	0x9
+#define ELSE_8852B	0xa
+#define END_8852B	0xb
+#define CHK_8852B	0x4
+
+#if 0
+#define RADIO_TO_FW_PAGE_SIZE 6
+#define RADIO_TO_FW_DATA_SIZE 500
+
+#define FWCMD_H2C_RADIO_A_INIT_0 0x0
+#define FWCMD_H2C_RADIO_A_INIT_1 0x1
+#define FWCMD_H2C_RADIO_A_INIT_2 0x2
+#define FWCMD_H2C_RADIO_A_INIT_3 0x3
+#define FWCMD_H2C_RADIO_A_INIT_4 0x4
+#define FWCMD_H2C_RADIO_A_INIT_5 0x5
+#define FWCMD_H2C_RADIO_A_INIT_6 0x6
+#define FWCMD_H2C_RADIO_A_INIT_7 0x7
+#define FWCMD_H2C_RADIO_A_INIT_8 0x8
+#define FWCMD_H2C_RADIO_A_INIT_9 0x9
+
+#define FWCMD_H2C_RADIO_B_INIT_0 0x0
+#define FWCMD_H2C_RADIO_B_INIT_1 0x1
+#define FWCMD_H2C_RADIO_B_INIT_2 0x2
+#define FWCMD_H2C_RADIO_B_INIT_3 0x3
+#define FWCMD_H2C_RADIO_B_INIT_4 0x4
+#define FWCMD_H2C_RADIO_B_INIT_5 0x5
+#define FWCMD_H2C_RADIO_B_INIT_6 0x6
+#define FWCMD_H2C_RADIO_B_INIT_7 0x7
+#define FWCMD_H2C_RADIO_B_INIT_8 0x8
+#define FWCMD_H2C_RADIO_B_INIT_9 0x9
+
+struct halrf_radio_info {
+	u32 write_times_a;
+	u32 write_times_b;
+	u32 radio_a_parameter[RADIO_TO_FW_PAGE_SIZE][RADIO_TO_FW_DATA_SIZE];
+	u32 radio_b_parameter[RADIO_TO_FW_PAGE_SIZE][RADIO_TO_FW_DATA_SIZE];
+};
+
+#endif
+void halrf_config_8852b_nctl_reg(struct rf_info *rf);
+void halrf_config_8852b_radio_a_reg(struct rf_info *rf, enum phl_phy_idx phy);
+void halrf_config_8852b_radio_b_reg(struct rf_info *rf, enum phl_phy_idx phy);
+void halrf_config_8852b_store_power_by_rate(struct rf_info *rf, enum phl_phy_idx phy);
+void halrf_config_8852b_store_power_limit(struct rf_info *rf, enum phl_phy_idx phy);
+void halrf_config_8852b_store_power_limit_ru(struct rf_info *rf, enum phl_phy_idx phy);
+void halrf_config_8852b_store_pwr_track(struct rf_info *rf, enum phl_phy_idx phy);
+void halrf_config_8852b_store_xtal_track(struct rf_info *rf, enum phl_phy_idx phy);
+
+u32 halrf_get_8852b_nctl_reg_ver(void);
+u32 halrf_get_8852b_radio_reg_ver(void);
+
+void halrf_config_8852b_radio_to_fw(struct rf_info *rf);
+
+#endif
+#endif /*  _HALRF_HW_IMG_8852b_H_ */

3rd/devourer/hal/halrf/g6/vendor/halrf_8852b/halrf_iqk_8852b.h

@@ -0,0 +1,106 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2020  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+#ifndef __HALRF_IQK_8852BH__
+#define __HALRF_IQK_8852BH__
+#ifdef RF_8852B_SUPPORT
+
+#define iqk_version_8852b 0x29
+#define ss_8852b 2
+#define mac_reg_num_8852b 2
+#define bb_reg_num_8852b 1
+#define rf_reg_num_8852b 6
+#define iqk_delay_8852b 1
+#define iqk_step_8852b 2
+#define rxk_step_8852b 4
+#define path_baseaddr 0x8
+#define txagck 0
+#define lok 1
+#define txk 2
+#define rxk 3
+#define IQK_THR_ReK 8
+
+
+void halrf_iqk_8852b(struct rf_info *rf, enum phl_phy_idx phy_idx, bool force);
+
+//cv b
+void iqk_init_8852b(struct rf_info *rf);
+void halrf_iqk_8852b(struct rf_info *rf, enum phl_phy_idx phy_idx, bool force);
+void halrf_doiqk_8852b(struct rf_info *rf, bool force,
+			enum phl_phy_idx phy_idx, u8 path);
+void iqk_get_ch_info_8852b(struct rf_info *rf, enum phl_phy_idx phy, u8 path);
+bool iqk_mcc_page_sel_8852b(struct rf_info *rf, enum phl_phy_idx phy, u8 path);
+void iqk_macbb_setting_8852b(struct rf_info *rf, enum phl_phy_idx phy_idx, u8 path);
+void iqk_preset_8852b(struct rf_info *rf, u8 path);
+void iqk_start_iqk_8852b(struct rf_info *rf, enum phl_phy_idx phy_idx,
+			  u8 path);
+void iqk_restore_8852b(struct rf_info *rf, u8 path);
+void iqk_afebb_restore_8852b(struct rf_info *rf, enum phl_phy_idx phy_idx, u8 path);
+void halrf_iqk_reload_8852b(struct rf_info *rf, u8 path);
+void halrf_nbiqk_enable_8852b(struct rf_info *rf, bool nbiqk_en);
+void halrf_iqk_toneleakage_8852b(struct rf_info *rf, u8 path);
+void halrf_iqk_sram_enable_8852b(struct rf_info *rf, bool iqk_sram_en);
+void halrf_iqk_xym_enable_8852b(struct rf_info *rf, bool iqk_xym_en);
+void halrf_iqk_fft_enable_8852b(struct rf_info *rf, bool iqk_fft_en);
+void halrf_iqk_cfir_enable_8852b(struct rf_info *rf, bool iqk_cfir_en);
+void halrf_iqk_onoff_8852b(struct rf_info *rf, bool is_enable);
+void halrf_iqk_lok_bypass_8852b(struct rf_info *rf, u8 path);
+void halrf_iqk_rx_bypass_8852b(struct rf_info *rf, u8 path);
+void halrf_iqk_tx_bypass_8852b(struct rf_info *rf, u8 path);
+
+void iqk_backup_mac_bb_8852b(struct rf_info *rf, u8 path,
+			     u32 backup_mac[mac_reg_num_8852b],
+			     u32 backup_bb[bb_reg_num_8852b],
+			     u32 backup_mac_reg[mac_reg_num_8852b],
+			     u32 backup_bb_reg[bb_reg_num_8852b]);
+void iqk_backup_rf_8852b(struct rf_info *rf, u8 path,
+			 u32 backup_rf[][rf_reg_num_8852b],
+			 u32 backup_rf_reg[][rf_reg_num_8852b]);
+void iqk_restore_mac_bb_8852b(struct rf_info *rf, u8 path,
+			      u32 backup_mac[mac_reg_num_8852b],
+			      u32 backup_bb[bb_reg_num_8852b],
+			      u32 backup_mac_reg[mac_reg_num_8852b],
+			      u32 backup_bb_reg[bb_reg_num_8852b]);
+void iqk_restore_rf_8852b(struct rf_info *rf, u8 path,
+			  u32 backup_rf[][rf_reg_num_8852b],
+			  u32 backup_rf_reg[][rf_reg_num_8852b]);
+
+void halrf_iqk_track_8852b(struct rf_info *rf);
+
+bool halrf_iqk_get_ther_rek_8852b(struct rf_info *rf );
+void halrf_iqk_dbcc_8852b(struct rf_info *rf, u8 path);
+u8 halrf_iqk_get_mcc_ch0_8852b(struct rf_info *rf );
+u8 halrf_iqk_get_mcc_ch1_8852b(struct rf_info *rf );
+bool halrf_check_fwiqk_done_8852b(struct rf_info *rf);
+void iqk_set_info_8852b(struct rf_info *rf, enum phl_phy_idx phy_idx, u8 path);
+void halrf_enable_fw_iqk_8852b(struct rf_info *rf, bool is_fw_iqk);
+u8 halrf_get_iqk_times_8852b(struct rf_info *rf) ;
+u32 halrf_get_iqk_ver_8852b(void);
+u8 halrf_iqk_get_rxevm_8852b(struct rf_info *rf);
+u32 halrf_iqk_get_rximr_8852b(struct rf_info *rf, u8 path, u32 idx);
+
+
+#endif
+#endif /*  __HALRF_IQK_8852BH__ */
+

3rd/devourer/hal/halrf/g6/vendor/halrf_8852b/halrf_kfree_8852b.c

@@ -0,0 +1,323 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2019 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#include "../halrf_precomp.h"
+
+#ifdef RF_8852B_SUPPORT
+
+void _halrf_get_total_efuse_8852b(struct rf_info *rf,
+					enum phl_phy_idx phy)
+{
+	struct halrf_kfree_info *kfree = &rf->kfree_info;
+	u32 i, array_size = sizeof(kfree->efuse_content);
+
+	if (array_size < HIDE_EFUSE_SIZE_8852B) {
+		RF_DBG(rf, DBG_RF_TSSI_TRIM, "======> %s   sizeof(kfree->efuse_content)(0x%x) < HIDE_EFUSE_SIZE_8852B(0x%x)\n",
+			__func__, array_size, HIDE_EFUSE_SIZE_8852B);
+		return;
+	}
+
+	halrf_phy_efuse_get_info(rf, HIDE_EFUSE_START_ADDR_8852B,
+		HIDE_EFUSE_SIZE_8852B, kfree->efuse_content);
+
+	for (i = 0; i < HIDE_EFUSE_SIZE_8852B; i++)
+		RF_DBG(rf, DBG_RF_TSSI_TRIM, "======> %s   efuse_con[0x%x] = 0x%x\n",
+			__func__, i + HIDE_EFUSE_START_ADDR_8852B, kfree->efuse_content[i]);
+}
+
+u8 _halrf_get_1byte_efuse_8852b(struct rf_info *rf, u32 addr, u8 *value)
+{
+	struct halrf_kfree_info *kfree = &rf->kfree_info;
+
+	if (addr < HIDE_EFUSE_START_ADDR_8852B || addr > HIDE_EFUSE_END_ADDR_8852B) {
+		RF_DBG(rf, DBG_RF_TSSI_TRIM, "===> %s addr(0x%x) < 0x%x(Min), > 0x%x(Max) Over Range Return !!!\n",
+			__func__, addr, HIDE_EFUSE_START_ADDR_8852B, HIDE_EFUSE_END_ADDR_8852B);
+		return 0xff;
+	}
+
+	*value = kfree->efuse_content[addr - HIDE_EFUSE_START_ADDR_8852B];
+
+	return *value;
+}
+
+s8 _halrf_efuse_exchange_8852b(struct rf_info *rf, u8 value, u8 mask)
+{
+	s8 tmp = 0;
+
+	if (mask == LOW_MASK) {
+		tmp = value & 0xf;
+
+		if (tmp & BIT(3))
+			tmp = tmp | 0xf0;
+	} else {
+		tmp = (value & 0xf0) >> 4;
+
+		if (tmp & BIT(3))
+			tmp = tmp | 0xf0;
+	}
+
+	return tmp;
+}
+
+void _halrf_set_thermal_trim_8852b(struct rf_info *rf,
+					enum phl_phy_idx phy)
+{
+	u8 thermal_a = 0xff, thermal_b = 0xff, tmp = 0;
+
+	RF_DBG(rf, DBG_RF_THER_TRIM, "======> %s   phy=%d\n", __func__, phy);
+
+	if (!(rf->support_ability & HAL_RF_THER_TRIM)) {
+		RF_DBG(rf, DBG_RF_THER_TRIM, "<== %s phy=%d support_ability=0x%x Ther Trim Off!!!\n",
+			__func__, phy, rf->support_ability);
+		return;
+	}
+
+	tmp = _halrf_get_1byte_efuse_8852b(rf, THERMAL_TRIM_HIDE_EFUSE_A_8852B, &thermal_a);
+
+	tmp = _halrf_get_1byte_efuse_8852b(rf, THERMAL_TRIM_HIDE_EFUSE_B_8852B, &thermal_b);
+
+	RF_DBG(rf, DBG_RF_THER_TRIM, "efuse Ther_A=0x%x Ther_B=0x%x\n",
+		thermal_a, thermal_b);
+
+	if (thermal_a == 0xff && thermal_b == 0xff) {
+		RF_DBG(rf, DBG_RF_THER_TRIM, "Ther_A, Ther_B=0xff no PG Return!!!\n");
+		return; 
+	}
+
+	thermal_a = thermal_a & 0xf;
+	thermal_a = ((thermal_a & 0x1) << 3) | (thermal_a >> 1);
+
+	thermal_b = thermal_b & 0xf;
+	thermal_b = ((thermal_b & 0x1) << 3) | (thermal_b >> 1);
+
+	RF_DBG(rf, DBG_RF_THER_TRIM, "After Exchange Ther_A=0x%x Ther_B=0x%x\n",
+		thermal_a, thermal_b);
+
+	halrf_wrf(rf, RF_PATH_A, 0x43, 0x000f0000, thermal_a & 0xf);
+	halrf_wrf(rf, RF_PATH_B, 0x43, 0x000f0000, thermal_b & 0xf);
+}
+
+void _halrf_set_pa_bias_trim_8852b(struct rf_info *rf,
+					enum phl_phy_idx phy)
+{
+	u8 pa_bias_a = 0xff, pa_bias_b = 0xff, tmp = 0;
+	u8 pa_bias_a_2g, pa_bias_b_2g, pa_bias_a_5g, pa_bias_b_5g;
+
+	RF_DBG(rf, DBG_RF_PABIAS_TRIM, "======> %s   phy=%d\n", __func__, phy);
+
+	if (!(rf->support_ability & HAL_RF_PABIAS_TRIM)) {
+		RF_DBG(rf, DBG_RF_PABIAS_TRIM, "<== %s phy=%d support_ability=0x%x PA Bias K Off!!!\n",
+			__func__, phy, rf->support_ability);
+		return;
+	}
+
+	tmp = _halrf_get_1byte_efuse_8852b(rf, PABIAS_TRIM_HIDE_EFUSE_A_8852B, &pa_bias_a);
+
+	tmp = _halrf_get_1byte_efuse_8852b(rf, PABIAS_TRIM_HIDE_EFUSE_B_8852B, &pa_bias_b);
+
+	RF_DBG(rf, DBG_RF_PABIAS_TRIM, "efuse PA_Bias_A=0x%x PA_Bias_B=0x%x\n",
+		pa_bias_a, pa_bias_b);
+
+	if (pa_bias_a == 0xff && pa_bias_b == 0xff) {
+		RF_DBG(rf, DBG_RF_PABIAS_TRIM, "PA_Bias_A, PA_Bias_B=0xff no PG Return!!!\n");
+		return; 
+	}
+
+	pa_bias_a_2g = pa_bias_a & 0xf;
+	pa_bias_a_5g = (pa_bias_a & 0xf0) >> 4;
+
+	pa_bias_b_2g = pa_bias_b & 0xf;
+	pa_bias_b_5g = (pa_bias_b & 0xf0) >> 4;
+
+	RF_DBG(rf, DBG_RF_PABIAS_TRIM, "After Calculate PA_Bias_A_2G=0x%x PA_Bias_A_5G=0x%x\n",
+		pa_bias_a_2g, pa_bias_a_5g);
+
+	RF_DBG(rf, DBG_RF_PABIAS_TRIM, "After Calculate PA_Bias_B_2G=0x%x PA_Bias_B_5G=0x%x\n",
+		pa_bias_b_2g, pa_bias_b_5g);
+
+	halrf_wrf(rf, RF_PATH_A, 0x60, 0x0000f000, pa_bias_a_2g);
+	halrf_wrf(rf, RF_PATH_A, 0x60, 0x000f0000, pa_bias_a_5g);
+
+	halrf_wrf(rf, RF_PATH_B, 0x60, 0x0000f000, pa_bias_b_2g);
+	halrf_wrf(rf, RF_PATH_B, 0x60, 0x000f0000, pa_bias_b_5g);
+}
+
+void _halrf_get_tssi_trim_8852b(struct rf_info *rf,
+					enum phl_phy_idx phy)
+{
+	struct halrf_tssi_info *tssi = &rf->tssi;
+	u8 i, j , check_tmp = 0;
+
+	RF_DBG(rf, DBG_RF_TSSI_TRIM, "======> %s   phy=%d\n", __func__, phy);
+
+	if (!(rf->support_ability & HAL_RF_TSSI_TRIM)) {
+		RF_DBG(rf, DBG_RF_TSSI_TRIM, "<== %s phy=%d support_ability=0x%x TSSI Trim Off!!!\n",
+			__func__, phy, rf->support_ability);
+		return;
+	}
+
+	_halrf_get_1byte_efuse_8852b(rf, TSSI_TRIM_HIDE_EFUSE_2GL_A_8852B,
+		(u8 *)&tssi->tssi_trim[RF_PATH_A][0]);
+	_halrf_get_1byte_efuse_8852b(rf, TSSI_TRIM_HIDE_EFUSE_2GH_A_8852B,
+		(u8 *)&tssi->tssi_trim[RF_PATH_A][1]);
+
+	_halrf_get_1byte_efuse_8852b(rf, TSSI_TRIM_HIDE_EFUSE_5GL1_A_8852B,
+		(u8 *)&tssi->tssi_trim[RF_PATH_A][2]);
+	_halrf_get_1byte_efuse_8852b(rf, TSSI_TRIM_HIDE_EFUSE_5GL2_A_8852B,
+		(u8 *)&tssi->tssi_trim[RF_PATH_A][3]);
+	_halrf_get_1byte_efuse_8852b(rf, TSSI_TRIM_HIDE_EFUSE_5GM1_A_8852B,
+		(u8 *)&tssi->tssi_trim[RF_PATH_A][4]);
+	_halrf_get_1byte_efuse_8852b(rf, TSSI_TRIM_HIDE_EFUSE_5GM2_A_8852B,
+		(u8 *)&tssi->tssi_trim[RF_PATH_A][5]);
+	_halrf_get_1byte_efuse_8852b(rf, TSSI_TRIM_HIDE_EFUSE_5GH1_A_8852B,
+		(u8 *)&tssi->tssi_trim[RF_PATH_A][6]);
+	_halrf_get_1byte_efuse_8852b(rf, TSSI_TRIM_HIDE_EFUSE_5GH2_A_8852B,
+		(u8 *)&tssi->tssi_trim[RF_PATH_A][7]);
+
+	_halrf_get_1byte_efuse_8852b(rf, TSSI_TRIM_HIDE_EFUSE_2GL_B_8852B,
+		(u8 *)&tssi->tssi_trim[RF_PATH_B][0]);
+	_halrf_get_1byte_efuse_8852b(rf, TSSI_TRIM_HIDE_EFUSE_2GH_B_8852B,
+		(u8 *)&tssi->tssi_trim[RF_PATH_B][1]);
+
+	_halrf_get_1byte_efuse_8852b(rf, TSSI_TRIM_HIDE_EFUSE_5GL1_B_8852B,
+		(u8 *)&tssi->tssi_trim[RF_PATH_B][2]);
+	_halrf_get_1byte_efuse_8852b(rf, TSSI_TRIM_HIDE_EFUSE_5GL2_B_8852B,
+		(u8 *)&tssi->tssi_trim[RF_PATH_B][3]);
+	_halrf_get_1byte_efuse_8852b(rf, TSSI_TRIM_HIDE_EFUSE_5GM1_B_8852B,
+		(u8 *)&tssi->tssi_trim[RF_PATH_B][4]);
+	_halrf_get_1byte_efuse_8852b(rf, TSSI_TRIM_HIDE_EFUSE_5GM2_B_8852B,
+		(u8 *)&tssi->tssi_trim[RF_PATH_B][5]);
+	_halrf_get_1byte_efuse_8852b(rf, TSSI_TRIM_HIDE_EFUSE_5GH1_B_8852B,
+		(u8 *)&tssi->tssi_trim[RF_PATH_B][6]);
+	_halrf_get_1byte_efuse_8852b(rf, TSSI_TRIM_HIDE_EFUSE_5GH2_B_8852B,
+		(u8 *)&tssi->tssi_trim[RF_PATH_B][7]);
+
+	for (i = 0; i < 2; i++) {
+		for (j = 0; j < TSSI_HIDE_EFUSE_NUM; j++) {
+			RF_DBG(rf, DBG_RF_TSSI_TRIM, "tssi->tssi_trim[%d][%d]=0x%x\n", i, j, tssi->tssi_trim[i][j]);
+			if ((tssi->tssi_trim[i][j] & 0xff) == 0xff)
+				check_tmp++;
+		}
+	}
+
+	RF_DBG(rf, DBG_RF_TSSI_TRIM, "check_tmp=%d\n", check_tmp);
+
+	if (check_tmp == 2 * TSSI_HIDE_EFUSE_NUM) {
+		for (i = 0; i < 2; i++) {
+			for (j = 0; j < TSSI_HIDE_EFUSE_NUM; j++)
+				tssi->tssi_trim[i][j] = 0;
+		}
+
+		RF_DBG(rf, DBG_RF_TSSI_TRIM, "TSSI Trim no PG tssi->tssi_trim=0x0\n");
+	}
+
+}
+
+void halrf_get_efuse_trim_8852b(struct rf_info *rf,
+					enum phl_phy_idx phy)
+{
+	_halrf_get_total_efuse_8852b(rf, phy);
+
+	halrf_write_fwofld_start(rf);	/*FW Offload Start*/
+
+	_halrf_set_thermal_trim_8852b(rf, phy);
+	_halrf_set_pa_bias_trim_8852b(rf, phy);
+
+	halrf_write_fwofld_end(rf);	/*FW Offload End*/
+	
+	_halrf_get_tssi_trim_8852b(rf, phy);
+}
+
+void halrf_kfree_get_info_8852b(struct rf_info *rf, char input[][16], u32 *_used,
+			 char *output, u32 *_out_len)
+{
+	u8 tmp;
+
+	RF_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
+		 "\n=====================[ KFREE info ]=====================\n");
+
+	RF_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
+		" %-30s : 0x%X = 0x%X\n",
+		"Thermal 2G A Efuse",
+		THERMAL_TRIM_HIDE_EFUSE_A_8852B,
+		_halrf_get_1byte_efuse_8852b(rf, THERMAL_TRIM_HIDE_EFUSE_A_8852B, &tmp));
+
+	RF_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
+		" %-30s : %s = 0x%X\n",
+		"Thermal 2G A RFC",
+		"0x43[19:16]",
+		halrf_rrf(rf, RF_PATH_A, 0x43, 0x000f0000));
+
+	RF_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
+		" %-30s : 0x%X = 0x%X\n",
+		"Thermal 2G B Efuse",
+		THERMAL_TRIM_HIDE_EFUSE_B_8852B,
+		_halrf_get_1byte_efuse_8852b(rf, THERMAL_TRIM_HIDE_EFUSE_B_8852B, &tmp));
+
+	RF_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
+		" %-30s : %s = 0x%X\n",
+		"Thermal 2G B RFC",
+		"0x43[19:16]",
+		halrf_rrf(rf, RF_PATH_B, 0x43, 0x000f0000));
+
+	RF_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
+		" %-30s : 0x%X = 0x%X\n",
+		"PABias 2G A Efuse",
+		PABIAS_TRIM_HIDE_EFUSE_A_8852B,
+		_halrf_get_1byte_efuse_8852b(rf, PABIAS_TRIM_HIDE_EFUSE_A_8852B, &tmp));
+
+	RF_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
+		" %-30s : %s = 0x%X\n",
+		"PABias 2G A RFC",
+		"0x60[15:12]",
+		halrf_rrf(rf, RF_PATH_A, 0x60, 0x0000f000));
+
+	RF_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
+		" %-30s : 0x%X = 0x%X\n",
+		"PABias 2G B Efuse",
+		PABIAS_TRIM_HIDE_EFUSE_B_8852B,
+		_halrf_get_1byte_efuse_8852b(rf, PABIAS_TRIM_HIDE_EFUSE_B_8852B, &tmp));
+
+	RF_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
+		" %-30s : %s = 0x%X\n",
+		"PABias 2G B RFC",
+		"0x60[15:12]",
+		halrf_rrf(rf, RF_PATH_B, 0x60, 0x0000f000));
+
+	RF_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
+		" %-30s : 0x%X = 0x%X\n",
+		"PABias 5G A Efuse",
+		PABIAS_TRIM_HIDE_EFUSE_A_8852B,
+		_halrf_get_1byte_efuse_8852b(rf, PABIAS_TRIM_HIDE_EFUSE_A_8852B, &tmp));
+
+	RF_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
+		" %-30s : %s = 0x%X\n",
+		"PABias 5G A RFC",
+		"0x60[19:16]",
+		halrf_rrf(rf, RF_PATH_A, 0x60, 0x000f0000));
+
+	RF_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
+		" %-30s : 0x%X = 0x%X\n",
+		"PABias 5G B Efuse",
+		PABIAS_TRIM_HIDE_EFUSE_B_8852B,
+		_halrf_get_1byte_efuse_8852b(rf, PABIAS_TRIM_HIDE_EFUSE_B_8852B, &tmp));
+
+	RF_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
+		" %-30s : %s = 0x%X\n",
+		"PABias 5G B RFC",
+		"0x60[19:16]",
+		halrf_rrf(rf, RF_PATH_B, 0x60, 0x000f0000));
+}
+
+#endif	/*RF_8852B_SUPPORT*/

3rd/devourer/hal/halrf/g6/vendor/halrf_8852b/halrf_kfree_8852b.h

@@ -0,0 +1,58 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2019 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef _HALRF_KFREE_8852B_H_
+#define _HALRF_KFREE_8852B_H_
+#ifdef RF_8852B_SUPPORT
+
+/*@--------------------------Define Parameters-------------------------------*/
+
+#define HIDE_EFUSE_START_ADDR_8852B	 0x5A0
+#define HIDE_EFUSE_END_ADDR_8852B	 0x5DF
+#define HIDE_EFUSE_SIZE_8852B		 HIDE_EFUSE_END_ADDR_8852B - HIDE_EFUSE_START_ADDR_8852B + 1
+
+#define THERMAL_TRIM_HIDE_EFUSE_A_8852B 0x5DF
+#define THERMAL_TRIM_HIDE_EFUSE_B_8852B 0x5DC
+
+#define PABIAS_TRIM_HIDE_EFUSE_A_8852B 0x5DE
+#define PABIAS_TRIM_HIDE_EFUSE_B_8852B 0x5DB
+
+#define TSSI_TRIM_HIDE_EFUSE_2GL_A_8852B 0x5D6
+#define TSSI_TRIM_HIDE_EFUSE_2GH_A_8852B 0x5D5
+#define TSSI_TRIM_HIDE_EFUSE_5GL1_A_8852B 0x5D4
+#define TSSI_TRIM_HIDE_EFUSE_5GL2_A_8852B 0x5D3
+#define TSSI_TRIM_HIDE_EFUSE_5GM1_A_8852B 0x5D2
+#define TSSI_TRIM_HIDE_EFUSE_5GM2_A_8852B 0x5D1
+#define TSSI_TRIM_HIDE_EFUSE_5GH1_A_8852B 0x5D0
+#define TSSI_TRIM_HIDE_EFUSE_5GH2_A_8852B 0x5CF
+
+#define TSSI_TRIM_HIDE_EFUSE_2GL_B_8852B 0x5AB
+#define TSSI_TRIM_HIDE_EFUSE_2GH_B_8852B 0x5AA
+#define TSSI_TRIM_HIDE_EFUSE_5GL1_B_8852B 0x5A9
+#define TSSI_TRIM_HIDE_EFUSE_5GL2_B_8852B 0x5A8
+#define TSSI_TRIM_HIDE_EFUSE_5GM1_B_8852B 0x5A7
+#define TSSI_TRIM_HIDE_EFUSE_5GM2_B_8852B 0x5A6
+#define TSSI_TRIM_HIDE_EFUSE_5GH1_B_8852B 0x5A5
+#define TSSI_TRIM_HIDE_EFUSE_5GH2_B_8852B 0x5A4
+
+/*@-----------------------End Define Parameters-----------------------*/
+
+void halrf_get_efuse_trim_8852b(struct rf_info *rf,
+					enum phl_phy_idx phy);
+
+void halrf_kfree_get_info_8852b(struct rf_info *rf, char input[][16], u32 *_used,
+			 char *output, u32 *_out_len);
+
+#endif
+#endif	/*_HALRF_SET_PWR_TABLE_8852B_H_*/

3rd/devourer/hal/halrf/g6/vendor/halrf_8852b/halrf_ops_rtl8852b.c

@@ -0,0 +1,50 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2023  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+#include "../halrf_precomp.h"
+#ifdef RF_8852B_SUPPORT
+
+static struct halrf_rfk_ops rfk_ops_8852b= {
+	.ops_rx_dck = halrf_rx_dck_8852b,
+	.ops_do_txgapk = halrf_do_txgapk_8852b,
+	.ops_tssi_disable = halrf_tssi_disable_8852b,
+	.ops_do_tssi = halrf_do_tssi_8852b,
+	.ops_dpk = halrf_dpk_8852b,
+	.ops_dack = halrf_dac_cal_8852b,
+	.ops_lo_test = halrf_lo_test_8852b,
+	.ops_config_radio_to_fw = halrf_config_8852b_radio_to_fw,	
+	.ops_txgapk_w_table_default = halrf_txgapk_write_table_default_8852b,
+	.ops_txgapk_enable = halrf_txgapk_enable_8852b,
+	.ops_txgapk_init = halrf_txgapk_init_8852b,
+#ifdef HALRF_MCC_DBCC
+	.ops_chlk_reload_check = halrf_chlk_reload_check_8852b,
+#endif
+};
+
+void rf_set_ops_8852b(struct rf_info *rf) {
+
+	rf->rf_rfk_ops = &rfk_ops_8852b;
+}
+
+#endif

3rd/devourer/hal/halrf/g6/vendor/halrf_8852b/halrf_ops_rtl8852b.h

@@ -0,0 +1,34 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2023  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+#ifndef __HALRF_OPS_RTL8852B_H__
+#define __HALRF_OPS_RTL8852B__
+#ifdef RF_8852B_SUPPORT
+
+
+void rf_set_ops_8852b(struct rf_info *rf) ;
+
+
+#endif
+#endif /*  __HALRF_OPS_RTL8852B_H__ */

3rd/devourer/hal/halrf/g6/vendor/halrf_8852b/halrf_psd_8852b.h

@@ -0,0 +1,41 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2019 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef _HALRF_PSD_TSSI_8852B_H_
+#define _HALRF_PSD_TSSI_8852B_H_
+
+#ifdef RF_8852B_SUPPORT
+#ifdef HALRF_PSD_SUPPORT
+
+#define PSD_VER_8852B 0x1
+#define PSD_BACKUP_NUM_8852B 41
+
+/*@--------------------------Define Parameters-------------------------------*/
+/*@-----------------------End Define Parameters-----------------------*/
+
+void halrf_psd_init_8852b(struct rf_info *rf, enum phl_phy_idx phy,
+			u8 path, u8 iq_path, u32 avg, u32 fft);
+			
+void halrf_psd_restore_8852b(struct rf_info *rf, enum phl_phy_idx phy);	
+			
+u32 halrf_psd_get_point_data_8852b(struct rf_info *rf,
+			enum phl_phy_idx phy, s32 point);
+			
+void halrf_psd_query_8852b(struct rf_info *rf, enum phl_phy_idx phy,
+			u32 point, u32 start_point, u32 stop_point, u32 *outbuf);
+
+#endif	/*HALRF_PSD_SUPPORT*/
+#endif	/*RF_8852B_SUPPORT*/
+#endif	/*_HALRF_PSD_TSSI_8852B_H_*/
+

3rd/devourer/hal/halrf/g6/vendor/halrf_8852b/halrf_reg_cfg_8852b.c

@@ -0,0 +1,64 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#include "../halrf_precomp.h"
+#ifdef RF_8852B_SUPPORT
+
+void halrf_cfg_rf_radio_a_8852b(struct rf_info *rf, u32 addr, u32 data)
+{
+	/*laod radio a table*/
+	halrf_wrf(rf, RF_PATH_A, addr, MASKRF, data);
+	RF_DBG(rf, DBG_RF_INIT, "[RF_a] %08X %08X\n", addr, data);
+}
+
+void halrf_cfg_rf_radio_b_8852b(struct rf_info *rf, u32 addr, u32 data)
+{
+	/*laod radio b table*/
+	halrf_wrf(rf, RF_PATH_B, addr, MASKRF, data);
+	RF_DBG(rf, DBG_RF_INIT, "[RF_b] %08X %08X\n", addr, data);
+}
+
+void halrf_cfg_rf_nctl_8852b(struct rf_info *rf, u32 addr, u32 mask, u32 data)
+{
+/*laod NCTL table*/
+	if (addr == 0xfe)
+		halrf_delay_ms(rf, 50);
+	else if (addr == 0xfd)
+		halrf_delay_ms(rf, 5);
+	else if (addr == 0xfc)
+		halrf_delay_ms(rf, 1);
+	else if (addr == 0xfb)
+		halrf_delay_us(rf, 50);
+	else if (addr == 0xfa)
+		halrf_delay_us(rf, 5);
+	else if (addr == 0xf9)
+		halrf_delay_us(rf, 1);
+	else
+		halrf_wreg(rf, addr, mask, data);
+	
+	RF_DBG(rf, DBG_RF_INIT, "[RFK] %08X %08X\n", addr, data);
+}
+
+#endif

3rd/devourer/hal/halrf/g6/vendor/halrf_8852b/halrf_reg_cfg_8852b.h

@@ -0,0 +1,35 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+#ifndef _HALRF_REG_CFG_8852B_H_
+#define _HALRF_REG_CFG_8852B_H_
+
+#ifdef RF_8852B_SUPPORT
+
+void halrf_cfg_rf_radio_a_8852b(struct rf_info *rf, u32 addr, u32 data);
+void halrf_cfg_rf_radio_b_8852b(struct rf_info *rf, u32 addr, u32 data);
+void halrf_cfg_rf_nctl_8852b(struct rf_info *rf, u32 addr, u32 mask, u32 data);
+
+#endif
+#endif /* RTL8822C_SUPPORT*/

3rd/devourer/hal/halrf/g6/vendor/halrf_8852b/halrf_set_pwr_table_8852b.h

@@ -0,0 +1,54 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2019 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef _HALRF_SET_PWR_TABLE_8852B_H_
+#define _HALRF_SET_PWR_TABLE_8852B_H_
+
+#ifdef RF_8852B_SUPPORT
+
+/*@--------------------------Define Parameters-------------------------------*/
+#define MAX_TX_PATH	2
+#define TPU_SIZE_RUA	3 /*{26, 52, 106}*/
+#define TPU_SIZE_BW20_SC  8 /*8 * 20M = 160M*/
+
+/*@-----------------------End Define Parameters-----------------------*/
+
+bool halrf_set_power_by_rate_to_mac_8852b(struct rf_info *rf,
+						enum phl_phy_idx phy);
+
+void halrf_set_fix_power_to_struct_8852b(struct rf_info *rf,
+					enum phl_phy_idx phy, s8 dbm);
+
+bool halrf_set_power_limit_to_mac_8852b(struct rf_info *rf,
+	enum phl_phy_idx phy);
+
+void halrf_set_ref_power_to_struct_8852b(struct rf_info *rf,
+						enum phl_phy_idx phy);
+
+bool halrf_set_power_8852b(struct rf_info *rf, enum phl_phy_idx phy,
+	enum phl_pwr_table pwr_table);
+
+void halrf_pwr_by_rate_info_8852b(struct rf_info *rf,
+		char input[][16], u32 *_used, char *output, u32 *_out_len);
+
+void halrf_pwr_limit_info_8852b(struct rf_info *rf,
+		char input[][16], u32 *_used, char *output, u32 *_out_len);
+
+void halrf_pwr_limit_ru_info_8852b(struct rf_info *rf,
+		char input[][16], u32 *_used, char *output, u32 *_out_len);
+
+void halrf_set_tx_shape_8852b(struct rf_info *rf, u8 tx_shape_idx);
+
+#endif	/*RF_8852B_SUPPORT*/
+#endif	/*_HALRF_SET_PWR_TABLE_8852B_H_*/

3rd/devourer/hal/halrf/g6/vendor/halrf_8852b/halrf_tssi_8852b.h

@@ -0,0 +1,74 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2019 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef _HALRF_TSSI_8852B_H_
+#define _HALRF_TSSI_8852B_H_
+#ifdef RF_8852B_SUPPORT
+
+#define TSSI_VER_8852B 0x34
+#define TSSI_PATH_MAX_8852B 2
+
+/*@--------------------------Define Parameters-------------------------------*/
+
+
+/*@-----------------------End Define Parameters-----------------------*/
+void halrf_tssi_get_efuse_8852b(struct rf_info *rf,
+						enum phl_phy_idx phy);
+bool halrf_tssi_check_efuse_data_8852b(struct rf_info *rf,
+						enum phl_phy_idx phy);
+void halrf_set_tssi_de_for_tx_verify_8852b(struct rf_info *rf,
+				enum phl_phy_idx phy, u32 tssi_de, u8 path);
+void halrf_set_tssi_de_offset_8852b(struct rf_info *rf,
+				enum phl_phy_idx phy, u32 tssi_de_offset, u8 path);
+void halrf_set_tssi_de_offset_zero_8852b(struct rf_info *rf,
+							enum phl_phy_idx phy);
+void halrf_do_tssi_8852b(struct rf_info *rf, enum phl_phy_idx phy, bool hwtx_en);
+void halrf_do_tssi_scan_8852b(struct rf_info *rf, enum phl_phy_idx phy);
+void halrf_tssi_enable_8852b(struct rf_info *rf, enum phl_phy_idx phy);
+void halrf_tssi_disable_8852b(struct rf_info *rf, enum phl_phy_idx phy);
+s32 halrf_get_online_tssi_de_8852b(struct rf_info *rf, enum phl_phy_idx phy_idx,
+				u8 path, s32 dbm, s32 puot);
+void halrf_tssi_cck_8852b(struct rf_info *rf, enum phl_phy_idx phy,
+				bool is_cck);
+void halrf_set_tssi_avg_mp_8852b(struct rf_info *rf,
+					enum phl_phy_idx phy_idx, s32 xdbm);
+void halrf_tssi_set_efuse_to_de_8852b(struct rf_info *rf,
+						enum phl_phy_idx phy);
+void halrf_tssi_default_txagc_8852b(struct rf_info *rf,
+					enum phl_phy_idx phy, bool enable);
+
+void halrf_tssi_scan_ch_setting_8852b(struct rf_info *rf,
+	enum phl_phy_idx phy, enum rf_path path);
+
+void halrf_tssi_scan_ch_8852b(struct rf_info *rf, enum rf_path path);
+
+void halrf_tssi_backup_txagc_8852b(struct rf_info *rf, enum phl_phy_idx phy, bool enable);
+
+u32 halrf_tssi_get_final_8852b(struct rf_info *rf, enum rf_path path);
+
+
+void halrf_tssi_hw_tx_8852b(struct rf_info *rf,
+			enum phl_phy_idx phy, u8 path, u16 cnt, s16 dbm, u32 rate, u8 bw,
+			bool enable);
+
+void halrf_tssi_ant_open_8852b(struct rf_info *rf);
+
+void halrf_get_tssi_info_8852b(struct rf_info *rf,
+		char input[][16], u32 *_used, char *output, u32 *_out_len);
+
+void _halrf_tssi_hw_tx_8852b(struct rf_info *rf,
+			enum phl_phy_idx phy, u8 path, u16 cnt, u16 period, s16 dbm, u32 rate, u8 bw,
+			bool enable);
+#endif
+#endif	/*_HALRF_SET_PWR_TABLE_8852B_H_*/

3rd/devourer/hal/halrf/g6/vendor/halrf_8852b/halrf_txgapk_8852b.h

@@ -0,0 +1,60 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#ifndef __HALRF_TXGAPK_8852B_H__
+#define __HALRF_TXGAPK_8852B_H__
+
+#ifdef RF_8852B_SUPPORT
+
+#define TXGAPK_VER_8852B 0x0d
+
+/*--------------------------Define Parameters-------------------------------*/
+#define TXGAPK_RF_PATH_MAX_8852B 2
+
+#define TXGAPK_RF_REG_NUM_8852B 1
+
+#define TXGAPK_DEBUGMASK_8852B		0x100EE
+
+#define TXGAP_TB_ADDR_8852B			0x10033
+	
+#define TXGAP_TB_VAL_8852B			0x1003F
+/*---------------------------End Define Parameters----------------------------*/
+
+
+
+
+void halrf_txgapk_enable_8852b
+	(struct rf_info *rf, enum phl_phy_idx phy);
+
+void halrf_txgapk_write_table_default_8852b
+	(struct rf_info *rf, enum phl_phy_idx phy);
+
+void halrf_do_txgapk_8852b(struct rf_info *rf, enum phl_phy_idx phy);
+
+
+void halrf_txgapk_init_8852b(struct rf_info *rf);
+
+#endif /* RF_8852B_SUPPORT */
+#endif /*#ifndef __HALRF_TXGAPK_8852B_H__*/

3rd/devourer/hal/halrf/g6/vendor/halrf_8852b/halrf_version_rtl8852b.h

@@ -0,0 +1,26 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+/*RTL8852B RF Parameters*/
+#define	RF_RELEASE_VERSION_8852B	0x42

3rd/devourer/hal/halrf/g6/vendor/halrf_8852c/halrf_8852c.h

@@ -0,0 +1,75 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2020  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+#ifndef __HALRF_8852C_H__
+#define __HALRF_8852C_H__
+#ifdef RF_8852C_SUPPORT
+
+#define RXDCK_VER_8852C 0xe
+#define RCK_VER_8852C 0x3
+#define LCK_VER_8852C 0x2
+#define NCTL_FINAL_LINE_8852C 0x8000
+#define LCK_TH_8852C 8
+
+void halrf_lo_test_8852c(struct rf_info *rf, bool is_on, enum rf_path path);
+u8 halrf_kpath_8852c(struct rf_info *rf, enum phl_phy_idx phy_idx);
+void halrf_rx_dck_toggle_8852c(struct rf_info *rf, enum rf_path path);
+void halrf_set_rx_dck_8852c(struct rf_info *rf, enum phl_phy_idx phy, enum rf_path path, bool is_afe);
+void halrf_rx_dck_8852c(struct rf_info *rf, enum phl_phy_idx phy, bool is_afe);
+void halrf_thermal_rx_dck_8852c(struct rf_info *rf, enum phl_phy_idx phy, bool is_afe);
+void halrf_scan_rx_dck_8852c(struct rf_info *rf, enum phl_phy_idx phy, enum rfk_tri_type tri_type);
+void halrf_rx_dck_onoff_8852c(struct rf_info *rf, bool is_enable);
+void halrf_rck_8852c(struct rf_info *rf, enum rf_path path);
+void halrf_rxdck_track_8852c(struct rf_info *rf);
+void halrf_rf_direct_cntrl_8852c(struct rf_info *rf, enum rf_path path, bool is_bybb);
+void halrf_drf_direct_cntrl_8852c(struct rf_info *rf, enum rf_path path, bool is_bybb);
+void halrf_bf_config_rf_8852c(struct rf_info *rf);
+extern struct rfk_iqk_info rf_iqk_hwspec_8852c;
+void halrf_rxbb_bw_8852c(struct rf_info *rf, enum phl_phy_idx phy, enum channel_width bw);
+bool halrf_ctl_band_ch_bw_8852c(struct rf_info *rf, enum phl_phy_idx phy, enum band_type band, u8 central_ch, enum channel_width bw);
+void halrf_before_one_shot_enable_8852c(struct rf_info *rf);
+bool halrf_one_shot_nctl_done_check_8852c(struct rf_info *rf, enum rf_path path);
+bool halrf_do_one_shot_8852c(struct rf_info *rf, enum rf_path path, u32 nctl_addr, u32 mask, u32 process_id);
+
+bool halrf_rfk_reg_check_8852c(struct rf_info *rf);
+void halrf_rfk_reg_backup_8852c(struct rf_info *rf);
+bool halrf_rfk_reg_check_fail_8852c(struct rf_info *rf);
+void halrf_rfc_reg_backup_8852c(struct rf_info *rf);
+bool halrf_rfc_reg_check_fail_8852c(struct rf_info *rf);
+void halrf_rfk_reg_reload_8852c(struct rf_info *rf);
+void halrf_disconnect_notify_8852c(struct rf_info *rf, struct rtw_chan_def *chandef);
+bool halrf_check_mcc_ch_8852c(struct rf_info *rf, struct rtw_chan_def *chandef);
+void halrf_fw_ntfy_8852c(struct rf_info *rf, enum phl_phy_idx phy_idx);
+void halrf_lck_8852c(struct rf_info *rf);
+void halrf_lck_tracking_8852c(struct rf_info *rf);
+void halrf_quick_checkrf_8852c(struct rf_info *rf);
+void halrf_adc_fifo_rst_8852c(struct rf_info *rf, enum phl_phy_idx phy_idx, u8 path);
+
+// FCS
+void halrf_fcs_backup_8852c(struct rf_info *rf, u32 chl_index);
+void halrf_fcs_drv_reload_8852c(struct rf_info *rf, u32 chl_index);
+void halrf_fcs_fw_reload_8852c(struct rf_info *rf, u32 chl_index);
+
+#endif
+#endif /*  __HALRF_8852C_H__ */

3rd/devourer/hal/halrf/g6/vendor/halrf_8852c/halrf_8852c_api.c

@@ -0,0 +1,902 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2020  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+#include "../halrf_precomp.h"
+#ifdef RF_8852C_SUPPORT
+
+u8 halrf_get_thermal_8852c(struct rf_info *rf, enum rf_path rf_path)
+{
+	u8 thermal = 0;
+
+	halrf_wrf(rf, rf_path, 0x42, BIT(19), 0x1);
+	halrf_wrf(rf, rf_path, 0x42, BIT(19), 0x0);
+	halrf_wrf(rf, rf_path, 0x42, BIT(19), 0x1);
+
+	halrf_delay_us(rf, 200);
+
+
+	thermal = (u8)halrf_rrf(rf, rf_path, 0x42, 0x0007e);
+	return thermal;
+}
+
+void halrf_set_syn01_8852c(struct rf_info *rf, bool dbcc_en)
+{
+	if (dbcc_en == 1) {
+		/*SYN0 on + SYN1 on*/
+		halrf_wrf(rf, RF_PATH_A, 0xA0, (BIT(3) | BIT(2)), 0x3);
+		halrf_wrf(rf, RF_PATH_B, 0xA0, (BIT(3) | BIT(2)), 0x3);
+		/*halrf_by_rate_dpd_8852c(rf, HW_PHY_1);*/
+	} else if (dbcc_en == 0) {
+		/*SYN0 on + SYN1 off*/
+		halrf_wrf(rf, RF_PATH_A, 0xA0, (BIT(3) | BIT(2)), 0x3);
+		halrf_wrf(rf, RF_PATH_B, 0xA0, (BIT(3) | BIT(2)), 0x0);
+	}
+}
+
+u32 halrf_mac_get_pwr_reg_8852c(struct rf_info *rf, enum phl_phy_idx phy,
+	u32 addr, u32 mask)
+{
+	struct rtw_hal_com_t *hal = rf->hal_com;
+	u32 result, ori_val, bit_shift, reg_val;
+
+	result = rtw_hal_mac_get_pwr_reg(hal, phy, addr, &ori_val);
+	if (result)
+		RF_WARNING("=======>%s Get MAC(0x%x) fail, error code=%d\n",
+			__func__, addr, result);
+	else
+		RF_DBG(rf, DBG_RF_POWER, "Get MAC(0x%x) ok!!! 0x%08x\n",
+			addr, ori_val);
+
+	bit_shift = halrf_cal_bit_shift(mask);
+	reg_val = (ori_val & mask) >> bit_shift;
+
+	return reg_val;
+}
+
+u32 halrf_mac_set_pwr_reg_8852c(struct rf_info *rf, enum phl_phy_idx phy,
+	u32 addr, u32 mask, u32 val)
+{
+	struct rtw_hal_com_t *hal = rf->hal_com;
+	u32 result;
+
+	result = rtw_hal_mac_write_msk_pwr_reg(hal, phy, addr, mask, val);
+	if (result) {
+		RF_WARNING("=======>%s Set MAC(0x%x[0x%08x]) fail, error code=%d\n",
+			__func__, addr, mask, result);
+		return false;
+	} else
+		RF_DBG(rf, DBG_RF_POWER, "Set MAC(0x%x[0x%08x])=0x%08x ok!!! \n",
+			addr, mask, val);
+
+	return result;
+}
+
+void halrf_wlan_tx_power_control_8852c(struct rf_info *rf,
+	enum phl_phy_idx phy, enum phl_pwr_ctrl pwr_ctrl_idx,
+	u32 tx_power_val, bool enable)
+{
+	u32 phy_tmp;
+
+	RF_DBG(rf, DBG_RF_POWER, "[Pwr Ctrl] ==>%s phy=%d pwr_ctrl_idx=%d tx_power_val=%d enable=%d\n",
+		__func__, phy, pwr_ctrl_idx, tx_power_val, enable);
+
+	if (rf->hal_com->dbcc_en)
+		phy_tmp = phy;
+	else
+		phy_tmp = HW_PHY_0;
+
+	if (enable == false) {
+		if (pwr_ctrl_idx == ALL_TIME_CTRL) {
+			/*all-time control Disable*/
+			halrf_mac_set_pwr_reg_8852c(rf, phy_tmp, 0xd200, 0x3ff, 0x0);
+		} else if (pwr_ctrl_idx == GNT_TIME_CTRL) {
+			/*GNT_BT control Disable*/
+			halrf_mac_set_pwr_reg_8852c(rf, phy_tmp, 0xd220, BIT(1), 0x0);
+			halrf_mac_set_pwr_reg_8852c(rf, phy_tmp, 0xd220, 0xff8, 0x0);
+		}
+	} else {
+		if (pwr_ctrl_idx == ALL_TIME_CTRL) {
+			halrf_mac_set_pwr_reg_8852c(rf, phy_tmp, 0xd200, 0x3ff,
+				((tx_power_val & 0x1ff) | BIT(9)));
+		} else if (pwr_ctrl_idx == GNT_TIME_CTRL) {
+			halrf_mac_set_pwr_reg_8852c(rf, phy_tmp, 0xd220, BIT(1), 0x1);
+			halrf_mac_set_pwr_reg_8852c(rf, phy_tmp, 0xd220, 0xff8, tx_power_val & 0x1ff);
+		} else {
+			RF_WARNING("[Pwr Ctrl] ==>%s (pwr_ctrl_idx = %d) don't exist !!!\n",
+				__func__, pwr_ctrl_idx);
+		}
+	}
+}
+
+bool halrf_wl_tx_power_control_8852c(struct rf_info *rf, u32 tx_power_val)
+{
+	struct halrf_pwr_info *pwr = &rf->pwr_info;
+	u32 result; 
+	s32 tmp_pwr;
+	u8 phy = 0;
+	u32 all_time_control = 0;
+	u32 gnt_bt_control = 0;
+
+	RF_DBG(rf, DBG_RF_POWER, "=======>%s\n", __func__);
+
+	all_time_control = tx_power_val & 0xffff;
+	gnt_bt_control = (tx_power_val & 0xffff0000) >> 16;
+
+	RF_DBG(rf, DBG_RF_POWER, "[Pwr Ctrl]tx_power_val=0x%x   all_time_control=0x%x   gnt_bt_control=0x%x\n",
+		tx_power_val, all_time_control, gnt_bt_control);
+
+	if (all_time_control == 0xffff) {
+		/*Coex Disable*/
+		pwr->coex_pwr_ctl_enable = false;
+		pwr->coex_pwr = 0;
+		RF_DBG(rf, DBG_RF_POWER, "[Pwr Ctrl] Coex Disable all_time_control=0xffff!!!\n");
+	} else if (all_time_control == 0xeeee) {
+		/*DPK Disable*/
+		pwr->dpk_pwr_ctl_enable = false;
+		pwr->dpk_pwr = 0;
+		RF_DBG(rf, DBG_RF_POWER, "[Pwr Ctrl] DPK Disable all_time_control=0xeeee\n");
+	} else {
+		if (all_time_control & BIT(15)) {
+			/*DPK*/
+			pwr->dpk_pwr_ctl_enable = true;
+			pwr->dpk_pwr = all_time_control & 0x1ff;
+
+			RF_DBG(rf, DBG_RF_POWER, "[Pwr Ctrl] DPK Enable Set pwr->dpk_pwr = %d\n",
+				pwr->dpk_pwr);
+		} else {
+			/*Coex*/
+			pwr->coex_pwr_ctl_enable = true;
+			pwr->coex_pwr = all_time_control & 0x1ff;
+
+			RF_DBG(rf, DBG_RF_POWER, "[Pwr Ctrl] Coex Enable Set pwr->coex_pwr = %d\n",
+				pwr->coex_pwr);
+		}
+	}
+
+	if (pwr->coex_pwr_ctl_enable == true && pwr->dpk_pwr_ctl_enable == false) {
+		tmp_pwr = pwr->coex_pwr;
+
+		RF_DBG(rf, DBG_RF_POWER, "[Pwr Ctrl] coex_pwr_ctl_enable=true dpk_pwr_ctl_enable=false tmp_pwr=%d\n",
+			tmp_pwr);
+	} else if (pwr->coex_pwr_ctl_enable == false && pwr->dpk_pwr_ctl_enable == true) {
+		tmp_pwr = pwr->dpk_pwr;
+
+		RF_DBG(rf, DBG_RF_POWER, "[Pwr Ctrl] coex_pwr_ctl_enable=false dpk_pwr_ctl_enable=true tmp_pwr=%d\n",
+			tmp_pwr);
+	} else if (pwr->coex_pwr_ctl_enable == true && pwr->dpk_pwr_ctl_enable == true) {
+		if (pwr->coex_pwr > pwr->dpk_pwr)
+			tmp_pwr = pwr->dpk_pwr;
+		else
+			tmp_pwr = pwr->coex_pwr;
+
+		RF_DBG(rf, DBG_RF_POWER, "[Pwr Ctrl] coex_pwr_ctl_enable=true dpk_pwr_ctl_enable=true tmp_pwr=%d\n",
+			tmp_pwr);
+	} else
+		tmp_pwr = 0;
+
+	if (pwr->coex_pwr_ctl_enable == false && pwr->dpk_pwr_ctl_enable == false) {
+		/*all-time control Disable*/
+		result = halrf_mac_set_pwr_reg_8852c(rf, phy, 0xd200, 0x3ff, 0x0);
+
+		if (result) {
+			RF_WARNING("=======>%s Set MAC(0xd200) fail, error code=%d\n",
+				__func__, result);
+			return false;
+		} else {
+			RF_DBG(rf, DBG_RF_POWER, "Set MAC(0xd200) ok!!!\n");
+			rf->is_coex = false;
+		}
+	} else {
+		/*all-time control*/
+		result = halrf_mac_set_pwr_reg_8852c(rf, phy, 0xd200, 0x3ff, ((tmp_pwr & 0x1ff) | BIT(9)));
+		if (result) {
+			RF_WARNING("=======>%s Set MAC(0xd200) fail, error code=%d\n",
+				__func__, result);
+			return false;
+		} else {
+			RF_DBG(rf, DBG_RF_POWER, "Set MAC(0xd200) ok!!!\n");
+			rf->is_coex = true;
+		}
+	}
+
+	if (gnt_bt_control == 0xffff) {
+		/*GNT_BT control*/
+
+		RF_DBG(rf, DBG_RF_POWER, "=======>%s   gnt_bt_control = 0x%x\n",
+			__func__, gnt_bt_control);
+
+		result = halrf_mac_set_pwr_reg_8852c(rf, phy, 0xd220, BIT(1), 0x0);
+		result = halrf_mac_set_pwr_reg_8852c(rf, phy, 0xd220, 0xff8, 0x0);
+		if (result) {
+			RF_WARNING("=======>%s Set MAC(0xd220) fail, error code=%d\n",
+				__func__, result);
+			return false;
+		} else {
+			RF_DBG(rf, DBG_RF_POWER, "Set MAC(0xd220) ok!!!\n");
+			rf->is_coex = false;
+		}
+	} else {
+		/*GNT_BT control*/
+
+		RF_DBG(rf, DBG_RF_POWER, "=======>%s   gnt_bt_control = 0x%x\n",
+			__func__, gnt_bt_control);
+
+		result = halrf_mac_set_pwr_reg_8852c(rf, phy, 0xd220, BIT(1), 0x1);
+		result = halrf_mac_set_pwr_reg_8852c(rf, phy, 0xd220, 0xff8, gnt_bt_control & 0x1ff);
+		if (result) {
+			RF_WARNING("=======>%s Set MAC(0xd220) fail, error code=%d\n",
+				__func__, result);
+			return false;
+		} else {
+			RF_DBG(rf, DBG_RF_POWER, "Set MAC(0xd220) ok!!!\n");
+			rf->is_coex = true;
+		}
+	}
+
+	return true;
+}
+
+#ifdef HALRF_THERMAL_PROTECT_SUPPORT
+s8 halrf_get_ther_protected_threshold_8852c(struct rf_info *rf)
+{
+	u8 thermal_a, thermal_b, tmp;
+	u8 therml_max = THER_PROTECTED_THRESHOLD_AX;
+	s8 thermal_trim_a, thermal_trim_b;
+	s8 abs_thermal_trim_a, abs_thermal_trim_b;
+
+	thermal_a = rf->cur_ther_s0;
+	thermal_b = rf->cur_ther_s1;
+
+	if (rf->is_set_thermal) {
+		thermal_a = rf->thermal_test[RF_PATH_A];
+		thermal_b = rf->thermal_test[RF_PATH_B];
+		RF_DBG(rf, DBG_RF_RFK, "=======>%s   Use Fix thermal, thermal S0/S1 = 0x%x / 0x%x\n",
+			__func__, thermal_a, thermal_b);
+	}
+
+#ifdef HALRF_THERMAL_PROTECT_SUPPORT
+	if (rf->phl_com->dev_sw_cap.thermal_threshold != 0xff)
+		therml_max = rf->phl_com->dev_sw_cap.thermal_threshold;
+#endif
+
+	RF_DBG(rf, DBG_RF_RFK, "=======>%s   thermal S0/S1 = 0x%x / 0x%x, thermal_protected_threshold=0x%x\n",
+		__func__, thermal_a, thermal_b, therml_max);
+
+	thermal_trim_a = halrf_get_thremal_trim_8852c(rf, RF_PATH_A);
+	thermal_trim_b = halrf_get_thremal_trim_8852c(rf, RF_PATH_B);
+
+	if (thermal_trim_a < 0)
+		abs_thermal_trim_a = thermal_trim_a * -1;	/*absolute value*/
+	else
+		abs_thermal_trim_a = thermal_trim_a;
+
+	if (thermal_trim_b < 0)
+		abs_thermal_trim_b = thermal_trim_b * -1;	/*absolute value*/
+	else
+		abs_thermal_trim_b = thermal_trim_b;
+
+	RF_DBG(rf, DBG_RF_RFK, "thermal_trim S0/S1 = 0x%x / 0x%x, abs_thermal_trim S0/S1 = 0x%x / 0x%x\n",
+		thermal_trim_a, thermal_trim_b, abs_thermal_trim_a, abs_thermal_trim_b);
+
+	if (abs_thermal_trim_a > abs_thermal_trim_b) {
+		RF_DBG(rf, DBG_RF_RFK, "abs_thermal_trim_a > abs_thermal_trim_b\n");
+		if (thermal_trim_b < -7 || thermal_trim_b > 7) {
+			tmp = thermal_b + thermal_trim_b;
+			RF_DBG(rf, DBG_RF_RFK, "Ther_trim > +7,-7, tmp(%d)(0x%x) = Use S1 thermal(%d) + ther_tirm(%d)\n",
+				tmp, tmp, thermal_b, thermal_trim_b);
+		} else {
+			tmp = thermal_b;
+			RF_DBG(rf, DBG_RF_RFK, "tmp(%d)(0x%x) = Use S1 thermal(%d)\n",
+				tmp, tmp, thermal_b);
+		}
+	} else {
+		RF_DBG(rf, DBG_RF_RFK, "abs_thermal_trim_a <= abs_thermal_trim_b\n");
+		if (thermal_trim_a < -7 || thermal_trim_a > 7) {
+			tmp = thermal_a + thermal_trim_a;
+			RF_DBG(rf, DBG_RF_RFK, "Ther_trim > +7,-7, tmp(%d)(0x%x) = Use S0 thermal(%d) + ther_tirm(%d)\n",
+				tmp, tmp, thermal_a, thermal_trim_a);
+		} else {
+			tmp = thermal_a;
+			RF_DBG(rf, DBG_RF_RFK, "tmp(%d)(0x%x) = Use S0 thermal(%d)\n",
+				tmp, tmp, thermal_a);
+		}
+	}
+
+	if (tmp > therml_max) {
+		RF_DBG(rf, DBG_RF_RFK, "tmp(0x%x) > thermal_protect(0x%x), Return -1. Tx duty reduce\n", tmp, therml_max);
+		return -1;	/*Tx duty reduce*/
+	} else if (tmp < therml_max - THER_PROTECTED_RANGE_AX) {
+		RF_DBG(rf, DBG_RF_RFK, "tmp(0x%x) < thermal_protect(0x%x) - %d, Return 1. Tx duty up\n", tmp, therml_max, THER_PROTECTED_RANGE_AX);
+		return 1;	/*Tx duty up*/
+	} else {
+		RF_DBG(rf, DBG_RF_RFK, "tmp(0x%x), thermal_protect(0x%x), Return 0. Tx duty the same\n", tmp, therml_max);
+		return 0;	/*Tx duty the same*/
+	}
+}
+#endif	/*HALRF_THERMAL_PROTECT_SUPPORT*/
+
+s8 halrf_xtal_tracking_offset_8852c(struct rf_info *rf,
+					enum phl_phy_idx phy)
+{
+	struct halrf_xtal_info *xtal_trk = &rf->xtal_track;
+	u8 thermal_a = 0xff, thermal_b = 0xff;
+	u8 tmp_a, tmp_b, tmp;
+	s8 xtal_ofst = 0;
+
+	RF_DBG(rf, DBG_RF_XTAL_TRACK, "======>%s   phy=%d\n",
+		__func__, phy);
+
+	tmp_a = rf->cur_ther_s0;
+	tmp_b = rf->cur_ther_s1;
+	halrf_efuse_get_info(rf, EFUSE_INFO_RF_THERMAL_A, &thermal_a, 1);
+	halrf_efuse_get_info(rf, EFUSE_INFO_RF_THERMAL_B, &thermal_b, 1);
+
+	if (thermal_a == 0xff || thermal_b == 0xff ||
+		thermal_a == 0x0 || thermal_b == 0x0) {
+		RF_DBG(rf, DBG_RF_XTAL_TRACK, "======>%s PG ThermalA=%d ThermalB=%d\n",
+			__func__, thermal_a, thermal_b);
+		return 0;
+	}
+
+	if (tmp_a > tmp_b) {
+		if (tmp_a > thermal_a) {
+			tmp = tmp_a - thermal_a;
+			if (tmp >= DELTA_SWINGIDX_SIZE)
+				tmp = DELTA_SWINGIDX_SIZE - 1;
+			xtal_ofst = xtal_trk->delta_swing_xtal_table_idx_p[tmp];
+		} else {
+			tmp = thermal_a - tmp_a;
+			if (tmp >= DELTA_SWINGIDX_SIZE)
+				tmp = DELTA_SWINGIDX_SIZE - 1;
+			xtal_ofst = xtal_trk->delta_swing_xtal_table_idx_n[tmp];
+		}
+	} else {
+		if (tmp_b > thermal_b) {
+			tmp = tmp_b - thermal_b;
+			if (tmp >= DELTA_SWINGIDX_SIZE)
+				tmp = DELTA_SWINGIDX_SIZE - 1;
+			xtal_ofst = xtal_trk->delta_swing_xtal_table_idx_p[tmp];
+		} else {
+			tmp = thermal_b - tmp_b;
+			if (tmp >= DELTA_SWINGIDX_SIZE)
+				tmp = DELTA_SWINGIDX_SIZE - 1;
+			xtal_ofst = xtal_trk->delta_swing_xtal_table_idx_n[tmp];
+		}
+	}
+
+	RF_DBG(rf, DBG_RF_XTAL_TRACK, "PG ThermalA=%d   ThermalA=%d\n",
+		thermal_a, tmp_a);
+
+	RF_DBG(rf, DBG_RF_XTAL_TRACK, "PG ThermalB=%d   ThermalB=%d\n",
+		thermal_b, tmp_b);
+
+	RF_DBG(rf, DBG_RF_XTAL_TRACK, "xtal_ofst[%d]=%d\n",
+		tmp, xtal_ofst);
+
+	return xtal_ofst;
+}
+void halrf_syn1_onoff_8852c(struct rf_info *rf, enum phl_phy_idx phy, u8 path, bool syn1_turn_on)
+{
+	if(path != RF_PATH_B)
+		return;
+	
+	if (syn1_turn_on) {
+		//Re-write LUT_SYNMODE_S1 to turn on SYN1 when exit 2x2 mode (DBCC or 1x1)
+		halrf_wrf(rf, RF_PATH_B, 0xED, MASKRF, 0x00010);      //LUT write enable ED[4]=1
+
+		halrf_wrf(rf, RF_PATH_B, 0x33, MASKRF, 0x00001);     //write register WA 33[2:0]=001
+		halrf_wrf(rf, RF_PATH_B, 0x3F, MASKRF, 0x0000E);     //write register WD 3F[3:0]=1010: 3F[2]=POW_SYN=1
+		halrf_wrf(rf, RF_PATH_B, 0x33, MASKRF, 0x00002);     //write register WA 33[2:0]=010
+		halrf_wrf(rf, RF_PATH_B, 0x3F, MASKRF, 0x0000E);     //write register WD 3F[3:0]=1010: 3F[2]=POW_SYN=1
+		halrf_wrf(rf, RF_PATH_B, 0x33, MASKRF, 0x00003);     //write register WA 33[2:0]=011
+		halrf_wrf(rf, RF_PATH_B, 0x3F, MASKRF, 0x0000E);     //write register WD 3F[3:0]=1010: 3F[2]=POW_SYN=1
+		halrf_wrf(rf, RF_PATH_B, 0x33, MASKRF, 0x00005);     //write register WA 33[2:0]=101
+		halrf_wrf(rf, RF_PATH_B, 0x3F, MASKRF, 0x0000D);     //write register WD 3F[3:0]=1010: 3F[2]=POW_SYN=1
+		halrf_wrf(rf, RF_PATH_B, 0x33, MASKRF, 0x00006);     //write register WA 33[2:0]=110
+		halrf_wrf(rf, RF_PATH_B, 0x3F, MASKRF, 0x0000D);     //write register WD 3F[3:0]=1010: 3F[2]=POW_SYN=1
+		halrf_wrf(rf, RF_PATH_B, 0x33, MASKRF, 0x00007);     //write register WA 33[2:0]=111
+		halrf_wrf(rf, RF_PATH_B, 0x3F, MASKRF, 0x0000D);     //write register WD 3F[3:0]=1010: 3F[2]=POW_SYN=1
+
+		halrf_wrf(rf, RF_PATH_B, 0xED, MASKRF, 0x00000);      //LUT write disable ED[4]=0
+	} else {
+		//Re-write LUT_SYNMODE_S1 to turn off SYN1 at 2x2 mode
+		//need to go back to default LUT_SYNMODE_S1 table if it is not 2x2 mode
+		halrf_wrf(rf, RF_PATH_B, 0xED, MASKRF, 0x00010);	    //LUT write enable ED[4]=1
+		
+		halrf_wrf(rf, RF_PATH_B, 0x33, MASKRF, 0x00001);	   //write register WA 33[2:0]=001
+		halrf_wrf(rf, RF_PATH_B, 0x3F, MASKRF, 0x0000A);	   //write register WD 3F[3:0]=1010: 3F[2]=POW_SYN=0
+		halrf_wrf(rf, RF_PATH_B, 0x33, MASKRF, 0x00002);	   //write register WA 33[2:0]=010
+		halrf_wrf(rf, RF_PATH_B, 0x3F, MASKRF, 0x0000A);	   //write register WD 3F[3:0]=1010: 3F[2]=POW_SYN=0
+		halrf_wrf(rf, RF_PATH_B, 0x33, MASKRF, 0x00003);	   //write register WA 33[2:0]=011
+		halrf_wrf(rf, RF_PATH_B, 0x3F, MASKRF, 0x0000A);	   //write register WD 3F[3:0]=1010: 3F[2]=POW_SYN=0
+		halrf_wrf(rf, RF_PATH_B, 0x33, MASKRF, 0x00005);	   //write register WA 33[2:0]=101
+		halrf_wrf(rf, RF_PATH_B, 0x3F, MASKRF, 0x0000A);	   //write register WD 3F[3:0]=1010: 3F[2]=POW_SYN=0
+		halrf_wrf(rf, RF_PATH_B, 0x33, MASKRF, 0x00006);	   //write register WA 33[2:0]=110
+		halrf_wrf(rf, RF_PATH_B, 0x3F, MASKRF, 0x0000A);	   //write register WD 3F[3:0]=1010: 3F[2]=POW_SYN=0
+		halrf_wrf(rf, RF_PATH_B, 0x33, MASKRF, 0x00007);	   //write register WA 33[2:0]=111
+		halrf_wrf(rf, RF_PATH_B, 0x3F, MASKRF, 0x0000A);	   //write register WD 3F[3:0]=1010: 3F[2]=POW_SYN=0
+		
+		halrf_wrf(rf, RF_PATH_B, 0xED, MASKRF, 0x00000);	    //LUT write disable ED[4]=0
+	}
+	return;
+}
+
+void halrf_txck_force_8852c(struct rf_info *rf, enum rf_path path, bool force, enum dac_ck ck)
+{
+	halrf_wreg(rf, 0x12a0 | (path <<13), BIT(15), 0x0);
+
+	if (!force)
+		return;
+
+	halrf_wreg(rf, 0x12a0 | (path <<13), 0x7000, ck);
+	halrf_wreg(rf, 0x12a0 | (path <<13), BIT(15), 0x1);
+}
+
+void halrf_rxck_force_8852c(struct rf_info *rf, enum rf_path path, bool force, enum adc_ck ck)
+{
+	u32 bw = 0;
+
+	halrf_wreg(rf, 0x12a0 | (path <<13), BIT(19), 0x0);
+
+	if (!force)
+		return;
+
+	halrf_wreg(rf, 0x12a0 | (path <<13), 0x70000, ck);
+	halrf_wreg(rf, 0x12a0 | (path <<13), BIT(19), 0x1);
+	switch (ck) {
+	case ADC_480M:
+		bw = CHANNEL_WIDTH_40;
+		break;
+	case ADC_960M:
+		bw = CHANNEL_WIDTH_80;
+		break;
+	case ADC_1920M:
+		bw = CHANNEL_WIDTH_160;
+		break;
+	default:
+		RF_WARNING("%s==>Invalid ck", __func__);
+		break;
+	}
+	halrf_bb_adc_cfg(rf, bw, path, HW_PHY_0);
+}
+
+void halrf_set_gpio_8852c(struct rf_info *rf, enum phl_phy_idx phy)
+{
+	u32 band = rf->hal_com->band[phy].cur_chandef.band;
+	u8 rfe_type = rf->phl_com->dev_cap.rfe_type;
+
+	RF_DBG(rf, DBG_RF_INIT, "===>%s   rfe_type=%d   phy=%d\n",
+		__func__, rfe_type, phy);
+
+	if (rfe_type == 51 || rfe_type == 52) {
+		/*Set BB GPIO Setting*/
+		/*PathA=0x1*/
+		halrf_gpio_setting(rf, 10, 0x1, true, HALRF_TRSW_RFM);
+		halrf_gpio_setting(rf, 7, 0x1, false, HALRF_LNAON_RFM);
+		halrf_gpio_setting(rf, 6, 0x1, false, HALRF_PAPE_RFM);
+		/*PathB=0x2*/
+		halrf_gpio_setting(rf, 1, 0x2, true, HALRF_TRSW_RFM);
+		halrf_gpio_setting(rf, 2, 0x2, false, HALRF_LNAON_RFM);
+		halrf_gpio_setting(rf, 3, 0x2, false, HALRF_PAPE_RFM);
+
+		/*Set MAC GPIO Setting*/
+		halrf_set_gpio_func(rf, RTW_MAC_GPIO_WL_RFE_CTRL, 1);
+		halrf_set_gpio_func(rf, RTW_MAC_GPIO_WL_RFE_CTRL, 2);
+		halrf_set_gpio_func(rf, RTW_MAC_GPIO_WL_RFE_CTRL, 3);
+		halrf_set_gpio_func(rf, RTW_MAC_GPIO_WL_RFE_CTRL, 6);
+		halrf_set_gpio_func(rf, RTW_MAC_GPIO_WL_RFE_CTRL, 7);
+		halrf_set_gpio_func(rf, RTW_MAC_GPIO_WL_RFE_CTRL, 10);
+	} 
+
+	if (rfe_type == 53 || rfe_type == 54 || rfe_type == 63 || rfe_type == 64) {
+		/*Set BB GPIO Setting*/
+		/*PathA=0x1*/
+		halrf_gpio_setting(rf, 10, 0x1, true, HALRF_TRSW_RFM);
+		halrf_gpio_setting(rf, 7, 0x1, true, HALRF_LNAON_RFM);
+		halrf_gpio_setting(rf, 6, 0x1, false, HALRF_PAPE_RFM);
+		/*PathB=0x2*/
+		halrf_gpio_setting(rf, 1, 0x2, true, HALRF_TRSW_RFM);
+		halrf_gpio_setting(rf, 2, 0x2, true, HALRF_LNAON_RFM);
+		halrf_gpio_setting(rf, 3, 0x2, false, HALRF_PAPE_RFM);
+		
+		/*Set MAC GPIO Setting*/
+		halrf_set_gpio_func(rf, RTW_MAC_GPIO_WL_RFE_CTRL, 1);
+		halrf_set_gpio_func(rf, RTW_MAC_GPIO_WL_RFE_CTRL, 2);
+		halrf_set_gpio_func(rf, RTW_MAC_GPIO_WL_RFE_CTRL, 3);
+		halrf_set_gpio_func(rf, RTW_MAC_GPIO_WL_RFE_CTRL, 6);
+		halrf_set_gpio_func(rf, RTW_MAC_GPIO_WL_RFE_CTRL, 7);
+		halrf_set_gpio_func(rf, RTW_MAC_GPIO_WL_RFE_CTRL, 10);
+	}
+
+	if (rfe_type == 21 || rfe_type == 22) {
+		if (band == BAND_ON_24G) {
+			/*Set BB GPIO Setting*/
+			/*PathA=0x1*/
+			halrf_gpio_setting(rf, 2, 0x1, false, HALRF_ZERO);
+			halrf_gpio_setting(rf, 1, 0x1, false, HALRF_ZERO);
+			halrf_gpio_setting(rf, 0, 0x1, false, HALRF_ZERO);
+			/*PathB=0x2*/
+			halrf_gpio_setting(rf, 5, 0x2, false, HALRF_ZERO);
+			halrf_gpio_setting(rf, 4, 0x2, false, HALRF_ZERO);
+			halrf_gpio_setting(rf, 3, 0x2, false, HALRF_ZERO);
+		} else {
+			/*Set BB GPIO Setting*/
+			/*PathA=0x1*/
+			halrf_gpio_setting(rf, 2, 0x1, true, HALRF_TRSW_RFM);
+			halrf_gpio_setting(rf, 1, 0x1, false, HALRF_LNAON_RFM);
+			halrf_gpio_setting(rf, 0, 0x1, false, HALRF_PAPE_RFM);
+			/*PathB=0x2*/
+			halrf_gpio_setting(rf, 5, 0x2, true, HALRF_TRSW_RFM);
+			halrf_gpio_setting(rf, 4, 0x2, false, HALRF_LNAON_RFM);
+			halrf_gpio_setting(rf, 3, 0x2, false, HALRF_PAPE_RFM);
+		}
+
+		/*Set MAC GPIO Setting*/
+		halrf_set_gpio_func(rf, RTW_MAC_GPIO_WL_RFE_CTRL, 0);
+		halrf_set_gpio_func(rf, RTW_MAC_GPIO_WL_RFE_CTRL, 1);
+		halrf_set_gpio_func(rf, RTW_MAC_GPIO_WL_RFE_CTRL, 2);
+		halrf_set_gpio_func(rf, RTW_MAC_GPIO_WL_RFE_CTRL, 3);
+		halrf_set_gpio_func(rf, RTW_MAC_GPIO_WL_RFE_CTRL, 4);
+		halrf_set_gpio_func(rf, RTW_MAC_GPIO_WL_RFE_CTRL, 5);
+	}
+}
+
+void halrf_set_gpio_by_ch_8852c(struct rf_info *rf, enum phl_phy_idx phy, enum band_type band)
+{
+	u8 rfe_type = rf->phl_com->dev_cap.rfe_type;
+
+	RF_DBG(rf, DBG_RF_RFK, "===>%s   rfe_type=%d   phy=%d   band=%d\n",
+		__func__, rfe_type, phy, band);
+
+	if (rfe_type == 21 || rfe_type == 22) {
+		if (rf->hal_com->dbcc_en) {
+			if (band == BAND_ON_24G) {
+				/*Set BB GPIO Setting*/
+				/*PathA=0x1*/
+				if (phy == HW_PHY_0) {
+					halrf_gpio_setting(rf, 2, 0x1, false, HALRF_ZERO);
+					halrf_gpio_setting(rf, 1, 0x1, false, HALRF_ZERO);
+					halrf_gpio_setting(rf, 0, 0x1, false, HALRF_ZERO);
+				} else {	/*PathB=0x2*/
+					halrf_gpio_setting(rf, 5, 0x2, false, HALRF_ZERO);
+					halrf_gpio_setting(rf, 4, 0x2, false, HALRF_ZERO);
+					halrf_gpio_setting(rf, 3, 0x2, false, HALRF_ZERO);
+				}
+			} else {
+				/*Set BB GPIO Setting*/
+				/*PathA=0x1*/
+				if (phy == HW_PHY_0) {
+					halrf_gpio_setting(rf, 2, 0x1, true, HALRF_TRSW_RFM);
+					halrf_gpio_setting(rf, 1, 0x1, false, HALRF_LNAON_RFM);
+					halrf_gpio_setting(rf, 0, 0x1, false, HALRF_PAPE_RFM);
+				} else {	/*PathB=0x2*/
+					halrf_gpio_setting(rf, 5, 0x2, true, HALRF_TRSW_RFM);
+					halrf_gpio_setting(rf, 4, 0x2, false, HALRF_LNAON_RFM);
+					halrf_gpio_setting(rf, 3, 0x2, false, HALRF_PAPE_RFM);
+				}
+			}
+		} else {
+			if (band == BAND_ON_24G) {
+				/*Set BB GPIO Setting*/
+				/*PathA=0x1*/
+				halrf_gpio_setting(rf, 2, 0x1, false, HALRF_ZERO);
+				halrf_gpio_setting(rf, 1, 0x1, false, HALRF_ZERO);
+				halrf_gpio_setting(rf, 0, 0x1, false, HALRF_ZERO);
+				/*PathB=0x2*/
+				halrf_gpio_setting(rf, 5, 0x2, false, HALRF_ZERO);
+				halrf_gpio_setting(rf, 4, 0x2, false, HALRF_ZERO);
+				halrf_gpio_setting(rf, 3, 0x2, false, HALRF_ZERO);
+			} else {
+				/*Set BB GPIO Setting*/
+				/*PathA=0x1*/
+				halrf_gpio_setting(rf, 2, 0x1, true, HALRF_TRSW_RFM);
+				halrf_gpio_setting(rf, 1, 0x1, false, HALRF_LNAON_RFM);
+				halrf_gpio_setting(rf, 0, 0x1, false, HALRF_PAPE_RFM);
+				/*PathB=0x2*/
+				halrf_gpio_setting(rf, 5, 0x2, true, HALRF_TRSW_RFM);
+				halrf_gpio_setting(rf, 4, 0x2, false, HALRF_LNAON_RFM);
+				halrf_gpio_setting(rf, 3, 0x2, false, HALRF_PAPE_RFM);
+			}
+		}
+	}
+}
+
+u32 bkup_kip_reg_8852c[] = {0x813c, 0x8124, 0x8120, 0xc0d4, 0xc0d8};
+u32 bkup_bb_reg_8852c[] = {0x2344};
+u32 bkup_rf_reg_8852c[] = {0x5, 0x10005, 0xdf};
+
+u32 bkup_kip_val_8852c[RF_PATH_MAX_NUM][RF_BACKUP_KIP_REG_MAX_NUM] = {{0x0}};
+u32 bkup_bb_val_8852c[RF_BACKUP_BB_REG_MAX_NUM] = {0x0};
+u32 bkup_rf_val_8852c[RF_PATH_MAX_NUM][RF_BACKUP_RF_REG_MAX_NUM] = {{0x0}};
+
+void do_bkup_kip_8852c(struct rf_info *rf, u8 path)
+{
+	u32 i;
+	u32 num = ARRAY_SIZE(bkup_kip_reg_8852c);
+
+	for (i = 0; i < num; i++) {
+		if (i >= RF_BACKUP_KIP_REG_MAX_NUM) {
+			RF_DBG(rf, DBG_RF_RFK,
+			       "[RFK] %s backup size not enough\n", __func__);
+			break;
+		}
+		bkup_kip_val_8852c[path][i] = halrf_rreg(rf, bkup_kip_reg_8852c[i] + (path << 8), MASKDWORD);
+		
+		RF_DBG(rf, DBG_RF_RFK, "[RFK] Backup KIP(S%d) 0x%x = %x\n", path, bkup_kip_reg_8852c[i] + (path << 8), bkup_kip_val_8852c[path][i]);
+	}
+}
+
+void do_bkup_bb_8852c(struct rf_info *rf)
+{
+	u32 i;
+	u32 num = ARRAY_SIZE(bkup_bb_reg_8852c);
+
+	for (i = 0; i < num; i++) {
+		if (i >= RF_BACKUP_BB_REG_MAX_NUM) {
+			RF_DBG(rf, DBG_RF_RFK,
+			       "[RFK] %s backup size not enough\n", __func__);
+			break;
+		}
+		bkup_bb_val_8852c[i] =
+			halrf_rreg(rf, bkup_bb_reg_8852c[i], MASKDWORD);
+
+		RF_DBG(rf, DBG_RF_RFK, "[RFK]backup bb reg : %x, value =%x\n",
+		      bkup_bb_reg_8852c[i], bkup_bb_val_8852c[i]);
+	}
+}
+
+
+void do_bkup_rf_8852c(struct rf_info *rf, u8 path)
+{
+	u32 i;
+	u32 num = ARRAY_SIZE(bkup_rf_reg_8852c);
+
+	for (i = 0; i < num; i++) {
+		if (i >= RF_BACKUP_RF_REG_MAX_NUM) {
+			RF_DBG(rf, DBG_RF_RFK,
+			       "[RFK] %s backup size not enough\n", __func__);
+			break;
+		}
+		bkup_rf_val_8852c[path][i] = halrf_rrf(rf, path, bkup_rf_reg_8852c[i], MASKRF);
+		
+		RF_DBG(rf, DBG_RF_RFK, "[RFK] Backup RF S%d 0x%x = %x\n",
+			path, bkup_rf_reg_8852c[i], bkup_rf_val_8852c[path][i]);
+	}
+}
+
+void do_reload_kip_8852c(struct rf_info *rf, u8 path) 
+{
+	u32 i;
+	u32 num = ARRAY_SIZE(bkup_kip_reg_8852c);
+
+	for (i = 0; i < num; i++) {
+		halrf_wreg(rf, bkup_kip_reg_8852c[i] + (path << 8), MASKDWORD, bkup_kip_val_8852c[path][i]);
+		
+		RF_DBG(rf, DBG_RF_RFK, "[RFK] Reload KIP(S%d) 0x%x = %x\n",path, bkup_kip_reg_8852c[i] + (path << 8),
+			bkup_kip_val_8852c[path][i]);
+	}
+}
+
+void do_reload_bb_8852c(struct rf_info *rf)
+{
+	u32 i;
+	u32 num = ARRAY_SIZE(bkup_bb_reg_8852c);
+
+	for (i = 0; i < num; i++) {
+		halrf_wreg(rf,  bkup_bb_reg_8852c[i], MASKDWORD, bkup_bb_val_8852c[i]);
+
+		RF_DBG(rf, DBG_RF_RFK, "[RFK] Reload BB 0x%x = 0x%x\n",
+		       bkup_bb_reg_8852c[i], bkup_bb_val_8852c[i]);
+	}
+}
+
+
+void do_reload_rf_8852c(struct rf_info *rf, u8 path)
+{
+	u32 i;
+	u32 num = ARRAY_SIZE(bkup_rf_reg_8852c);
+
+	for (i = 0; i < num; i++) {
+		halrf_wrf(rf, path, bkup_rf_reg_8852c[i], MASKRF, bkup_rf_val_8852c[path][i]);
+		
+			RF_DBG(rf, DBG_RF_RFK, "[RFK] Reload RF S%d 0x%x = %x\n",
+				path, bkup_rf_reg_8852c[i], bkup_rf_val_8852c[path][i]);
+	}
+}
+
+void halrf_set_regulation_from_driver_8852c(struct rf_info *rf,
+	u8 regulation_idx)
+{
+	struct halrf_pwr_info *pwr = &rf->pwr_info;
+
+	pwr->regulation_idx = regulation_idx;
+	RF_DBG(rf, DBG_RF_POWER, "Set regulation_idx=%d\n", pwr->regulation_idx);
+}
+
+bool halrf_set_dbcc_8852c(struct rf_info *rf, bool dbcc_en)
+{
+	halrf_set_syn01_8852c(rf, dbcc_en);
+	if (dbcc_en) {
+		halrf_set_ref_power_to_struct(rf, HW_PHY_1);
+	}
+
+	return true;
+}
+
+void halrf_adie_pow_ctrl_8852c(struct rf_info *rf, bool rf_off, bool others_off)
+{
+#if 1
+	if (rf_off) {
+		halrf_wrf(rf, RF_PATH_A, 0x0, MASKRFMODE,0x0);
+		halrf_wrf(rf, RF_PATH_B, 0x0, MASKRFMODE,0x0);
+		halrf_delay_us(rf, 1000);
+		halrf_wrf(rf, RF_PATH_A, 0x5, MASKRF,0x0);
+		halrf_wrf(rf, RF_PATH_B, 0x5, MASKRF,0x0);
+		halrf_delay_us(rf, 1000);
+		halrf_wrf(rf, RF_PATH_A, 0x0, MASKRF,0x0);
+		halrf_wrf(rf, RF_PATH_B, 0x0, MASKRF,0x0);
+	} 
+	
+	if (others_off) {
+		/*ARFC off*/
+		/*XTAL off*/
+		rtw_hal_mac_set_xsi((rf)->hal_com, 0x0, 0x0);
+	} 
+#endif
+}
+
+void halrf_afe_pow_ctrl_8852c(struct rf_info *rf, bool adda_off, bool pll_off)
+{
+#if 1
+	if (adda_off) {
+		halrf_wmac(rf, 0x14, 0xc0000, 0x0);
+		halrf_wreg(rf, 0x12b8, BIT(30), 0x1);
+		halrf_wreg(rf, 0x32b8, BIT(30), 0x1);
+		halrf_wreg(rf, 0x030c, 0xff000000, 0xe3);
+		halrf_wreg(rf, 0x032c, 0xffff0000, 0x8049);
+		halrf_wreg(rf, 0x032c, BIT(22), 0x0);
+		halrf_wreg(rf, 0x030c, 0x0f000000, 0xc);
+		halrf_wreg(rf, 0x030c, 0xe0000000, 0x0);
+		halrf_wreg(rf, 0x032c, 0x60000000, 0x3);
+		halrf_wreg(rf, 0xc0e4, 0x300, 0x0);
+		halrf_wreg(rf, 0xc1e4, 0x300, 0x0);
+	}
+
+	if (pll_off) {
+		halrf_wmac(rf, 0x248, 0x7, 0x0);
+		halrf_wmac(rf, 0x24c, 0x1, 0x0);
+		halrf_wmac(rf, 0x14, 0x30000, 0x0);
+		halrf_wmac(rf, 0x280, 0x7f, 0x0);
+		halrf_wmac(rf, 0x14, 0x3000000, 0x0);
+	}
+#endif
+}
+
+#ifdef HALRF_MCC_DBCC
+bool halrf_chlk_reload_check_8852c(struct rf_info *rf, enum phl_phy_idx phy) 
+{
+	struct halrf_dbcc_info *dbcc_info = &rf->dbcc_info;
+	struct halrf_mcc_info *mcc_info = &rf->mcc_info;
+	u8 path, i, j, idx, kpath, kch, kband;
+	bool reload = false;
+	u8 get_empty_table = false;
+
+	RF_DBG(rf, DBG_RF_RFK, "[DBCC]======> %s \n", __func__);
+	kpath = halrf_kpath(rf, phy);
+	kch = rf->hal_com->band[phy].cur_chandef.center_ch;
+	kband = rf->hal_com->band[phy].cur_chandef.band;
+	idx = dbcc_info->table_idx;
+	RF_DBG(rf, DBG_RF_RFK, "[DBCC]dbcc_en=%d  prek_is_dbcc=%d\n", rf->hal_com->dbcc_en, dbcc_info->prek_is_dbcc);
+	if (rf->hal_com->dbcc_en || dbcc_info->prek_is_dbcc) {
+		//try reload
+		for(i = 0; i < 2; i++) {
+			if (kpath == RF_AB) {
+				if (kch == dbcc_info->ch[i][1] && kband == dbcc_info->band[i][1] &&
+					kch == dbcc_info->ch[i][0] && kband == dbcc_info->band[i][0]) {
+					idx = i;
+					reload = true;
+				}
+			} else {
+				if (kpath == RF_A)
+					path = 0;
+				else
+					path = 1;
+				if (kch == dbcc_info->ch[i][path] && kband == dbcc_info->band[i][path]) {
+					idx = i;
+					reload = true;
+				}
+			}
+		}
+		if (reload) {
+			halrf_chlk_reload_dbcc(rf, phy, idx);
+			rf->chlk_map = 0xffffffff & (~HAL_RF_IQK) & (~HAL_RF_DPK);
+			RF_DBG(rf, DBG_RF_RFK, "[DBCC]reload kpath=%d, index=%d\n", kpath, idx);
+			RF_DBG(rf, DBG_RF_RFK, "[DBCC]table0 S0 ch=%5d S1 ch=%5d\n", dbcc_info->ch[0][0], dbcc_info->ch[0][1]);
+			RF_DBG(rf, DBG_RF_RFK, "[DBCC]table1 S0 ch=%5d S1 ch=%5d\n", dbcc_info->ch[1][0], dbcc_info->ch[1][1]);
+			RF_DBG(rf, DBG_RF_RFK, "[DBCC]table0 S0 band =%5d S1 band =%5d\n", dbcc_info->band[0][0], dbcc_info->band[0][1]);
+			RF_DBG(rf, DBG_RF_RFK, "[DBCC]table1 S0 band =%5d S1 band =%5d\n", dbcc_info->band[1][0], dbcc_info->band[1][1]);
+			return reload;
+		}
+	}
+	//force K
+	for  (i = 0;  i < 2; i++){
+		if (((dbcc_info->ch[i][0] == 0) && (dbcc_info->ch[i][1] == 0)) ||
+			((dbcc_info->ch[i][0] == kch) && (dbcc_info->band[i][0] == kband)))
+			break;
+	}
+	
+	if (i < 2) {
+		idx = i;
+	} else {
+		if ((kpath == RF_A) && !rf->hal_com->dbcc_en) {
+			halrf_mcc_info_init(rf, phy);
+			//get channel info
+			for  (idx = 0;  idx < 2; idx++) {
+				if (mcc_info->ch[idx] == 0) {
+					get_empty_table = true;
+					break;
+				}
+			}
+
+			if (false == get_empty_table) {
+				idx = mcc_info->table_idx + 1;
+				if (idx > 1) {
+					idx = 0;
+				}
+			}
+		}
+		else {
+			for  (j = 0;  j < 2; j++)
+				if (dbcc_info->ch[j][0] != dbcc_info->ch[j][1] ||
+					dbcc_info->band[j][0] != dbcc_info->band[j][1])
+					break;
+			if (j == 2) {
+				idx++;
+				if (idx > 1)
+					idx = 0;
+			} else {
+				idx = j;
+			}
+		}
+	}
+	rf->chlk_map = 0xffffffff;
+	dbcc_info->prek_is_dbcc = rf->hal_com->dbcc_en;
+	dbcc_info->table_idx = idx;
+	mcc_info->table_idx = idx;
+	for (path = 0; path < 2; path++) {
+		if (kpath & BIT(path)) {
+			dbcc_info->ch[idx][path] = kch;
+			dbcc_info->band[idx][path] = kband;
+		}
+	}
+	RF_DBG(rf, DBG_RF_RFK, "[DBCC]foreK kpath=%d, index=%d\n", kpath, idx);
+	RF_DBG(rf, DBG_RF_RFK, "[DBCC]ch00=%d ch01=%d ch10=%d ch11=%d\n",
+		dbcc_info->ch[0][0], dbcc_info->ch[0][1], dbcc_info->ch[1][0], dbcc_info->ch[1][1]);
+	RF_DBG(rf, DBG_RF_RFK, "[DBCC]band00=%d band01=%d band10=%d band10=%d\n",
+		dbcc_info->band[0][0], dbcc_info->band[0][1], dbcc_info->band[1][0], dbcc_info->band[1][1]);
+	RF_DBG(rf, DBG_RF_RFK, "[DBCC] mcc_info->table_idx=%d\n", mcc_info->table_idx);
+	return reload;
+}
+#endif
+#endif

3rd/devourer/hal/halrf/g6/vendor/halrf_8852c/halrf_8852c_api.h

@@ -0,0 +1,72 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2020  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+#ifndef __HALRF_8852C_API_H__
+#define __HALRF_8852C_API_H__
+#ifdef RF_8852C_SUPPORT
+
+u8 halrf_get_thermal_8852c(struct rf_info *rf, enum rf_path rf_path);
+
+bool halrf_set_dbcc_8852c(struct rf_info *rf, bool dbcc_en);
+
+u32 halrf_mac_get_pwr_reg_8852c(struct rf_info *rf, enum phl_phy_idx phy,
+	u32 addr, u32 mask);
+
+u32 halrf_mac_set_pwr_reg_8852c(struct rf_info *rf, enum phl_phy_idx phy,
+	u32 addr, u32 mask, u32 val);
+
+void halrf_wlan_tx_power_control_8852c(struct rf_info *rf,
+	enum phl_phy_idx phy, enum phl_pwr_ctrl pwr_ctrl_idx,
+	u32 tx_power_val, bool enable);
+
+bool halrf_wl_tx_power_control_8852c(struct rf_info *rf, u32 tx_power_val);
+#ifdef HALRF_THERMAL_PROTECT_SUPPORT
+s8 halrf_get_ther_protected_threshold_8852c(struct rf_info *rf);
+#endif
+s8 halrf_xtal_tracking_offset_8852c(struct rf_info *rf, enum phl_phy_idx phy);
+
+void halrf_syn1_onoff_8852c(struct rf_info *rf, enum phl_phy_idx phy, u8 path, bool syn1_turn_on);
+
+void halrf_txck_force_8852c(struct rf_info *rf, enum rf_path path, bool force, enum dac_ck ck);
+
+void halrf_rxck_force_8852c(struct rf_info *rf, enum rf_path path, bool force, enum adc_ck ck);
+
+void halrf_set_gpio_8852c(struct rf_info *rf, enum phl_phy_idx phy);
+
+void halrf_set_gpio_by_ch_8852c(struct rf_info *rf, enum phl_phy_idx phy, enum band_type band);
+
+void do_bkup_kip_8852c(struct rf_info *rf, u8 path);
+void do_bkup_bb_8852c(struct rf_info *rf);
+void do_bkup_rf_8852c(struct rf_info *rf, u8 path);
+void do_reload_kip_8852c(struct rf_info *rf, u8 path);
+void do_reload_bb_8852c(struct rf_info *rf);
+void do_reload_rf_8852c(struct rf_info *rf, u8 path);
+void halrf_set_regulation_from_driver_8852c(struct rf_info *rf, u8 regulation_idx);
+void halrf_adie_pow_ctrl_8852c(struct rf_info *rf, bool rf_off, bool others_off);
+void halrf_afe_pow_ctrl_8852c(struct rf_info *rf, bool adda_off, bool pll_off);
+#ifdef HALRF_MCC_DBCC
+bool halrf_chlk_reload_check_8852c(struct rf_info *rf, enum phl_phy_idx phy);
+#endif
+#endif
+#endif /*  __INC_PHYDM_API_H_8852C__ */

3rd/devourer/hal/halrf/g6/vendor/halrf_8852c/halrf_dack_8852c.h

@@ -0,0 +1,34 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2020  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+#ifndef __HALRF_DACK_8852C_H__
+#define __HALRF_DACK_8852C_H__
+#ifdef RF_8852C_SUPPORT
+
+#define DACK_VER_8852C 0xc
+
+void halrf_dac_cal_8852c(struct rf_info *rf, bool force);
+void halrf_dack_fwrpt_8852c(struct rf_info *rf, u16 len, u8 *c2h);
+#endif
+#endif /*  __INC_PHYDM_API_H_8852A__ */

3rd/devourer/hal/halrf/g6/vendor/halrf_8852c/halrf_dpk_8852c.h

@@ -0,0 +1,53 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2020  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+#ifndef __HALRF_DPK_8852CH__
+#define __HALRF_DPK_8852CH__
+#ifdef RF_8852C_SUPPORT
+/*--------------------------Define Parameters-------------------------------*/
+#define DPK_VER_8852C 0x1e
+#define DPK_RF_PATH_MAX_8852C 2
+#define DPK_KIP_REG_NUM_8852C 7
+#define DPK_BB_REG_NUM_8852C 2
+#define DPK_RF_REG_NUM_8852C 7
+#define DPK_PATH_A_8852C 1
+#define DPK_PATH_B_8852C 1
+#define PATH_OFST_8852C 0x100
+#define CH_OFST_8852C 0x4
+#define PHY_OFST_8852C 0x80
+#define DPK_BY_NCTL_8852C 1
+#define DPK_RELOAD_EN_8852C 0
+#define DPK_REG_DBG 0
+#define DPK_RXSRAM_DBG_8852C 0
+
+/*---------------------------End Define Parameters----------------------------*/
+
+void halrf_dpk_8852c(struct rf_info *rf, enum phl_phy_idx phy_idx, bool force);
+
+void halrf_dpk_onoff_8852c(struct rf_info *rf, enum rf_path path, bool off);
+
+void halrf_dpk_track_8852c(struct rf_info *rf);
+
+#endif
+#endif /*  __HALRF_DPK_8852CH__ */

3rd/devourer/hal/halrf/g6/vendor/halrf_8852c/halrf_efuse_8852c.h

@@ -0,0 +1,677 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2020  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+#ifndef _HALRF_EFUSE_8852C_H_
+#define _HALRF_EFUSE_8852C_H_
+
+#ifdef RF_8852C_SUPPORT
+
+enum rtw_flash_8852c_info {
+	/* AP customize configs*/
+	FLASH_INFO_START_8852C = (EFUSE_INFO_BTCOEX_MAX + 1),
+	FLASH_INFO_COSTUM_PARA_PATH_8852C = FLASH_INFO_START_8852C,
+
+	/* RF TSSI SLOPE K, GAIN DIFF */
+	FLASH_INFO_RF_2G_CCK_TSSI_GAIN_DIFF_A_8852C_1,
+	FLASH_INFO_RF_2G_CCK_TSSI_GAIN_DIFF_A_8852C_2,
+	FLASH_INFO_RF_2G_CCK_TSSI_GAIN_DIFF_A_8852C_3,
+	FLASH_INFO_RF_2G_CCK_TSSI_GAIN_DIFF_A_8852C_4,
+	FLASH_INFO_RF_2G_CCK_TSSI_GAIN_DIFF_A_8852C_5,
+	FLASH_INFO_RF_2G_CCK_TSSI_GAIN_DIFF_A_8852C_6,
+	FLASH_INFO_RF_2G_TSSI_GAIN_DIFF_A_8852C_1,
+	FLASH_INFO_RF_2G_TSSI_GAIN_DIFF_A_8852C_2,
+	FLASH_INFO_RF_2G_TSSI_GAIN_DIFF_A_8852C_3,
+	FLASH_INFO_RF_2G_TSSI_GAIN_DIFF_A_8852C_4,
+	FLASH_INFO_RF_2G_TSSI_GAIN_DIFF_A_8852C_5,
+	FLASH_INFO_RF_5G_TSSI_GAIN_DIFF_A_8852C_1,
+	FLASH_INFO_RF_5G_TSSI_GAIN_DIFF_A_8852C_2,
+	FLASH_INFO_RF_5G_TSSI_GAIN_DIFF_A_8852C_3,
+	FLASH_INFO_RF_5G_TSSI_GAIN_DIFF_A_8852C_4,
+	FLASH_INFO_RF_5G_TSSI_GAIN_DIFF_A_8852C_5,
+	FLASH_INFO_RF_5G_TSSI_GAIN_DIFF_A_8852C_6,
+	FLASH_INFO_RF_5G_TSSI_GAIN_DIFF_A_8852C_7,
+	FLASH_INFO_RF_5G_TSSI_GAIN_DIFF_A_8852C_8,
+	FLASH_INFO_RF_5G_TSSI_GAIN_DIFF_A_8852C_9,
+	FLASH_INFO_RF_5G_TSSI_GAIN_DIFF_A_8852C_10,
+	FLASH_INFO_RF_5G_TSSI_GAIN_DIFF_A_8852C_11,
+	FLASH_INFO_RF_5G_TSSI_GAIN_DIFF_A_8852C_12,
+	FLASH_INFO_RF_5G_TSSI_GAIN_DIFF_A_8852C_13,
+	FLASH_INFO_RF_5G_TSSI_GAIN_DIFF_A_8852C_14,
+	FLASH_INFO_RF_2G_CCK_TSSI_GAIN_DIFF_B_8852C_1,
+	FLASH_INFO_RF_2G_CCK_TSSI_GAIN_DIFF_B_8852C_2,
+	FLASH_INFO_RF_2G_CCK_TSSI_GAIN_DIFF_B_8852C_3,
+	FLASH_INFO_RF_2G_CCK_TSSI_GAIN_DIFF_B_8852C_4,
+	FLASH_INFO_RF_2G_CCK_TSSI_GAIN_DIFF_B_8852C_5,
+	FLASH_INFO_RF_2G_CCK_TSSI_GAIN_DIFF_B_8852C_6,
+	FLASH_INFO_RF_2G_TSSI_GAIN_DIFF_B_8852C_1,
+	FLASH_INFO_RF_2G_TSSI_GAIN_DIFF_B_8852C_2,
+	FLASH_INFO_RF_2G_TSSI_GAIN_DIFF_B_8852C_3,
+	FLASH_INFO_RF_2G_TSSI_GAIN_DIFF_B_8852C_4,
+	FLASH_INFO_RF_2G_TSSI_GAIN_DIFF_B_8852C_5,
+	FLASH_INFO_RF_5G_TSSI_GAIN_DIFF_B_8852C_1,
+	FLASH_INFO_RF_5G_TSSI_GAIN_DIFF_B_8852C_2,
+	FLASH_INFO_RF_5G_TSSI_GAIN_DIFF_B_8852C_3,
+	FLASH_INFO_RF_5G_TSSI_GAIN_DIFF_B_8852C_4,
+	FLASH_INFO_RF_5G_TSSI_GAIN_DIFF_B_8852C_5,
+	FLASH_INFO_RF_5G_TSSI_GAIN_DIFF_B_8852C_6,
+	FLASH_INFO_RF_5G_TSSI_GAIN_DIFF_B_8852C_7,
+	FLASH_INFO_RF_5G_TSSI_GAIN_DIFF_B_8852C_8,
+	FLASH_INFO_RF_5G_TSSI_GAIN_DIFF_B_8852C_9,
+	FLASH_INFO_RF_5G_TSSI_GAIN_DIFF_B_8852C_10,
+	FLASH_INFO_RF_5G_TSSI_GAIN_DIFF_B_8852C_11,
+	FLASH_INFO_RF_5G_TSSI_GAIN_DIFF_B_8852C_12,
+	FLASH_INFO_RF_5G_TSSI_GAIN_DIFF_B_8852C_13,
+	FLASH_INFO_RF_5G_TSSI_GAIN_DIFF_B_8852C_14,
+	FLASH_INFO_RF_2G_CCK_TSSI_GAIN_DIFF_C_8852C_1,
+	FLASH_INFO_RF_2G_CCK_TSSI_GAIN_DIFF_C_8852C_2,
+	FLASH_INFO_RF_2G_CCK_TSSI_GAIN_DIFF_C_8852C_3,
+	FLASH_INFO_RF_2G_CCK_TSSI_GAIN_DIFF_C_8852C_4,
+	FLASH_INFO_RF_2G_CCK_TSSI_GAIN_DIFF_C_8852C_5,
+	FLASH_INFO_RF_2G_CCK_TSSI_GAIN_DIFF_C_8852C_6,
+	FLASH_INFO_RF_2G_TSSI_GAIN_DIFF_C_8852C_1,
+	FLASH_INFO_RF_2G_TSSI_GAIN_DIFF_C_8852C_2,
+	FLASH_INFO_RF_2G_TSSI_GAIN_DIFF_C_8852C_3,
+	FLASH_INFO_RF_2G_TSSI_GAIN_DIFF_C_8852C_4,
+	FLASH_INFO_RF_2G_TSSI_GAIN_DIFF_C_8852C_5,
+	FLASH_INFO_RF_5G_TSSI_GAIN_DIFF_C_8852C_1,
+	FLASH_INFO_RF_5G_TSSI_GAIN_DIFF_C_8852C_2,
+	FLASH_INFO_RF_5G_TSSI_GAIN_DIFF_C_8852C_3,
+	FLASH_INFO_RF_5G_TSSI_GAIN_DIFF_C_8852C_4,
+	FLASH_INFO_RF_5G_TSSI_GAIN_DIFF_C_8852C_5,
+	FLASH_INFO_RF_5G_TSSI_GAIN_DIFF_C_8852C_6,
+	FLASH_INFO_RF_5G_TSSI_GAIN_DIFF_C_8852C_7,
+	FLASH_INFO_RF_5G_TSSI_GAIN_DIFF_C_8852C_8,
+	FLASH_INFO_RF_5G_TSSI_GAIN_DIFF_C_8852C_9,
+	FLASH_INFO_RF_5G_TSSI_GAIN_DIFF_C_8852C_10,
+	FLASH_INFO_RF_5G_TSSI_GAIN_DIFF_C_8852C_11,
+	FLASH_INFO_RF_5G_TSSI_GAIN_DIFF_C_8852C_12,
+	FLASH_INFO_RF_5G_TSSI_GAIN_DIFF_C_8852C_13,
+	FLASH_INFO_RF_5G_TSSI_GAIN_DIFF_C_8852C_14,
+	FLASH_INFO_RF_2G_CCK_TSSI_GAIN_DIFF_D_8852C_1,
+	FLASH_INFO_RF_2G_CCK_TSSI_GAIN_DIFF_D_8852C_2,
+	FLASH_INFO_RF_2G_CCK_TSSI_GAIN_DIFF_D_8852C_3,
+	FLASH_INFO_RF_2G_CCK_TSSI_GAIN_DIFF_D_8852C_4,
+	FLASH_INFO_RF_2G_CCK_TSSI_GAIN_DIFF_D_8852C_5,
+	FLASH_INFO_RF_2G_CCK_TSSI_GAIN_DIFF_D_8852C_6,
+	FLASH_INFO_RF_2G_TSSI_GAIN_DIFF_D_8852C_1,
+	FLASH_INFO_RF_2G_TSSI_GAIN_DIFF_D_8852C_2,
+	FLASH_INFO_RF_2G_TSSI_GAIN_DIFF_D_8852C_3,
+	FLASH_INFO_RF_2G_TSSI_GAIN_DIFF_D_8852C_4,
+	FLASH_INFO_RF_2G_TSSI_GAIN_DIFF_D_8852C_5,
+	FLASH_INFO_RF_5G_TSSI_GAIN_DIFF_D_8852C_1,
+	FLASH_INFO_RF_5G_TSSI_GAIN_DIFF_D_8852C_2,
+	FLASH_INFO_RF_5G_TSSI_GAIN_DIFF_D_8852C_3,
+	FLASH_INFO_RF_5G_TSSI_GAIN_DIFF_D_8852C_4,
+	FLASH_INFO_RF_5G_TSSI_GAIN_DIFF_D_8852C_5,
+	FLASH_INFO_RF_5G_TSSI_GAIN_DIFF_D_8852C_6,
+	FLASH_INFO_RF_5G_TSSI_GAIN_DIFF_D_8852C_7,
+	FLASH_INFO_RF_5G_TSSI_GAIN_DIFF_D_8852C_8,
+	FLASH_INFO_RF_5G_TSSI_GAIN_DIFF_D_8852C_9,
+	FLASH_INFO_RF_5G_TSSI_GAIN_DIFF_D_8852C_10,
+	FLASH_INFO_RF_5G_TSSI_GAIN_DIFF_D_8852C_11,
+	FLASH_INFO_RF_5G_TSSI_GAIN_DIFF_D_8852C_12,
+	FLASH_INFO_RF_5G_TSSI_GAIN_DIFF_D_8852C_13,
+	FLASH_INFO_RF_5G_TSSI_GAIN_DIFF_D_8852C_14,
+
+	/* RF TSSI SLOPE K, CW DIFF */
+	FLASH_INFO_RF_2G_CCK_TSSI_CW_DIFF_A_8852C_1,
+	FLASH_INFO_RF_2G_CCK_TSSI_CW_DIFF_A_8852C_2,
+	FLASH_INFO_RF_2G_CCK_TSSI_CW_DIFF_A_8852C_3,
+	FLASH_INFO_RF_2G_CCK_TSSI_CW_DIFF_A_8852C_4,
+	FLASH_INFO_RF_2G_CCK_TSSI_CW_DIFF_A_8852C_5,
+	FLASH_INFO_RF_2G_CCK_TSSI_CW_DIFF_A_8852C_6,
+	FLASH_INFO_RF_2G_TSSI_CW_DIFF_A_8852C_1,
+	FLASH_INFO_RF_2G_TSSI_CW_DIFF_A_8852C_2,
+	FLASH_INFO_RF_2G_TSSI_CW_DIFF_A_8852C_3,
+	FLASH_INFO_RF_2G_TSSI_CW_DIFF_A_8852C_4,
+	FLASH_INFO_RF_2G_TSSI_CW_DIFF_A_8852C_5,
+	FLASH_INFO_RF_5G_TSSI_CW_DIFF_A_8852C_1,
+	FLASH_INFO_RF_5G_TSSI_CW_DIFF_A_8852C_2,
+	FLASH_INFO_RF_5G_TSSI_CW_DIFF_A_8852C_3,
+	FLASH_INFO_RF_5G_TSSI_CW_DIFF_A_8852C_4,
+	FLASH_INFO_RF_5G_TSSI_CW_DIFF_A_8852C_5,
+	FLASH_INFO_RF_5G_TSSI_CW_DIFF_A_8852C_6,
+	FLASH_INFO_RF_5G_TSSI_CW_DIFF_A_8852C_7,
+	FLASH_INFO_RF_5G_TSSI_CW_DIFF_A_8852C_8,
+	FLASH_INFO_RF_5G_TSSI_CW_DIFF_A_8852C_9,
+	FLASH_INFO_RF_5G_TSSI_CW_DIFF_A_8852C_10,
+	FLASH_INFO_RF_5G_TSSI_CW_DIFF_A_8852C_11,
+	FLASH_INFO_RF_5G_TSSI_CW_DIFF_A_8852C_12,
+	FLASH_INFO_RF_5G_TSSI_CW_DIFF_A_8852C_13,
+	FLASH_INFO_RF_5G_TSSI_CW_DIFF_A_8852C_14,
+	FLASH_INFO_RF_2G_CCK_TSSI_CW_DIFF_B_8852C_1,
+	FLASH_INFO_RF_2G_CCK_TSSI_CW_DIFF_B_8852C_2,
+	FLASH_INFO_RF_2G_CCK_TSSI_CW_DIFF_B_8852C_3,
+	FLASH_INFO_RF_2G_CCK_TSSI_CW_DIFF_B_8852C_4,
+	FLASH_INFO_RF_2G_CCK_TSSI_CW_DIFF_B_8852C_5,
+	FLASH_INFO_RF_2G_CCK_TSSI_CW_DIFF_B_8852C_6,
+	FLASH_INFO_RF_2G_TSSI_CW_DIFF_B_8852C_1,
+	FLASH_INFO_RF_2G_TSSI_CW_DIFF_B_8852C_2,
+	FLASH_INFO_RF_2G_TSSI_CW_DIFF_B_8852C_3,
+	FLASH_INFO_RF_2G_TSSI_CW_DIFF_B_8852C_4,
+	FLASH_INFO_RF_2G_TSSI_CW_DIFF_B_8852C_5,
+	FLASH_INFO_RF_5G_TSSI_CW_DIFF_B_8852C_1,
+	FLASH_INFO_RF_5G_TSSI_CW_DIFF_B_8852C_2,
+	FLASH_INFO_RF_5G_TSSI_CW_DIFF_B_8852C_3,
+	FLASH_INFO_RF_5G_TSSI_CW_DIFF_B_8852C_4,
+	FLASH_INFO_RF_5G_TSSI_CW_DIFF_B_8852C_5,
+	FLASH_INFO_RF_5G_TSSI_CW_DIFF_B_8852C_6,
+	FLASH_INFO_RF_5G_TSSI_CW_DIFF_B_8852C_7,
+	FLASH_INFO_RF_5G_TSSI_CW_DIFF_B_8852C_8,
+	FLASH_INFO_RF_5G_TSSI_CW_DIFF_B_8852C_9,
+	FLASH_INFO_RF_5G_TSSI_CW_DIFF_B_8852C_10,
+	FLASH_INFO_RF_5G_TSSI_CW_DIFF_B_8852C_11,
+	FLASH_INFO_RF_5G_TSSI_CW_DIFF_B_8852C_12,
+	FLASH_INFO_RF_5G_TSSI_CW_DIFF_B_8852C_13,
+	FLASH_INFO_RF_5G_TSSI_CW_DIFF_B_8852C_14,
+	FLASH_INFO_RF_2G_CCK_TSSI_CW_DIFF_C_8852C_1,
+	FLASH_INFO_RF_2G_CCK_TSSI_CW_DIFF_C_8852C_2,
+	FLASH_INFO_RF_2G_CCK_TSSI_CW_DIFF_C_8852C_3,
+	FLASH_INFO_RF_2G_CCK_TSSI_CW_DIFF_C_8852C_4,
+	FLASH_INFO_RF_2G_CCK_TSSI_CW_DIFF_C_8852C_5,
+	FLASH_INFO_RF_2G_CCK_TSSI_CW_DIFF_C_8852C_6,
+	FLASH_INFO_RF_2G_TSSI_CW_DIFF_C_8852C_1,
+	FLASH_INFO_RF_2G_TSSI_CW_DIFF_C_8852C_2,
+	FLASH_INFO_RF_2G_TSSI_CW_DIFF_C_8852C_3,
+	FLASH_INFO_RF_2G_TSSI_CW_DIFF_C_8852C_4,
+	FLASH_INFO_RF_2G_TSSI_CW_DIFF_C_8852C_5,
+	FLASH_INFO_RF_5G_TSSI_CW_DIFF_C_8852C_1,
+	FLASH_INFO_RF_5G_TSSI_CW_DIFF_C_8852C_2,
+	FLASH_INFO_RF_5G_TSSI_CW_DIFF_C_8852C_3,
+	FLASH_INFO_RF_5G_TSSI_CW_DIFF_C_8852C_4,
+	FLASH_INFO_RF_5G_TSSI_CW_DIFF_C_8852C_5,
+	FLASH_INFO_RF_5G_TSSI_CW_DIFF_C_8852C_6,
+	FLASH_INFO_RF_5G_TSSI_CW_DIFF_C_8852C_7,
+	FLASH_INFO_RF_5G_TSSI_CW_DIFF_C_8852C_8,
+	FLASH_INFO_RF_5G_TSSI_CW_DIFF_C_8852C_9,
+	FLASH_INFO_RF_5G_TSSI_CW_DIFF_C_8852C_10,
+	FLASH_INFO_RF_5G_TSSI_CW_DIFF_C_8852C_11,
+	FLASH_INFO_RF_5G_TSSI_CW_DIFF_C_8852C_12,
+	FLASH_INFO_RF_5G_TSSI_CW_DIFF_C_8852C_13,
+	FLASH_INFO_RF_5G_TSSI_CW_DIFF_C_8852C_14,
+	FLASH_INFO_RF_2G_CCK_TSSI_CW_DIFF_D_8852C_1,
+	FLASH_INFO_RF_2G_CCK_TSSI_CW_DIFF_D_8852C_2,
+	FLASH_INFO_RF_2G_CCK_TSSI_CW_DIFF_D_8852C_3,
+	FLASH_INFO_RF_2G_CCK_TSSI_CW_DIFF_D_8852C_4,
+	FLASH_INFO_RF_2G_CCK_TSSI_CW_DIFF_D_8852C_5,
+	FLASH_INFO_RF_2G_CCK_TSSI_CW_DIFF_D_8852C_6,
+	FLASH_INFO_RF_2G_TSSI_CW_DIFF_D_8852C_1,
+	FLASH_INFO_RF_2G_TSSI_CW_DIFF_D_8852C_2,
+	FLASH_INFO_RF_2G_TSSI_CW_DIFF_D_8852C_3,
+	FLASH_INFO_RF_2G_TSSI_CW_DIFF_D_8852C_4,
+	FLASH_INFO_RF_2G_TSSI_CW_DIFF_D_8852C_5,
+	FLASH_INFO_RF_5G_TSSI_CW_DIFF_D_8852C_1,
+	FLASH_INFO_RF_5G_TSSI_CW_DIFF_D_8852C_2,
+	FLASH_INFO_RF_5G_TSSI_CW_DIFF_D_8852C_3,
+	FLASH_INFO_RF_5G_TSSI_CW_DIFF_D_8852C_4,
+	FLASH_INFO_RF_5G_TSSI_CW_DIFF_D_8852C_5,
+	FLASH_INFO_RF_5G_TSSI_CW_DIFF_D_8852C_6,
+	FLASH_INFO_RF_5G_TSSI_CW_DIFF_D_8852C_7,
+	FLASH_INFO_RF_5G_TSSI_CW_DIFF_D_8852C_8,
+	FLASH_INFO_RF_5G_TSSI_CW_DIFF_D_8852C_9,
+	FLASH_INFO_RF_5G_TSSI_CW_DIFF_D_8852C_10,
+	FLASH_INFO_RF_5G_TSSI_CW_DIFF_D_8852C_11,
+	FLASH_INFO_RF_5G_TSSI_CW_DIFF_D_8852C_12,
+	FLASH_INFO_RF_5G_TSSI_CW_DIFF_D_8852C_13,
+	FLASH_INFO_RF_5G_TSSI_CW_DIFF_D_8852C_14,
+
+	/* RF 20M 80M 160M, TSSI DIFF */
+	FLASH_INFO_RF_5G_BW20M_BW40M_TSSI_DIFF_A_8852C_1,
+	FLASH_INFO_RF_5G_BW20M_BW40M_TSSI_DIFF_A_8852C_2,
+	FLASH_INFO_RF_5G_BW20M_BW40M_TSSI_DIFF_A_8852C_3,
+	FLASH_INFO_RF_5G_BW20M_BW40M_TSSI_DIFF_A_8852C_4,
+	FLASH_INFO_RF_5G_BW20M_BW40M_TSSI_DIFF_A_8852C_5,
+	FLASH_INFO_RF_5G_BW20M_BW40M_TSSI_DIFF_A_8852C_6,
+	FLASH_INFO_RF_5G_BW20M_BW40M_TSSI_DIFF_A_8852C_7,
+	FLASH_INFO_RF_5G_BW20M_BW40M_TSSI_DIFF_A_8852C_8,
+	FLASH_INFO_RF_5G_BW20M_BW40M_TSSI_DIFF_A_8852C_9,
+	FLASH_INFO_RF_5G_BW20M_BW40M_TSSI_DIFF_A_8852C_10,
+	FLASH_INFO_RF_5G_BW20M_BW40M_TSSI_DIFF_A_8852C_11,
+	FLASH_INFO_RF_5G_BW20M_BW40M_TSSI_DIFF_A_8852C_12,
+	FLASH_INFO_RF_5G_BW20M_BW40M_TSSI_DIFF_A_8852C_13,
+	FLASH_INFO_RF_5G_BW20M_BW40M_TSSI_DIFF_A_8852C_14,
+	FLASH_INFO_RF_5G_BW80M_BW40M_TSSI_DIFF_A_8852C_1,
+	FLASH_INFO_RF_5G_BW80M_BW40M_TSSI_DIFF_A_8852C_2,
+	FLASH_INFO_RF_5G_BW80M_BW40M_TSSI_DIFF_A_8852C_3,
+	FLASH_INFO_RF_5G_BW80M_BW40M_TSSI_DIFF_A_8852C_4,
+	FLASH_INFO_RF_5G_BW80M_BW40M_TSSI_DIFF_A_8852C_5,
+	FLASH_INFO_RF_5G_BW80M_BW40M_TSSI_DIFF_A_8852C_6,
+	FLASH_INFO_RF_5G_BW80M_BW40M_TSSI_DIFF_A_8852C_7,
+	FLASH_INFO_RF_5G_BW80M_BW40M_TSSI_DIFF_A_8852C_8,
+	FLASH_INFO_RF_5G_BW80M_BW40M_TSSI_DIFF_A_8852C_9,
+	FLASH_INFO_RF_5G_BW80M_BW40M_TSSI_DIFF_A_8852C_10,
+	FLASH_INFO_RF_5G_BW80M_BW40M_TSSI_DIFF_A_8852C_11,
+	FLASH_INFO_RF_5G_BW80M_BW40M_TSSI_DIFF_A_8852C_12,
+	FLASH_INFO_RF_5G_BW80M_BW40M_TSSI_DIFF_A_8852C_13,
+	FLASH_INFO_RF_5G_BW80M_BW40M_TSSI_DIFF_A_8852C_14,
+	FLASH_INFO_RF_5G_BW160M_BW40M_TSSI_DIFF_A_8852C_1,
+	FLASH_INFO_RF_5G_BW160M_BW40M_TSSI_DIFF_A_8852C_2,
+	FLASH_INFO_RF_5G_BW160M_BW40M_TSSI_DIFF_A_8852C_3,
+	FLASH_INFO_RF_5G_BW160M_BW40M_TSSI_DIFF_A_8852C_4,
+	FLASH_INFO_RF_5G_BW160M_BW40M_TSSI_DIFF_A_8852C_5,
+	FLASH_INFO_RF_5G_BW160M_BW40M_TSSI_DIFF_A_8852C_6,
+	FLASH_INFO_RF_5G_BW160M_BW40M_TSSI_DIFF_A_8852C_7,
+	FLASH_INFO_RF_5G_BW160M_BW40M_TSSI_DIFF_A_8852C_8,
+	FLASH_INFO_RF_5G_BW160M_BW40M_TSSI_DIFF_A_8852C_9,
+	FLASH_INFO_RF_5G_BW160M_BW40M_TSSI_DIFF_A_8852C_10,
+	FLASH_INFO_RF_5G_BW160M_BW40M_TSSI_DIFF_A_8852C_11,
+	FLASH_INFO_RF_5G_BW160M_BW40M_TSSI_DIFF_A_8852C_12,
+	FLASH_INFO_RF_5G_BW160M_BW40M_TSSI_DIFF_A_8852C_13,
+	FLASH_INFO_RF_5G_BW160M_BW40M_TSSI_DIFF_A_8852C_14,
+	FLASH_INFO_RF_5G_BW20M_BW40M_TSSI_DIFF_B_8852C_1,
+	FLASH_INFO_RF_5G_BW20M_BW40M_TSSI_DIFF_B_8852C_2,
+	FLASH_INFO_RF_5G_BW20M_BW40M_TSSI_DIFF_B_8852C_3,
+	FLASH_INFO_RF_5G_BW20M_BW40M_TSSI_DIFF_B_8852C_4,
+	FLASH_INFO_RF_5G_BW20M_BW40M_TSSI_DIFF_B_8852C_5,
+	FLASH_INFO_RF_5G_BW20M_BW40M_TSSI_DIFF_B_8852C_6,
+	FLASH_INFO_RF_5G_BW20M_BW40M_TSSI_DIFF_B_8852C_7,
+	FLASH_INFO_RF_5G_BW20M_BW40M_TSSI_DIFF_B_8852C_8,
+	FLASH_INFO_RF_5G_BW20M_BW40M_TSSI_DIFF_B_8852C_9,
+	FLASH_INFO_RF_5G_BW20M_BW40M_TSSI_DIFF_B_8852C_10,
+	FLASH_INFO_RF_5G_BW20M_BW40M_TSSI_DIFF_B_8852C_11,
+	FLASH_INFO_RF_5G_BW20M_BW40M_TSSI_DIFF_B_8852C_12,
+	FLASH_INFO_RF_5G_BW20M_BW40M_TSSI_DIFF_B_8852C_13,
+	FLASH_INFO_RF_5G_BW20M_BW40M_TSSI_DIFF_B_8852C_14,
+	FLASH_INFO_RF_5G_BW80M_BW40M_TSSI_DIFF_B_8852C_1,
+	FLASH_INFO_RF_5G_BW80M_BW40M_TSSI_DIFF_B_8852C_2,
+	FLASH_INFO_RF_5G_BW80M_BW40M_TSSI_DIFF_B_8852C_3,
+	FLASH_INFO_RF_5G_BW80M_BW40M_TSSI_DIFF_B_8852C_4,
+	FLASH_INFO_RF_5G_BW80M_BW40M_TSSI_DIFF_B_8852C_5,
+	FLASH_INFO_RF_5G_BW80M_BW40M_TSSI_DIFF_B_8852C_6,
+	FLASH_INFO_RF_5G_BW80M_BW40M_TSSI_DIFF_B_8852C_7,
+	FLASH_INFO_RF_5G_BW80M_BW40M_TSSI_DIFF_B_8852C_8,
+	FLASH_INFO_RF_5G_BW80M_BW40M_TSSI_DIFF_B_8852C_9,
+	FLASH_INFO_RF_5G_BW80M_BW40M_TSSI_DIFF_B_8852C_10,
+	FLASH_INFO_RF_5G_BW80M_BW40M_TSSI_DIFF_B_8852C_11,
+	FLASH_INFO_RF_5G_BW80M_BW40M_TSSI_DIFF_B_8852C_12,
+	FLASH_INFO_RF_5G_BW80M_BW40M_TSSI_DIFF_B_8852C_13,
+	FLASH_INFO_RF_5G_BW80M_BW40M_TSSI_DIFF_B_8852C_14,
+	FLASH_INFO_RF_5G_BW160M_BW40M_TSSI_DIFF_B_8852C_1,
+	FLASH_INFO_RF_5G_BW160M_BW40M_TSSI_DIFF_B_8852C_2,
+	FLASH_INFO_RF_5G_BW160M_BW40M_TSSI_DIFF_B_8852C_3,
+	FLASH_INFO_RF_5G_BW160M_BW40M_TSSI_DIFF_B_8852C_4,
+	FLASH_INFO_RF_5G_BW160M_BW40M_TSSI_DIFF_B_8852C_5,
+	FLASH_INFO_RF_5G_BW160M_BW40M_TSSI_DIFF_B_8852C_6,
+	FLASH_INFO_RF_5G_BW160M_BW40M_TSSI_DIFF_B_8852C_7,
+	FLASH_INFO_RF_5G_BW160M_BW40M_TSSI_DIFF_B_8852C_8,
+	FLASH_INFO_RF_5G_BW160M_BW40M_TSSI_DIFF_B_8852C_9,
+	FLASH_INFO_RF_5G_BW160M_BW40M_TSSI_DIFF_B_8852C_10,
+	FLASH_INFO_RF_5G_BW160M_BW40M_TSSI_DIFF_B_8852C_11,
+	FLASH_INFO_RF_5G_BW160M_BW40M_TSSI_DIFF_B_8852C_12,
+	FLASH_INFO_RF_5G_BW160M_BW40M_TSSI_DIFF_B_8852C_13,
+	FLASH_INFO_RF_5G_BW160M_BW40M_TSSI_DIFF_B_8852C_14,
+	FLASH_INFO_RF_5G_BW20M_BW40M_TSSI_DIFF_C_8852C_1,
+	FLASH_INFO_RF_5G_BW20M_BW40M_TSSI_DIFF_C_8852C_2,
+	FLASH_INFO_RF_5G_BW20M_BW40M_TSSI_DIFF_C_8852C_3,
+	FLASH_INFO_RF_5G_BW20M_BW40M_TSSI_DIFF_C_8852C_4,
+	FLASH_INFO_RF_5G_BW20M_BW40M_TSSI_DIFF_C_8852C_5,
+	FLASH_INFO_RF_5G_BW20M_BW40M_TSSI_DIFF_C_8852C_6,
+	FLASH_INFO_RF_5G_BW20M_BW40M_TSSI_DIFF_C_8852C_7,
+	FLASH_INFO_RF_5G_BW20M_BW40M_TSSI_DIFF_C_8852C_8,
+	FLASH_INFO_RF_5G_BW20M_BW40M_TSSI_DIFF_C_8852C_9,
+	FLASH_INFO_RF_5G_BW20M_BW40M_TSSI_DIFF_C_8852C_10,
+	FLASH_INFO_RF_5G_BW20M_BW40M_TSSI_DIFF_C_8852C_11,
+	FLASH_INFO_RF_5G_BW20M_BW40M_TSSI_DIFF_C_8852C_12,
+	FLASH_INFO_RF_5G_BW20M_BW40M_TSSI_DIFF_C_8852C_13,
+	FLASH_INFO_RF_5G_BW20M_BW40M_TSSI_DIFF_C_8852C_14,
+	FLASH_INFO_RF_5G_BW80M_BW40M_TSSI_DIFF_C_8852C_1,
+	FLASH_INFO_RF_5G_BW80M_BW40M_TSSI_DIFF_C_8852C_2,
+	FLASH_INFO_RF_5G_BW80M_BW40M_TSSI_DIFF_C_8852C_3,
+	FLASH_INFO_RF_5G_BW80M_BW40M_TSSI_DIFF_C_8852C_4,
+	FLASH_INFO_RF_5G_BW80M_BW40M_TSSI_DIFF_C_8852C_5,
+	FLASH_INFO_RF_5G_BW80M_BW40M_TSSI_DIFF_C_8852C_6,
+	FLASH_INFO_RF_5G_BW80M_BW40M_TSSI_DIFF_C_8852C_7,
+	FLASH_INFO_RF_5G_BW80M_BW40M_TSSI_DIFF_C_8852C_8,
+	FLASH_INFO_RF_5G_BW80M_BW40M_TSSI_DIFF_C_8852C_9,
+	FLASH_INFO_RF_5G_BW80M_BW40M_TSSI_DIFF_C_8852C_10,
+	FLASH_INFO_RF_5G_BW80M_BW40M_TSSI_DIFF_C_8852C_11,
+	FLASH_INFO_RF_5G_BW80M_BW40M_TSSI_DIFF_C_8852C_12,
+	FLASH_INFO_RF_5G_BW80M_BW40M_TSSI_DIFF_C_8852C_13,
+	FLASH_INFO_RF_5G_BW80M_BW40M_TSSI_DIFF_C_8852C_14,
+	FLASH_INFO_RF_5G_BW160M_BW40M_TSSI_DIFF_C_8852C_1,
+	FLASH_INFO_RF_5G_BW160M_BW40M_TSSI_DIFF_C_8852C_2,
+	FLASH_INFO_RF_5G_BW160M_BW40M_TSSI_DIFF_C_8852C_3,
+	FLASH_INFO_RF_5G_BW160M_BW40M_TSSI_DIFF_C_8852C_4,
+	FLASH_INFO_RF_5G_BW160M_BW40M_TSSI_DIFF_C_8852C_5,
+	FLASH_INFO_RF_5G_BW160M_BW40M_TSSI_DIFF_C_8852C_6,
+	FLASH_INFO_RF_5G_BW160M_BW40M_TSSI_DIFF_C_8852C_7,
+	FLASH_INFO_RF_5G_BW160M_BW40M_TSSI_DIFF_C_8852C_8,
+	FLASH_INFO_RF_5G_BW160M_BW40M_TSSI_DIFF_C_8852C_9,
+	FLASH_INFO_RF_5G_BW160M_BW40M_TSSI_DIFF_C_8852C_10,
+	FLASH_INFO_RF_5G_BW160M_BW40M_TSSI_DIFF_C_8852C_11,
+	FLASH_INFO_RF_5G_BW160M_BW40M_TSSI_DIFF_C_8852C_12,
+	FLASH_INFO_RF_5G_BW160M_BW40M_TSSI_DIFF_C_8852C_13,
+	FLASH_INFO_RF_5G_BW160M_BW40M_TSSI_DIFF_C_8852C_14,
+	FLASH_INFO_RF_5G_BW20M_BW40M_TSSI_DIFF_D_8852C_1,
+	FLASH_INFO_RF_5G_BW20M_BW40M_TSSI_DIFF_D_8852C_2,
+	FLASH_INFO_RF_5G_BW20M_BW40M_TSSI_DIFF_D_8852C_3,
+	FLASH_INFO_RF_5G_BW20M_BW40M_TSSI_DIFF_D_8852C_4,
+	FLASH_INFO_RF_5G_BW20M_BW40M_TSSI_DIFF_D_8852C_5,
+	FLASH_INFO_RF_5G_BW20M_BW40M_TSSI_DIFF_D_8852C_6,
+	FLASH_INFO_RF_5G_BW20M_BW40M_TSSI_DIFF_D_8852C_7,
+	FLASH_INFO_RF_5G_BW20M_BW40M_TSSI_DIFF_D_8852C_8,
+	FLASH_INFO_RF_5G_BW20M_BW40M_TSSI_DIFF_D_8852C_9,
+	FLASH_INFO_RF_5G_BW20M_BW40M_TSSI_DIFF_D_8852C_10,
+	FLASH_INFO_RF_5G_BW20M_BW40M_TSSI_DIFF_D_8852C_11,
+	FLASH_INFO_RF_5G_BW20M_BW40M_TSSI_DIFF_D_8852C_12,
+	FLASH_INFO_RF_5G_BW20M_BW40M_TSSI_DIFF_D_8852C_13,
+	FLASH_INFO_RF_5G_BW20M_BW40M_TSSI_DIFF_D_8852C_14,
+	FLASH_INFO_RF_5G_BW80M_BW40M_TSSI_DIFF_D_8852C_1,
+	FLASH_INFO_RF_5G_BW80M_BW40M_TSSI_DIFF_D_8852C_2,
+	FLASH_INFO_RF_5G_BW80M_BW40M_TSSI_DIFF_D_8852C_3,
+	FLASH_INFO_RF_5G_BW80M_BW40M_TSSI_DIFF_D_8852C_4,
+	FLASH_INFO_RF_5G_BW80M_BW40M_TSSI_DIFF_D_8852C_5,
+	FLASH_INFO_RF_5G_BW80M_BW40M_TSSI_DIFF_D_8852C_6,
+	FLASH_INFO_RF_5G_BW80M_BW40M_TSSI_DIFF_D_8852C_7,
+	FLASH_INFO_RF_5G_BW80M_BW40M_TSSI_DIFF_D_8852C_8,
+	FLASH_INFO_RF_5G_BW80M_BW40M_TSSI_DIFF_D_8852C_9,
+	FLASH_INFO_RF_5G_BW80M_BW40M_TSSI_DIFF_D_8852C_10,
+	FLASH_INFO_RF_5G_BW80M_BW40M_TSSI_DIFF_D_8852C_11,
+	FLASH_INFO_RF_5G_BW80M_BW40M_TSSI_DIFF_D_8852C_12,
+	FLASH_INFO_RF_5G_BW80M_BW40M_TSSI_DIFF_D_8852C_13,
+	FLASH_INFO_RF_5G_BW80M_BW40M_TSSI_DIFF_D_8852C_14,
+	FLASH_INFO_RF_5G_BW160M_BW40M_TSSI_DIFF_D_8852C_1,
+	FLASH_INFO_RF_5G_BW160M_BW40M_TSSI_DIFF_D_8852C_2,
+	FLASH_INFO_RF_5G_BW160M_BW40M_TSSI_DIFF_D_8852C_3,
+	FLASH_INFO_RF_5G_BW160M_BW40M_TSSI_DIFF_D_8852C_4,
+	FLASH_INFO_RF_5G_BW160M_BW40M_TSSI_DIFF_D_8852C_5,
+	FLASH_INFO_RF_5G_BW160M_BW40M_TSSI_DIFF_D_8852C_6,
+	FLASH_INFO_RF_5G_BW160M_BW40M_TSSI_DIFF_D_8852C_7,
+	FLASH_INFO_RF_5G_BW160M_BW40M_TSSI_DIFF_D_8852C_8,
+	FLASH_INFO_RF_5G_BW160M_BW40M_TSSI_DIFF_D_8852C_9,
+	FLASH_INFO_RF_5G_BW160M_BW40M_TSSI_DIFF_D_8852C_10,
+	FLASH_INFO_RF_5G_BW160M_BW40M_TSSI_DIFF_D_8852C_11,
+	FLASH_INFO_RF_5G_BW160M_BW40M_TSSI_DIFF_D_8852C_12,
+	FLASH_INFO_RF_5G_BW160M_BW40M_TSSI_DIFF_D_8852C_13,
+	FLASH_INFO_RF_5G_BW160M_BW40M_TSSI_DIFF_D_8852C_14,
+
+	/*Error Code*/
+	FLASH_INFO_ID_ERROR_8852C,
+};
+
+enum halrf_efsue_info_8852c_offset {
+	EFUSE_INFO_RF_BOARD_OPTION_8852C_ADDR	= 0x2c1,
+	EFUSE_INFO_RF_RFE_8852C_ADDR		= 0x2ca,
+	EFUSE_INFO_RF_CHAN_PLAN_8852C_ADDR	= 0x2b8,
+	EFUSE_INFO_RF_CHAN_PLAN_6GHZ_8852C_ADDR	= 0x3b8,
+	EFUSE_INFO_RF_XTAL_8852C_ADDR		= 0x2b9,
+	EFUSE_INFO_RF_COUNTRY_CODE1_8852C_ADDR	= 0x2cb,
+	EFUSE_INFO_RF_COUNTRY_CODE2_8852C_ADDR	= 0x2cc,
+	EFUSE_INFO_RF_THERMAL_A_8852C_ADDR	= 0x2d0,
+	EFUSE_INFO_RF_THERMAL_B_8852C_ADDR	= 0x2d1,
+	EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_1_8852C_ADDR	= 0x210,
+	EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_2_8852C_ADDR	= 0x211,
+	EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_3_8852C_ADDR	= 0x212,
+	EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_4_8852C_ADDR	= 0x213,
+	EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_5_8852C_ADDR	= 0x214,
+	EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_6_8852C_ADDR	= 0x215,
+	EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_1_8852C_ADDR	= 0x216,
+	EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_2_8852C_ADDR	= 0x217,
+	EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_3_8852C_ADDR	= 0x218,
+	EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_4_8852C_ADDR	= 0x219,
+	EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_5_8852C_ADDR	= 0x21a,
+	EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_1_8852C_ADDR	= 0x222,
+	EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_2_8852C_ADDR	= 0x223,
+	EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_3_8852C_ADDR	= 0x224,
+	EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_4_8852C_ADDR	= 0x225,
+	EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_5_8852C_ADDR	= 0x226,
+	EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_6_8852C_ADDR	= 0x227,
+	EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_7_8852C_ADDR	= 0x228,
+	EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_8_8852C_ADDR	= 0x229,
+	EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_9_8852C_ADDR	= 0x22a,
+	EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_10_8852C_ADDR	= 0x22b,
+	EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_11_8852C_ADDR	= 0x22c,
+	EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_12_8852C_ADDR	= 0x22d,
+	EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_13_8852C_ADDR	= 0x22e,
+	EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_14_8852C_ADDR	= 0x22f,
+	EFUSE_INFO_RF_5G_BW20M1S_BW40M1S_A_DIFF_8852C_ADDR	= 0x230,
+	EFUSE_INFO_RF_5G_OFDM1T_BW40M1S_A_DIFF_8852C_ADDR	= 0x230,
+	EFUSE_INFO_RF_5G_BW40M2S_BW40M1S_A_DIFF_8852C_ADDR	= 0x231,
+	EFUSE_INFO_RF_5G_BW20M2S_BW20M1S_A_DIFF_8852C_ADDR	= 0x231,
+	EFUSE_INFO_RF_5G_BW40M3S_BW40M2S_A_DIFF_8852C_ADDR	= 0x232,
+	EFUSE_INFO_RF_5G_BW20M3S_BW20M2S_A_DIFF_8852C_ADDR	= 0x232,
+	EFUSE_INFO_RF_5G_BW40M4S_BW40M3S_A_DIFF_8852C_ADDR	= 0x233,
+	EFUSE_INFO_RF_5G_BW20M4S_BW20M3S_A_DIFF_8852C_ADDR	= 0x233,
+	EFUSE_INFO_RF_5G_OFDM2T_OFDM1T_A_DIFF_8852C_ADDR	= 0x234,
+	EFUSE_INFO_RF_5G_OFDM3T_OFDM2T_A_DIFF_8852C_ADDR	= 0x234,
+	EFUSE_INFO_RF_5G_OFDM4T_OFDM3T_A_DIFF_8852C_ADDR	= 0x235,
+	EFUSE_INFO_RF_5G_BW80M1S_BW40M1S_A_DIFF_8852C_ADDR	= 0x236,
+	EFUSE_INFO_RF_5G_BW160M1S_BW80M1S_A_DIFF_8852C_ADDR	= 0x236,
+	EFUSE_INFO_RF_5G_BW80M2S_BW80M1S_A_DIFF_8852C_ADDR	= 0x237,
+	EFUSE_INFO_RF_5G_BW160M2S_BW160M1S_A_DIFF_8852C_ADDR	= 0x237,
+	EFUSE_INFO_RF_5G_BW80M3S_BW80M2S_A_DIFF_8852C_ADDR	= 0x238,
+	EFUSE_INFO_RF_5G_BW160M3S_BW160M2S_A_DIFF_8852C_ADDR	= 0x238,
+	EFUSE_INFO_RF_5G_BW80M4S_BW80M3S_A_DIFF_8852C_ADDR	= 0x239,
+	EFUSE_INFO_RF_5G_BW160M4S_BW160M3S_A_DIFF_8852C_ADDR	= 0x239,
+	EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_1_8852C_ADDR	= 0x23a,
+	EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_2_8852C_ADDR	= 0x23b,
+	EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_3_8852C_ADDR	= 0x23c,
+	EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_4_8852C_ADDR	= 0x23d,
+	EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_5_8852C_ADDR	= 0x23e,
+	EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_6_8852C_ADDR	= 0x23f,
+	EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_1_8852C_ADDR	= 0x240,
+	EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_2_8852C_ADDR	= 0x241,
+	EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_3_8852C_ADDR	= 0x242,
+	EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_4_8852C_ADDR	= 0x243,
+	EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_5_8852C_ADDR	= 0x244,
+	EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_1_8852C_ADDR	= 0x24c,
+	EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_2_8852C_ADDR	= 0x24d,
+	EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_3_8852C_ADDR	= 0x24e,
+	EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_4_8852C_ADDR	= 0x24f,
+	EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_5_8852C_ADDR	= 0x250,
+	EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_6_8852C_ADDR	= 0x251,
+	EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_7_8852C_ADDR	= 0x252,
+	EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_8_8852C_ADDR	= 0x253,
+	EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_9_8852C_ADDR	= 0x254,
+	EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_10_8852C_ADDR	= 0x255,
+	EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_11_8852C_ADDR	= 0x256,
+	EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_12_8852C_ADDR	= 0x257,
+	EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_13_8852C_ADDR	= 0x258,
+	EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_14_8852C_ADDR	= 0x259,
+	EFUSE_INFO_RF_5G_BW20M1S_BW40M1S_B_DIFF_8852C_ADDR	= 0x25a,
+	EFUSE_INFO_RF_5G_OFDM1T_BW40M1S_B_DIFF_8852C_ADDR	= 0x25a,
+	EFUSE_INFO_RF_5G_BW40M2S_BW40M1S_B_DIFF_8852C_ADDR	= 0x25b,
+	EFUSE_INFO_RF_5G_BW20M2S_BW20M1S_B_DIFF_8852C_ADDR	= 0x25b,
+	EFUSE_INFO_RF_5G_BW40M3S_BW40M2S_B_DIFF_8852C_ADDR	= 0x25c,
+	EFUSE_INFO_RF_5G_BW20M3S_BW20M2S_B_DIFF_8852C_ADDR	= 0x25c,
+	EFUSE_INFO_RF_5G_BW40M4S_BW40M3S_B_DIFF_8852C_ADDR	= 0x25d,
+	EFUSE_INFO_RF_5G_BW20M4S_BW20M3S_B_DIFF_8852C_ADDR	= 0x25d,
+	EFUSE_INFO_RF_5G_OFDM2T_OFDM1T_B_DIFF_8852C_ADDR	= 0x25e,
+	EFUSE_INFO_RF_5G_OFDM3T_OFDM2T_B_DIFF_8852C_ADDR	= 0x25e,
+	EFUSE_INFO_RF_5G_OFDM4T_OFDM3T_B_DIFF_8852C_ADDR	= 0x25f,
+	EFUSE_INFO_RF_5G_BW80M1S_BW40M1S_B_DIFF_8852C_ADDR	= 0x260,
+	EFUSE_INFO_RF_5G_BW160M1S_BW80M1S_B_DIFF_8852C_ADDR	= 0x260,
+	EFUSE_INFO_RF_5G_BW80M2S_BW80M1S_B_DIFF_8852C_ADDR	= 0x261,
+	EFUSE_INFO_RF_5G_BW160M2S_BW160M1S_B_DIFF_8852C_ADDR	= 0x261,
+	EFUSE_INFO_RF_5G_BW80M3S_BW80M2S_B_DIFF_8852C_ADDR	= 0x262,
+	EFUSE_INFO_RF_5G_BW160M3S_BW160M2S_B_DIFF_8852C_ADDR	= 0x262,
+	EFUSE_INFO_RF_5G_BW80M4S_BW80M3S_B_DIFF_8852C_ADDR	= 0x263,
+	EFUSE_INFO_RF_5G_BW160M4S_BW160M3S_B_DIFF_8852C_ADDR	= 0x263,
+	EFUSE_INFO_RF_RX_GAIN_K_A_2G_CCK_8852C_ADDR	= 0x2d6,
+	EFUSE_INFO_RF_RX_GAIN_K_A_2G_OFMD_8852C_ADDR	= 0x2d4,
+	EFUSE_INFO_RF_RX_GAIN_K_A_5GL_8852C_ADDR	= 0x2d8,
+	EFUSE_INFO_RF_RX_GAIN_K_A_5GM_8852C_ADDR	= 0x2da,
+	EFUSE_INFO_RF_RX_GAIN_K_A_5GH_8852C_ADDR	= 0x2dc,
+	EFUSE_INFO_RF_5G_BW160M_BW40M_DIFF_8852C_ADDR		= 0x2e8,
+	EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_1_8852C_ADDR	= 0x300,
+	EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_2_8852C_ADDR	= 0x301,
+	EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_3_8852C_ADDR	= 0x302,
+	EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_4_8852C_ADDR	= 0x303,
+	EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_5_8852C_ADDR	= 0x304,
+	EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_6_8852C_ADDR	= 0x305,
+	EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_7_8852C_ADDR	= 0x306,
+	EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_8_8852C_ADDR	= 0x307,
+	EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_9_8852C_ADDR	= 0x308,
+	EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_10_8852C_ADDR	= 0x309,
+	EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_11_8852C_ADDR	= 0x30a,
+	EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_12_8852C_ADDR	= 0x30b,
+	EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_13_8852C_ADDR	= 0x30c,
+	EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_14_8852C_ADDR	= 0x30d,
+	EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_15_8852C_ADDR	= 0x30e,
+	EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_16_8852C_ADDR	= 0x30f,
+	EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_17_8852C_ADDR	= 0x310,
+	EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_18_8852C_ADDR	= 0x311,
+	EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_19_8852C_ADDR	= 0x312,
+	EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_20_8852C_ADDR	= 0x313,
+	EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_21_8852C_ADDR	= 0x314,
+	EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_22_8852C_ADDR	= 0x315,
+	EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_23_8852C_ADDR	= 0x316,
+	EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_24_8852C_ADDR	= 0x317,
+	EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_25_8852C_ADDR	= 0x318,
+	EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_26_8852C_ADDR	= 0x319,
+	EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_27_8852C_ADDR	= 0x31a,
+	EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_28_8852C_ADDR	= 0x31b,
+	EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_29_8852C_ADDR	= 0x31c,
+	EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_30_8852C_ADDR	= 0x31d,
+	EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_31_8852C_ADDR	= 0x31e,
+	EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_32_8852C_ADDR	= 0x31f,
+	EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_1_8852C_ADDR	= 0x32a,
+	EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_2_8852C_ADDR	= 0x32b,
+	EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_3_8852C_ADDR	= 0x32c,
+	EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_4_8852C_ADDR	= 0x32d,
+	EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_5_8852C_ADDR	= 0x32e,
+	EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_6_8852C_ADDR	= 0x32f,
+	EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_7_8852C_ADDR	= 0x330,
+	EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_8_8852C_ADDR	= 0x331,
+	EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_9_8852C_ADDR	= 0x332,
+	EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_10_8852C_ADDR	= 0x333,
+	EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_11_8852C_ADDR	= 0x334,
+	EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_12_8852C_ADDR	= 0x335,
+	EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_13_8852C_ADDR	= 0x336,
+	EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_14_8852C_ADDR	= 0x337,
+	EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_15_8852C_ADDR	= 0x338,
+	EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_16_8852C_ADDR	= 0x339,
+	EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_17_8852C_ADDR	= 0x33a,
+	EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_18_8852C_ADDR	= 0x33b,
+	EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_19_8852C_ADDR	= 0x33c,
+	EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_20_8852C_ADDR	= 0x33d,
+	EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_21_8852C_ADDR	= 0x33e,
+	EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_22_8852C_ADDR	= 0x33f,
+	EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_23_8852C_ADDR	= 0x340,
+	EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_24_8852C_ADDR	= 0x341,
+	EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_25_8852C_ADDR	= 0x342,
+	EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_26_8852C_ADDR	= 0x343,
+	EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_27_8852C_ADDR	= 0x344,
+	EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_28_8852C_ADDR	= 0x345,
+	EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_29_8852C_ADDR	= 0x346,
+	EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_30_8852C_ADDR	= 0x347,
+	EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_31_8852C_ADDR	= 0x348,
+	EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_32_8852C_ADDR	= 0x349,
+	EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_1_8852C_ADDR	= 0x354,
+	EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_2_8852C_ADDR	= 0x355,
+	EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_3_8852C_ADDR	= 0x356,
+	EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_4_8852C_ADDR	= 0x357,
+	EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_5_8852C_ADDR	= 0x358,
+	EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_6_8852C_ADDR	= 0x359,
+	EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_7_8852C_ADDR	= 0x35a,
+	EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_8_8852C_ADDR	= 0x35b,
+	EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_9_8852C_ADDR	= 0x35c,
+	EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_10_8852C_ADDR	= 0x35d,
+	EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_11_8852C_ADDR	= 0x35e,
+	EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_12_8852C_ADDR	= 0x35f,
+	EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_13_8852C_ADDR	= 0x360,
+	EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_14_8852C_ADDR	= 0x361,
+	EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_15_8852C_ADDR	= 0x362,
+	EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_16_8852C_ADDR	= 0x363,
+	EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_17_8852C_ADDR	= 0x364,
+	EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_18_8852C_ADDR	= 0x365,
+	EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_19_8852C_ADDR	= 0x366,
+	EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_20_8852C_ADDR	= 0x367,
+	EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_21_8852C_ADDR	= 0x368,
+	EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_22_8852C_ADDR	= 0x369,
+	EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_23_8852C_ADDR	= 0x36a,
+	EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_24_8852C_ADDR	= 0x36b,
+	EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_25_8852C_ADDR	= 0x36c,
+	EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_26_8852C_ADDR	= 0x36d,
+	EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_27_8852C_ADDR	= 0x36e,
+	EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_28_8852C_ADDR	= 0x36f,
+	EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_29_8852C_ADDR	= 0x370,
+	EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_30_8852C_ADDR	= 0x371,
+	EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_31_8852C_ADDR	= 0x372,
+	EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_32_8852C_ADDR	= 0x373,
+	EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_1_8852C_ADDR	= 0x37e,
+	EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_2_8852C_ADDR	= 0x37f,
+	EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_3_8852C_ADDR	= 0x380,
+	EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_4_8852C_ADDR	= 0x381,
+	EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_5_8852C_ADDR	= 0x382,
+	EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_6_8852C_ADDR	= 0x383,
+	EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_7_8852C_ADDR	= 0x384,
+	EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_8_8852C_ADDR	= 0x385,
+	EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_9_8852C_ADDR	= 0x386,
+	EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_10_8852C_ADDR	= 0x387,
+	EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_11_8852C_ADDR	= 0x388,
+	EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_12_8852C_ADDR	= 0x389,
+	EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_13_8852C_ADDR	= 0x38a,
+	EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_14_8852C_ADDR	= 0x38b,
+	EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_15_8852C_ADDR	= 0x38c,
+	EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_16_8852C_ADDR	= 0x38d,
+	EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_17_8852C_ADDR	= 0x38e,
+	EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_18_8852C_ADDR	= 0x38f,
+	EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_19_8852C_ADDR	= 0x390,
+	EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_20_8852C_ADDR	= 0x391,
+	EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_21_8852C_ADDR	= 0x392,
+	EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_22_8852C_ADDR	= 0x393,
+	EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_23_8852C_ADDR	= 0x394,
+	EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_24_8852C_ADDR	= 0x395,
+	EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_25_8852C_ADDR	= 0x396,
+	EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_26_8852C_ADDR	= 0x397,
+	EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_27_8852C_ADDR	= 0x398,
+	EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_28_8852C_ADDR	= 0x399,
+	EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_29_8852C_ADDR	= 0x39a,
+	EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_30_8852C_ADDR	= 0x39b,
+	EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_31_8852C_ADDR	= 0x39c,
+	EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_32_8852C_ADDR	= 0x39d,
+	EFUSE_INFO_RF_RX_GAIN_K_A_6GL1_8852C_ADDR	= 0x3a8,
+	EFUSE_INFO_RF_RX_GAIN_K_A_6GL2_8852C_ADDR	= 0x3aa,
+	EFUSE_INFO_RF_RX_GAIN_K_A_6GL3_8852C_ADDR	= 0x3ac,
+	EFUSE_INFO_RF_RX_GAIN_K_A_6GM1_8852C_ADDR	= 0x3ae,
+	EFUSE_INFO_RF_RX_GAIN_K_A_6GM2_8852C_ADDR	= 0x3b0,
+	EFUSE_INFO_RF_RX_GAIN_K_A_6GM3_8852C_ADDR	= 0x3b2,
+	EFUSE_INFO_RF_RX_GAIN_K_A_6GH1_8852C_ADDR	= 0x3b4,
+	EFUSE_INFO_RF_RX_GAIN_K_A_6GH2_8852C_ADDR	= 0x3b6,
+	EFUSE_INFO_RF_6G_BW160M_BW40M_DIFF_8852C_ADDR		= 0x3ca
+};
+
+enum halrf_efsue_default_value_8852c {
+	EFUSE_INFO_RF_RFE_8852C_VALUE		= 0x1,
+	EFUSE_INFO_RF_CHAN_PLAN_8852C_VALUE	= 0x7f,
+	EFUSE_INFO_RF_COUNTRY_CODE_8852C_VALUE	= 0xffff,
+	EFUSE_INFO_RF_XTAL_8852C_VALUE		= 0x3f,
+	EFUSE_INFO_RF_THERMAL_A_8852C_VALUE	= 0x22,
+	EFUSE_INFO_RF_THERMAL_B_8852C_VALUE	= 0x22,
+	EFUSE_INFO_RF_TSSI_DE_8852C_VALUE	= 0x0,
+	EFUSE_INFO_RF_RX_GAIN_K_8852C_VALUE	= 0xff,
+	EFUSE_INFO_RF_BOARD_OPTION_8852C_VALUE	= 0x1,
+	EFUSE_INFO_RF_5G_DIFF_8852C_VALUE_1		= 0x0,
+	EFUSE_INFO_RF_5G_DIFF_8852C_VALUE_2		= 0xf,
+	EFUSE_INFO_RF_BW_DIFF_8852C_VALUE		= 0x0,
+};
+
+bool halrf_get_efuse_info_8852c(struct rf_info *rf, u8 *efuse_map,
+		       enum rtw_efuse_info id, void *value, u32 length,
+		       u8 autoload_status);
+
+#endif	/*RF_8852C_SUPPORT*/
+#endif	/*_HALRF_EFUSE_8852C_H_*/
+

3rd/devourer/hal/halrf/g6/vendor/halrf_8852c/halrf_hwimg_8852c.h

@@ -0,0 +1,91 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2020  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+#ifndef _HALRF_HW_IMG_8852C_H_
+#define _HALRF_HW_IMG_8852C_H_
+#ifdef RF_8852C_SUPPORT
+
+#define DONT_CARE_8852C	0xff
+
+#define IF_8852C	0x8
+#define ELSE_IF_8852C	0x9
+#define ELSE_8852C	0xa
+#define END_8852C	0xb
+#define CHK_8852C	0x4
+
+#if 0
+#define RADIO_TO_FW_PAGE_SIZE 6
+#define RADIO_TO_FW_DATA_SIZE 500
+
+#define FWCMD_H2C_RADIO_A_INIT_0 0x0
+#define FWCMD_H2C_RADIO_A_INIT_1 0x1
+#define FWCMD_H2C_RADIO_A_INIT_2 0x2
+#define FWCMD_H2C_RADIO_A_INIT_3 0x3
+#define FWCMD_H2C_RADIO_A_INIT_4 0x4
+#define FWCMD_H2C_RADIO_A_INIT_5 0x5
+#define FWCMD_H2C_RADIO_A_INIT_6 0x6
+#define FWCMD_H2C_RADIO_A_INIT_7 0x7
+#define FWCMD_H2C_RADIO_A_INIT_8 0x8
+#define FWCMD_H2C_RADIO_A_INIT_9 0x9
+
+#define FWCMD_H2C_RADIO_B_INIT_0 0x0
+#define FWCMD_H2C_RADIO_B_INIT_1 0x1
+#define FWCMD_H2C_RADIO_B_INIT_2 0x2
+#define FWCMD_H2C_RADIO_B_INIT_3 0x3
+#define FWCMD_H2C_RADIO_B_INIT_4 0x4
+#define FWCMD_H2C_RADIO_B_INIT_5 0x5
+#define FWCMD_H2C_RADIO_B_INIT_6 0x6
+#define FWCMD_H2C_RADIO_B_INIT_7 0x7
+#define FWCMD_H2C_RADIO_B_INIT_8 0x8
+#define FWCMD_H2C_RADIO_B_INIT_9 0x9
+
+struct halrf_radio_info {
+	u32 write_times_a;
+	u32 write_times_b;
+	u32 radio_a_parameter[RADIO_TO_FW_PAGE_SIZE][RADIO_TO_FW_DATA_SIZE];
+	u32 radio_b_parameter[RADIO_TO_FW_PAGE_SIZE][RADIO_TO_FW_DATA_SIZE];
+};
+
+#endif
+void halrf_config_8852c_nctl_reg(struct rf_info *rf);
+void halrf_config_8852c_radio_a_reg(struct rf_info *rf, enum phl_phy_idx phy);
+void halrf_config_8852c_radio_b_reg(struct rf_info *rf, enum phl_phy_idx phy);
+void halrf_config_8852c_store_power_by_rate(struct rf_info *rf, enum phl_phy_idx phy);
+void halrf_config_8852c_store_power_limit(struct rf_info *rf, enum phl_phy_idx phy);
+void halrf_config_8852c_store_power_limit_6g(struct rf_info *rf, enum phl_phy_idx phy);
+void halrf_config_8852c_store_power_limit_ru(struct rf_info *rf, enum phl_phy_idx phy);
+void halrf_config_8852c_store_power_limit_ru_6g(struct rf_info *rf, enum phl_phy_idx phy);
+void halrf_config_8852c_store_pwr_track(struct rf_info *rf, enum phl_phy_idx phy);
+void halrf_config_8852c_store_xtal_track(struct rf_info *rf, enum phl_phy_idx phy);
+
+u32 halrf_get_8852c_nctl_reg_ver(void);
+u32 halrf_get_8852c_radio_reg_ver(void);
+
+void halrf_config_8852c_radio_to_fw(struct rf_info *rf);
+
+void halrf_cfg_8852c_radio_b_w_bt_status(struct rf_info *rf, bool bt_connect);
+
+
+#endif
+#endif /*  _HALRF_HW_IMG_8852C_H_ */

3rd/devourer/hal/halrf/g6/vendor/halrf_8852c/halrf_hwimg_raw_data_w_bt_8852c.h

@@ -0,0 +1,267 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+#ifndef _HALRF_HWIMG_RAW_DATA_W_BT_8852C_H_
+#define _HALRF_HWIMG_RAW_DATA_W_BT_8852C_H_
+
+#if 1
+const u32 array_mp_8852c_radiob_with_bt_con[] = {
+		//LUT_RXG_GAIN 2022/08/29
+		//BT connect, 
+		0xEF, 0x04000,
+		0x33, 0x00007,//BT connect HG 20220829
+		0x3E, 0x00000, 
+		0x3F, 0xA0700, 
+		0x33, 0x00006,//BT connect HG 20220829
+		0x3E, 0x00000, 
+		0x3F, 0xA0700, 
+		0x33, 0x00005, 
+		0x3E, 0x00000, 
+		0x3F, 0x10500, 
+		0x33, 0x00004,// modify 20220315, 
+		0x3E, 0x00000, 
+		0x3F, 0x00400, 
+		0x33, 0x00003,// modify b-cut, 
+		0x3E, 0x00000, 
+		0x3F, 0x28B00, 
+		0x33, 0x00002,// modify b-cut, 
+		0x3E, 0x00000, 
+		0x3F, 0x9AB00, 
+		0x33, 0x00001,// modify 20220315, 
+		0x3E, 0x00000, 
+		0x3F, 0x01A00, 
+		0x33, 0x00000,// modify 20220315, 
+		0x3E, 0x00000, 
+		0x3F, 0x02900, 
+		//LUT_RXG_GAIN COEX  2022/08/29
+		//BT connect, 
+		//BTS0 TX when WLS1 RX, 
+		//LNA1 change Table by POW_PA_BTS1
+		0x33, 0x0000F,//BT connect HG 20220829
+		0x3E, 0x00000, 
+		0x3F, 0xA0700, 
+		0x33, 0x0000E,//BT connect HG 20220829
+		0x3E, 0x00000, 
+		0x3F, 0xA0700,
+		0x33, 0x0000D, 
+		0x3E, 0x00000, 
+		0x3F, 0x10500, 
+		0x33, 0x0000C,// modify 20220315, 
+		0x3E, 0x00000, 
+		0x3F, 0x00400, 
+		0x33, 0x0000B,// modify b-cut, 
+		0x3E, 0x00000, 
+		0x3F, 0x28B00, 
+		0x33, 0x0000A,// modify b-cut, 
+		0x3E, 0x00000, 
+		0x3F, 0x9AB00, 
+		0x33, 0x00009,// modify 20220315, 
+		0x3E, 0x00000, 
+		0x3F, 0x01A00, 
+		0x33, 0x00008,// modify 20220315, 
+		0x3E, 0x00000, 
+		0x3F, 0x02900, 
+		//LUT_RXG_GAIN 2R  2022/08/29
+		//BT connect, 
+		//LNA1 change Table by POW_LNA2_BTS1
+		0x33, 0x00017,//BT connect HG 20220829
+		0x3E, 0x00000, 
+		0x3F, 0xA0700, 
+		0x33, 0x00016,//BT connect HG 20220829
+		0x3E, 0x00000, 
+		0x3F, 0xA0700,
+		0x33, 0x00015, 
+		0x3E, 0x00000, 
+		0x3F, 0x10500, 
+		0x33, 0x00014,// modify 20220315, 
+		0x3E, 0x00000, 
+		0x3F, 0x00400, 
+		0x33, 0x00013,// modify b-cut, 
+		0x3E, 0x00000, 
+		0x3F, 0x28B00, 
+		0x33, 0x00012,// modify b-cut, 
+		0x3E, 0x00000, 
+		0x3F, 0x9AB00, 
+		0x33, 0x00011,// modify 20220315, 
+		0x3E, 0x00000, 
+		0x3F, 0x01A00, 
+		0x33, 0x00010,// modify 20220315, 
+		0x3E, 0x00000, 
+		0x3F, 0x02900, 
+		0xEF, 0x00000, 
+		//LUT_RXG_BIAS  2022/08/29
+		//BT connect, , 
+		0xEE,  0x00010,
+		0x33,  0x00000,// normal RX idle BS=2
+		0x3F,  0x00002,
+		0x33,  0x00001,// normal RX CCK BS=2
+		0x3F,  0x00002,
+		0x33,  0x00002,// normal RX OFDM BS=2
+		0x3F,  0x00002,
+		0x33,  0x00006,// LNA5~0 normal HG BS=3
+		0x3F, 0x00003,
+		0x33, 0x00007,// LNA5~0 BCN HG BS=3
+		0x3F,  0x00003,
+		0x33,  0x00008,// LNA on RFMODE=3.6.7.8 BS=1
+		0x3F,  0x00001,
+		0x33, 0x0000E,// LNA5~0 normal LG BS=3
+		0x3F,  0x00003,
+		0x33, 0x0000F,// LNA5~0 BCN LG,BS=3
+		0x3F,  0x00003,
+		0xEE,  0x00000, 
+		//TIA gain modify LUT , , 
+		//BT connect, 
+		0xEF, 0x01000, 
+		0x33, 0x00000, 
+		0x3F, 0x00015, //LNA2 -8 +TIA22
+		0x33, 0x00001, 
+		0x3F, 0x00005, //LNA2 -8 +TIA28
+		0x33, 0x00002, 
+		0x3F, 0x00015, //LNA2 -8 +TIA22
+		0x33, 0x00003, 
+		0x3F, 0x00005, //LNA2 -8 +TIA28
+		0xEF, 0x00000, 
+};
+
+const u32 array_mp_8852c_radiob_with_bt_discon[] = {
+
+		//LUT_RXG_GAIN 2022/08/29
+		//BT disconnect,
+		0xEF, 0x04000, 
+		0x33, 0x00007,//BT disconnect HG 20220829
+		0x3E, 0x00000, 
+		0x3F, 0x00700,
+		0x33, 0x00006,//BT disconnect, HG 20220829
+		0x3E, 0x00000, 
+		0x3F, 0x00700, 
+		0x33, 0x00005, 
+		0x3E, 0x00000, 
+		0x3F, 0x10500, 
+		0x33, 0x00004,// modify 20220315, 
+		0x3E, 0x00000, 
+		0x3F, 0x00400, 
+		0x33, 0x00003,// modify b-cut, 
+		0x3E, 0x00000, 
+		0x3F, 0x28B00, 
+		0x33, 0x00002,// modify b-cut, 
+		0x3E, 0x00000, 
+		0x3F, 0x9AB00, 
+		0x33, 0x00001,// modify 20220315, 
+		0x3E, 0x00000, 
+		0x3F, 0x01A00, 
+		0x33, 0x00000,// modify 20220315, 
+		0x3E, 0x00000, 
+		0x3F, 0x02900, 
+		//LUT_RXG_GAIN COEX  2022/08/29
+		//BT disconnect, 
+		//BTS0 TX when WLS1 RX, 
+		//LNA1 change Table by POW_PA_BTS1
+		0x33, 0x0000F,//BT disconnect, HG 20220829
+		0x3E, 0x00000, 
+		0x3F, 0x00700, 
+		0x33, 0x0000E, //BT disconnect HG 20220829
+		0x3E, 0x00000, 
+		0x3F, 0x00700,
+		0x33, 0x0000D, 
+		0x3E, 0x00000, 
+		0x3F, 0x10500, 
+		0x33, 0x0000C,// modify 20220315, 
+		0x3E, 0x00000, 
+		0x3F, 0x00400, 
+		0x33, 0x0000B,// modify b-cut, 
+		0x3E, 0x00000, 
+		0x3F, 0x28B00, 
+		0x33, 0x0000A,// modify b-cut, 
+		0x3E, 0x00000, 
+		0x3F, 0x9AB00, 
+		0x33, 0x00009,// modify 20220315, 
+		0x3E, 0x00000, 
+		0x3F, 0x01A00, 
+		0x33, 0x00008,// modify 20220315, 
+		0x3E, 0x00000, 
+		0x3F, 0x02900, 
+		//LUT_RXG_GAIN 2R  2022/08/09
+		//BT disconnect, 
+		//LNA1 change Table by POW_LNA2_BTS1
+		0x33, 0x00017, //BT disconnect HG 20220809
+		0x3E, 0x00000, 
+		0x3F, 0x00700, 
+		0x33, 0x00016, //BT disconnect HG 20220809, 
+		0x3E, 0x00000, 
+		0x3F, 0x00700, 
+		0x33, 0x00015, 
+		0x3E, 0x00000, 
+		0x3F, 0x10500, 
+		0x33, 0x00014,// modify 20220315, 
+		0x3E, 0x00000, 
+		0x3F, 0x00400, 
+		0x33, 0x00013,// modify b-cut, 
+		0x3E, 0x00000, 
+		0x3F, 0x28B00, 
+		0x33, 0x00012,// modify b-cut, 
+		0x3E, 0x00000, 
+		0x3F, 0x9AB00, 
+		0x33, 0x00011,// modify 20220315, 
+		0x3E, 0x00000, 
+		0x3F, 0x01A00, 
+		0x33, 0x00010,// modify 20220315, 
+		0x3E, 0x00000, 
+		0x3F, 0x02900, 
+		0xEF, 0x00000, 
+		//LUT_RXG_BIAS  2022/08/29
+		//BT disconnect, , 
+		0xEE, 0x00010,
+		0x33, 0x00000,// normal RX idle BS=3
+		0x3F,  0x00003,
+		0x33,  0x00001,// normal RX CCK BS=3
+		0x3F,  0x00003,
+		0x33,  0x00002,// normal RX OFDM BS=3
+		0x3F,  0x00003,
+		0x33, 0x00006,// LNA5~0 normal HG BS=3
+		0x3F,  0x00003,
+		0x33, 0x00007,// LNA5~0 BCN HG BS=3
+		0x3F, 0x00003,
+		0x33,  0x00008,// LNA on RFMODE=3.6.7.8 BS=1
+		0x3F,  0x00001,
+		0x33,  0x0000E,// LNA5~0 normal LG BS=3
+		0x3F,  0x00003,
+		0x33,  0x0000F,// LNA5~0 BCN LG,BS=3
+		0x3F,  0x00003,
+		0xEE,  0x00000, 
+		//TIA gain modify LUT 
+		//BT disconnect, 
+		0xEF, 0x01000, 
+		0x33, 0x00000, 
+		0x3F, 0x00015, //LNA2 -8 +TIA22
+		0x33, 0x00001, 
+		0x3F, 0x00017, //LNA2 0 +TIA22
+		0x33, 0x00002, 
+		0x3F, 0x00015, //LNA2 -8 +TIA22
+		0x33, 0x00003, 
+		0x3F, 0x00017, //LNA2 0 +TIA22
+		0xEF, 0x00000, 
+};
+#endif
+
+#endif /* _HALRF_HWIMG_RAW_DATA_W_BT_8852C_H */

3rd/devourer/hal/halrf/g6/vendor/halrf_8852c/halrf_iqk_8852c.h

@@ -0,0 +1,106 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2020  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+#ifndef __HALRF_IQK_8852CH__
+#define __HALRF_IQK_8852CH__
+#ifdef RF_8852C_SUPPORT
+
+#define iqk_version_8852c 0x25
+#define ss_8852c 2
+#define mac_reg_num_8852c 2
+#define bb_reg_num_8852c 1
+#define rf_reg_num_8852c 6
+#define iqk_delay_8852c 1
+#define iqk_step_8852c 2
+#define rxk_step_8852c 4
+#define path_baseaddr 0x8
+#define txagck 0
+#define lok 1
+#define txk 2
+#define rxk 3
+#define IQK_THR_ReK 8
+
+
+void halrf_iqk_8852c(struct rf_info *rf, enum phl_phy_idx phy_idx, bool force);
+
+//cv b
+void iqk_init_8852c(struct rf_info *rf);
+void halrf_iqk_8852c(struct rf_info *rf, enum phl_phy_idx phy_idx, bool force);
+void halrf_doiqk_8852c(struct rf_info *rf, bool force,
+			enum phl_phy_idx phy_idx, u8 path);
+void iqk_get_ch_info_8852c(struct rf_info *rf, enum phl_phy_idx phy, u8 path);
+bool iqk_mcc_page_sel_8852c(struct rf_info *rf, enum phl_phy_idx phy, u8 path);
+void iqk_macbb_setting_8852c(struct rf_info *rf, enum phl_phy_idx phy_idx, u8 path);
+void iqk_preset_8852c(struct rf_info *rf, u8 path);
+void iqk_start_iqk_8852c(struct rf_info *rf, enum phl_phy_idx phy_idx,
+			  u8 path);
+void iqk_restore_8852c(struct rf_info *rf, u8 path);
+void iqk_afebb_restore_8852c(struct rf_info *rf, enum phl_phy_idx phy_idx, u8 path);
+void halrf_iqk_reload_8852c(struct rf_info *rf, u8 path);
+void halrf_nbiqk_enable_8852c(struct rf_info *rf, bool nbiqk_en);
+void halrf_iqk_toneleakage_8852c(struct rf_info *rf, u8 path);
+void halrf_iqk_sram_enable_8852c(struct rf_info *rf, bool iqk_sram_en);
+void halrf_iqk_xym_enable_8852c(struct rf_info *rf, bool iqk_xym_en);
+void halrf_iqk_fft_enable_8852c(struct rf_info *rf, bool iqk_fft_en);
+void halrf_iqk_cfir_enable_8852c(struct rf_info *rf, bool iqk_cfir_en);
+void halrf_iqk_onoff_8852c(struct rf_info *rf, bool is_enable);
+void halrf_iqk_lok_bypass_8852c(struct rf_info *rf, u8 path);
+void halrf_iqk_rx_bypass_8852c(struct rf_info *rf, u8 path);
+void halrf_iqk_tx_bypass_8852c(struct rf_info *rf, u8 path);
+
+void iqk_backup_mac_bb_8852c(struct rf_info *rf, u8 path,
+			     u32 backup_mac[mac_reg_num_8852c],
+			     u32 backup_bb[bb_reg_num_8852c],
+			     u32 backup_mac_reg[mac_reg_num_8852c],
+			     u32 backup_bb_reg[bb_reg_num_8852c]);
+void iqk_backup_rf_8852c(struct rf_info *rf, u8 path,
+			 u32 backup_rf[][rf_reg_num_8852c],
+			 u32 backup_rf_reg[][rf_reg_num_8852c]);
+void iqk_restore_mac_bb_8852c(struct rf_info *rf, u8 path,
+			      u32 backup_mac[mac_reg_num_8852c],
+			      u32 backup_bb[bb_reg_num_8852c],
+			      u32 backup_mac_reg[mac_reg_num_8852c],
+			      u32 backup_bb_reg[bb_reg_num_8852c]);
+void iqk_restore_rf_8852c(struct rf_info *rf, u8 path,
+			  u32 backup_rf[][rf_reg_num_8852c],
+			  u32 backup_rf_reg[][rf_reg_num_8852c]);
+
+void halrf_iqk_track_8852c(struct rf_info *rf);
+
+bool halrf_iqk_get_ther_rek_8852c(struct rf_info *rf );
+void halrf_iqk_dbcc_8852c(struct rf_info *rf, u8 path);
+u8 halrf_iqk_get_mcc_ch0_8852c(struct rf_info *rf );
+u8 halrf_iqk_get_mcc_ch1_8852c(struct rf_info *rf );
+bool halrf_check_fwiqk_done_8852c(struct rf_info *rf);
+void iqk_set_info_8852c(struct rf_info *rf, enum phl_phy_idx phy_idx, u8 path);
+void halrf_enable_fw_iqk_8852c(struct rf_info *rf, bool is_fw_iqk);
+u8 halrf_get_iqk_times_8852c(struct rf_info *rf) ;
+u32 halrf_get_iqk_ver_8852c(void);
+u8 halrf_iqk_get_rxevm_8852c(struct rf_info *rf);
+u32 halrf_iqk_get_rximr_8852c(struct rf_info *rf, u8 path, u32 idx);
+
+
+#endif
+#endif /*  __HALRF_IQK_8852CH__ */
+

3rd/devourer/hal/halrf/g6/vendor/halrf_8852c/halrf_kfree_8852c.c

@@ -0,0 +1,449 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2019 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#include "../halrf_precomp.h"
+
+#ifdef RF_8852C_SUPPORT
+
+void _halrf_get_total_efuse_8852c(struct rf_info *rf,
+					enum phl_phy_idx phy)
+{
+	struct halrf_kfree_info *kfree = &rf->kfree_info;
+	u32 i, array_size = sizeof(kfree->efuse_content);
+
+	if (array_size < HIDE_EFUSE_SIZE_8852C) {
+		RF_DBG(rf, DBG_RF_TSSI_TRIM, "======> %s   sizeof(kfree->efuse_content)(0x%x) < HIDE_EFUSE_SIZE_8852C(0x%x)\n",
+			__func__, array_size, HIDE_EFUSE_SIZE_8852C);
+		return;
+	}
+
+	halrf_phy_efuse_get_info(rf, HIDE_EFUSE_START_ADDR_8852C,
+		HIDE_EFUSE_SIZE_8852C, kfree->efuse_content);
+
+	for (i = 0; i < HIDE_EFUSE_SIZE_8852C; i++)
+		RF_DBG(rf, DBG_RF_TSSI_TRIM, "======> %s   efuse_con[0x%x] = 0x%x\n",
+			__func__, i + HIDE_EFUSE_START_ADDR_8852C, kfree->efuse_content[i]);
+}
+
+u8 _halrf_get_1byte_efuse_8852c(struct rf_info *rf, u32 addr, u8 *value)
+{
+	struct halrf_kfree_info *kfree = &rf->kfree_info;
+
+	if (addr < HIDE_EFUSE_START_ADDR_8852C || addr > HIDE_EFUSE_END_ADDR_8852C) {
+		RF_DBG(rf, DBG_RF_TSSI_TRIM, "===> %s addr(0x%x) < 0x%x(Min), > 0x%x(Max) Over Range Return !!!\n",
+			__func__, addr, HIDE_EFUSE_START_ADDR_8852C, HIDE_EFUSE_END_ADDR_8852C);
+		return 0xff;
+	}
+
+	*value = kfree->efuse_content[addr - HIDE_EFUSE_START_ADDR_8852C];
+
+	RF_DBG(rf, DBG_RF_TSSI_TRIM, "===> %s addr(0x%x) = 0x%x\n", __func__, addr, *value);
+
+	return *value;
+}
+
+s8 _halrf_efuse_exchange_8852c(struct rf_info *rf, u8 value, u8 mask)
+{
+	s8 tmp = 0;
+
+	if (mask == LOW_MASK) {
+		tmp = value & 0xf;
+
+		if (tmp & BIT(3))
+			tmp = tmp | 0xf0;
+	} else {
+		tmp = (value & 0xf0) >> 4;
+
+		if (tmp & BIT(3))
+			tmp = tmp | 0xf0;
+	}
+
+	return tmp;
+}
+
+void _halrf_set_thermal_trim_8852c(struct rf_info *rf,
+					enum phl_phy_idx phy)
+{
+	struct halrf_kfree_info *kfree = &rf->kfree_info;
+	u32 pc_type = ((rf->phl_com->id.id) >> 8) & 0xff;
+	u8 thermal_a = 0xff, thermal_b = 0xff, tmp = 0;
+
+	RF_DBG(rf, DBG_RF_THER_TRIM, "======> %s   phy=%d\n", __func__, phy);
+
+	if (!(rf->support_ability & HAL_RF_THER_TRIM)) {
+		RF_DBG(rf, DBG_RF_THER_TRIM, "<== %s phy=%d support_ability=0x%x Ther Trim Off!!!\n",
+			__func__, phy, rf->support_ability);
+		return;
+	}
+
+	tmp = _halrf_get_1byte_efuse_8852c(rf, THERMAL_TRIM_HIDE_EFUSE_A_8852C, &thermal_a);
+
+	tmp = _halrf_get_1byte_efuse_8852c(rf, THERMAL_TRIM_HIDE_EFUSE_B_8852C, &thermal_b);
+
+	RF_DBG(rf, DBG_RF_THER_TRIM, "efuse Ther_A=0x%x Ther_B=0x%x\n",
+		thermal_a, thermal_b);
+
+	if (thermal_a == 0xff && thermal_b == 0xff) {
+		RF_DBG(rf, DBG_RF_THER_TRIM, "Ther_A, Ther_B=0xff no PG Return!!!\n");
+		return; 
+	}
+
+	if (thermal_a & BIT(0))
+		kfree->thermal_trim[RF_PATH_A] = (thermal_a & 0x1f) >> 1;
+	else
+		kfree->thermal_trim[RF_PATH_A] = ((thermal_a & 0x1f) >> 1) * -1;
+
+	if (thermal_b & BIT(0))
+		kfree->thermal_trim[RF_PATH_B] = (thermal_b & 0x1f) >> 1;
+	else
+		kfree->thermal_trim[RF_PATH_B] = ((thermal_b & 0x1f) >> 1) * -1;
+
+	RF_DBG(rf, DBG_RF_THER_TRIM, "Real offset Ther_A=%d Ther_B=%d\n",
+		kfree->thermal_trim[RF_PATH_A], kfree->thermal_trim[RF_PATH_B]);
+
+	if (pc_type == 2) { /*pc_type == 2 Asus PC*/
+		if (kfree->thermal_trim[RF_PATH_A] > 2) {
+			kfree->thermal_trim_protect[RF_PATH_A] = true;
+			thermal_a = 0;
+		} else
+			kfree->thermal_trim_protect[RF_PATH_A] = false;
+
+		if (kfree->thermal_trim[RF_PATH_B] > 2) {
+			kfree->thermal_trim_protect[RF_PATH_B] = true;
+			thermal_b = 0;
+		} else
+			kfree->thermal_trim_protect[RF_PATH_B] = false;
+	}
+
+	thermal_a = thermal_a & 0xf;
+	thermal_a = ((thermal_a & 0x1) << 3) | (thermal_a >> 1);
+
+	thermal_b = thermal_b & 0xf;
+	thermal_b = ((thermal_b & 0x1) << 3) | (thermal_b >> 1);
+
+	RF_DBG(rf, DBG_RF_THER_TRIM, "After Exchange Ther_A=0x%x Ther_B=0x%x\n",
+		thermal_a, thermal_b);
+
+	halrf_wrf(rf, RF_PATH_A, 0x43, 0x000f0000, thermal_a & 0xf);
+	halrf_wrf(rf, RF_PATH_B, 0x43, 0x000f0000, thermal_b & 0xf);
+}
+
+void _halrf_set_pa_bias_trim_8852c(struct rf_info *rf,
+					enum phl_phy_idx phy)
+{
+	u8 pa_bias_a = 0xff, pa_bias_b = 0xff, tmp = 0;
+	u8 pa_bias_a_2g, pa_bias_b_2g, pa_bias_a_5g, pa_bias_b_5g;
+
+	RF_DBG(rf, DBG_RF_PABIAS_TRIM, "======> %s   phy=%d\n", __func__, phy);
+
+	if (!(rf->support_ability & HAL_RF_PABIAS_TRIM)) {
+		RF_DBG(rf, DBG_RF_PABIAS_TRIM, "<== %s phy=%d support_ability=0x%x PA Bias K Off!!!\n",
+			__func__, phy, rf->support_ability);
+		return;
+	}
+
+	tmp = _halrf_get_1byte_efuse_8852c(rf, PABIAS_TRIM_HIDE_EFUSE_A_8852C, &pa_bias_a);
+
+	tmp = _halrf_get_1byte_efuse_8852c(rf, PABIAS_TRIM_HIDE_EFUSE_B_8852C, &pa_bias_b);
+
+	RF_DBG(rf, DBG_RF_PABIAS_TRIM, "efuse PA_Bias_A=0x%x PA_Bias_B=0x%x\n",
+		pa_bias_a, pa_bias_b);
+
+	if (pa_bias_a == 0xff && pa_bias_b == 0xff) {
+		RF_DBG(rf, DBG_RF_PABIAS_TRIM, "PA_Bias_A, PA_Bias_B=0xff no PG Return!!!\n");
+		return; 
+	}
+
+	pa_bias_a_2g = pa_bias_a & 0xf;
+	pa_bias_a_5g = (pa_bias_a & 0xf0) >> 4;
+
+	pa_bias_b_2g = pa_bias_b & 0xf;
+	pa_bias_b_5g = (pa_bias_b & 0xf0) >> 4;
+
+	RF_DBG(rf, DBG_RF_PABIAS_TRIM, "After Calculate PA_Bias_A_2G=0x%x PA_Bias_A_5G=0x%x\n",
+		pa_bias_a_2g, pa_bias_a_5g);
+
+	RF_DBG(rf, DBG_RF_PABIAS_TRIM, "After Calculate PA_Bias_B_2G=0x%x PA_Bias_B_5G=0x%x\n",
+		pa_bias_b_2g, pa_bias_b_5g);
+
+	halrf_wrf(rf, RF_PATH_A, 0x60, 0x0000f000, pa_bias_a_2g);
+	halrf_wrf(rf, RF_PATH_A, 0x60, 0x000f0000, pa_bias_a_5g);
+
+	halrf_wrf(rf, RF_PATH_B, 0x60, 0x0000f000, pa_bias_b_2g);
+	halrf_wrf(rf, RF_PATH_B, 0x60, 0x000f0000, pa_bias_b_5g);
+}
+
+void _halrf_get_tssi_trim_8852c(struct rf_info *rf,
+					enum phl_phy_idx phy)
+{
+	struct halrf_tssi_info *tssi = &rf->tssi;
+	u8 i, j , check_tmp = 0, check_tmp_6g = 0;
+
+	RF_DBG(rf, DBG_RF_TSSI_TRIM, "======> %s   phy=%d\n", __func__, phy);
+
+	if (!(rf->support_ability & HAL_RF_TSSI_TRIM)) {
+		RF_DBG(rf, DBG_RF_TSSI_TRIM, "<== %s phy=%d support_ability=0x%x TSSI Trim Off!!!\n",
+			__func__, phy, rf->support_ability);
+		return;
+	}
+
+	_halrf_get_1byte_efuse_8852c(rf, TSSI_TRIM_HIDE_EFUSE_2GL_A_8852C,
+		(u8 *)&tssi->tssi_trim[RF_PATH_A][0]);
+	_halrf_get_1byte_efuse_8852c(rf, TSSI_TRIM_HIDE_EFUSE_2GH_A_8852C,
+		(u8 *)&tssi->tssi_trim[RF_PATH_A][1]);
+
+	_halrf_get_1byte_efuse_8852c(rf, TSSI_TRIM_HIDE_EFUSE_5GL1_A_8852C,
+		(u8 *)&tssi->tssi_trim[RF_PATH_A][2]);
+	_halrf_get_1byte_efuse_8852c(rf, TSSI_TRIM_HIDE_EFUSE_5GL2_A_8852C,
+		(u8 *)&tssi->tssi_trim[RF_PATH_A][3]);
+	_halrf_get_1byte_efuse_8852c(rf, TSSI_TRIM_HIDE_EFUSE_5GM1_A_8852C,
+		(u8 *)&tssi->tssi_trim[RF_PATH_A][4]);
+	_halrf_get_1byte_efuse_8852c(rf, TSSI_TRIM_HIDE_EFUSE_5GM2_A_8852C,
+		(u8 *)&tssi->tssi_trim[RF_PATH_A][5]);
+	_halrf_get_1byte_efuse_8852c(rf, TSSI_TRIM_HIDE_EFUSE_5GH1_A_8852C,
+		(u8 *)&tssi->tssi_trim[RF_PATH_A][6]);
+	_halrf_get_1byte_efuse_8852c(rf, TSSI_TRIM_HIDE_EFUSE_5GH2_A_8852C,
+		(u8 *)&tssi->tssi_trim[RF_PATH_A][7]);
+
+	_halrf_get_1byte_efuse_8852c(rf, TSSI_TRIM_HIDE_EFUSE_2GL_B_8852C,
+		(u8 *)&tssi->tssi_trim[RF_PATH_B][0]);
+	_halrf_get_1byte_efuse_8852c(rf, TSSI_TRIM_HIDE_EFUSE_2GH_B_8852C,
+		(u8 *)&tssi->tssi_trim[RF_PATH_B][1]);
+
+	_halrf_get_1byte_efuse_8852c(rf, TSSI_TRIM_HIDE_EFUSE_5GL1_B_8852C,
+		(u8 *)&tssi->tssi_trim[RF_PATH_B][2]);
+	_halrf_get_1byte_efuse_8852c(rf, TSSI_TRIM_HIDE_EFUSE_5GL2_B_8852C,
+		(u8 *)&tssi->tssi_trim[RF_PATH_B][3]);
+	_halrf_get_1byte_efuse_8852c(rf, TSSI_TRIM_HIDE_EFUSE_5GM1_B_8852C,
+		(u8 *)&tssi->tssi_trim[RF_PATH_B][4]);
+	_halrf_get_1byte_efuse_8852c(rf, TSSI_TRIM_HIDE_EFUSE_5GM2_B_8852C,
+		(u8 *)&tssi->tssi_trim[RF_PATH_B][5]);
+	_halrf_get_1byte_efuse_8852c(rf, TSSI_TRIM_HIDE_EFUSE_5GH1_B_8852C,
+		(u8 *)&tssi->tssi_trim[RF_PATH_B][6]);
+	_halrf_get_1byte_efuse_8852c(rf, TSSI_TRIM_HIDE_EFUSE_5GH2_B_8852C,
+		(u8 *)&tssi->tssi_trim[RF_PATH_B][7]);
+
+	_halrf_get_1byte_efuse_8852c(rf, TSSI_TRIM_HIDE_EFUSE_6GL1_A_8852C,
+		(u8 *)&tssi->tssi_trim_6g[RF_PATH_A][0]);
+	_halrf_get_1byte_efuse_8852c(rf, TSSI_TRIM_HIDE_EFUSE_6GL2_A_8852C,
+		(u8 *)&tssi->tssi_trim_6g[RF_PATH_A][1]);
+	_halrf_get_1byte_efuse_8852c(rf, TSSI_TRIM_HIDE_EFUSE_6GM1_A_8852C,
+		(u8 *)&tssi->tssi_trim_6g[RF_PATH_A][2]);
+	_halrf_get_1byte_efuse_8852c(rf, TSSI_TRIM_HIDE_EFUSE_6GM2_A_8852C,
+		(u8 *)&tssi->tssi_trim_6g[RF_PATH_A][3]);
+	_halrf_get_1byte_efuse_8852c(rf, TSSI_TRIM_HIDE_EFUSE_6GH1_A_8852C,
+		(u8 *)&tssi->tssi_trim_6g[RF_PATH_A][4]);
+	_halrf_get_1byte_efuse_8852c(rf, TSSI_TRIM_HIDE_EFUSE_6GH2_A_8852C,
+		(u8 *)&tssi->tssi_trim_6g[RF_PATH_A][5]);
+	_halrf_get_1byte_efuse_8852c(rf, TSSI_TRIM_HIDE_EFUSE_6GUH1_A_8852C,
+		(u8 *)&tssi->tssi_trim_6g[RF_PATH_A][6]);
+	_halrf_get_1byte_efuse_8852c(rf, TSSI_TRIM_HIDE_EFUSE_6GUH2_A_8852C,
+		(u8 *)&tssi->tssi_trim_6g[RF_PATH_A][7]);
+
+	_halrf_get_1byte_efuse_8852c(rf, TSSI_TRIM_HIDE_EFUSE_6GL1_B_8852C,
+		(u8 *)&tssi->tssi_trim_6g[RF_PATH_B][0]);
+	_halrf_get_1byte_efuse_8852c(rf, TSSI_TRIM_HIDE_EFUSE_6GL2_B_8852C,
+		(u8 *)&tssi->tssi_trim_6g[RF_PATH_B][1]);
+	_halrf_get_1byte_efuse_8852c(rf, TSSI_TRIM_HIDE_EFUSE_6GM1_B_8852C,
+		(u8 *)&tssi->tssi_trim_6g[RF_PATH_B][2]);
+	_halrf_get_1byte_efuse_8852c(rf, TSSI_TRIM_HIDE_EFUSE_6GM2_B_8852C,
+		(u8 *)&tssi->tssi_trim_6g[RF_PATH_B][3]);
+	_halrf_get_1byte_efuse_8852c(rf, TSSI_TRIM_HIDE_EFUSE_6GH1_B_8852C,
+		(u8 *)&tssi->tssi_trim_6g[RF_PATH_B][4]);
+	_halrf_get_1byte_efuse_8852c(rf, TSSI_TRIM_HIDE_EFUSE_6GH2_B_8852C,
+		(u8 *)&tssi->tssi_trim_6g[RF_PATH_B][5]);
+	_halrf_get_1byte_efuse_8852c(rf, TSSI_TRIM_HIDE_EFUSE_6GUH1_B_8852C,
+		(u8 *)&tssi->tssi_trim_6g[RF_PATH_B][6]);
+	_halrf_get_1byte_efuse_8852c(rf, TSSI_TRIM_HIDE_EFUSE_6GUH2_B_8852C,
+		(u8 *)&tssi->tssi_trim_6g[RF_PATH_B][7]);
+
+	/*TSSI Trim 2G, 5G*/
+	for (i = 0; i < 2; i++) {
+		for (j = 0; j < TSSI_HIDE_EFUSE_NUM; j++) {
+			RF_DBG(rf, DBG_RF_TSSI_TRIM, "2G/5G tssi->tssi_trim[%d][%d]=0x%x\n", i, j, tssi->tssi_trim[i][j]);
+			if ((tssi->tssi_trim[i][j] & 0xff) == 0xff)
+				check_tmp++;
+		}
+	}
+
+	RF_DBG(rf, DBG_RF_TSSI_TRIM, "2G/5G check_tmp=%d\n", check_tmp);
+
+	if (check_tmp == 2 * TSSI_HIDE_EFUSE_NUM) {
+		for (i = 0; i < 2; i++) {
+			for (j = 0; j < TSSI_HIDE_EFUSE_NUM; j++)
+				tssi->tssi_trim[i][j] = 0;
+		}
+
+		RF_DBG(rf, DBG_RF_TSSI_TRIM, "2G/5G TSSI Trim no PG tssi->tssi_trim=0x0\n");
+	}
+
+	/*TSSI Trim 6G*/
+	for (i = 0; i < 2; i++) {
+		for (j = 0; j < TSSI_HIDE_EFUSE_NUM_6G; j++) {
+			RF_DBG(rf, DBG_RF_TSSI_TRIM, "6G tssi->tssi_trim_6g[%d][%d]=0x%x\n", i, j, tssi->tssi_trim_6g[i][j]);
+			if ((tssi->tssi_trim_6g[i][j] & 0xff) == 0xff)
+				check_tmp_6g++;
+		}
+	}
+
+	RF_DBG(rf, DBG_RF_TSSI_TRIM, "6G check_tmp_6g=%d\n", check_tmp_6g);
+
+	if (check_tmp_6g == 2 * TSSI_HIDE_EFUSE_NUM_6G) {
+		for (i = 0; i < 2; i++) {
+			for (j = 0; j < TSSI_HIDE_EFUSE_NUM_6G; j++)
+				tssi->tssi_trim_6g[i][j] = 0;
+		}
+
+		RF_DBG(rf, DBG_RF_TSSI_TRIM, "6G TSSI Trim no PG tssi->tssi_trim_6g=0x0\n");
+	}
+}
+
+void halrf_get_efuse_trim_8852c(struct rf_info *rf,
+					enum phl_phy_idx phy)
+{
+	_halrf_get_total_efuse_8852c(rf, phy);
+
+	halrf_write_fwofld_start(rf);	/*FW Offload Start*/
+
+	_halrf_set_thermal_trim_8852c(rf, phy);
+	_halrf_set_pa_bias_trim_8852c(rf, phy);
+
+	halrf_write_fwofld_end(rf); 	/*FW Offload End*/
+
+	_halrf_get_tssi_trim_8852c(rf, phy);
+}
+
+s8 halrf_get_thremal_trim_8852c(struct rf_info *rf, enum rf_path path)
+{
+	struct halrf_kfree_info *kfree = &rf->kfree_info;
+
+	if (path >= MAX_RF_PATH) {
+		RF_DBG(rf, DBG_RF_THER_TRIM, "======> %s   path >= MAX_RF_PATH\n",
+			__func__);
+
+		return 0;
+	}
+
+	RF_DBG(rf, DBG_RF_THER_TRIM, "======> %s   kfree->thermal_trim[%d]=%d\n",
+		__func__, path, kfree->thermal_trim[path]);
+
+	return kfree->thermal_trim[path];
+}
+
+void halrf_kfree_get_info_8852c(struct rf_info *rf, char input[][16], u32 *_used,
+			 char *output, u32 *_out_len)
+{
+	struct halrf_kfree_info *kfree = &rf->kfree_info;
+
+	u8 tmp;
+
+	RF_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
+		 "\n=====================[ KFREE info ]=====================\n");
+
+	RF_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
+		" %-30s : %s\n",
+		"Thermal Trim Protection A",
+		(kfree->thermal_trim_protect[RF_PATH_A] == true) ? " > 2, Enable, Thermal Trim offset = 0" : "Disable, Thermal Trim offset = efuse");
+
+	RF_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
+		" %-30s : 0x%X = 0x%X\n",
+		"Thermal A Efuse",
+		THERMAL_TRIM_HIDE_EFUSE_A_8852C,
+		_halrf_get_1byte_efuse_8852c(rf, THERMAL_TRIM_HIDE_EFUSE_A_8852C, &tmp));
+
+	RF_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
+		" %-30s : %s = 0x%X\n",
+		"Thermal A RFC",
+		"0x43[19:16]",
+		halrf_rrf(rf, RF_PATH_A, 0x43, 0x000f0000));
+
+	RF_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
+		" %-30s : %s = %d\n",
+		"Thermal Trim A",
+		"Offset",
+		halrf_get_thremal_trim_8852c(rf, RF_PATH_A));
+
+	RF_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
+		" %-30s : %s\n",
+		"Thermal Trim Protection B",
+		(kfree->thermal_trim_protect[RF_PATH_B] == true) ? " > 2, Enable, Thermal Trim offset = 0" : "Disable, Thermal Trim offset = efuse");
+
+	RF_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
+		" %-30s : 0x%X = 0x%X\n",
+		"Thermal B Efuse",
+		THERMAL_TRIM_HIDE_EFUSE_B_8852C,
+		_halrf_get_1byte_efuse_8852c(rf, THERMAL_TRIM_HIDE_EFUSE_B_8852C, &tmp));
+
+	RF_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
+		" %-30s : %s = 0x%X\n",
+		"Thermal B RFC",
+		"0x43[19:16]",
+		halrf_rrf(rf, RF_PATH_B, 0x43, 0x000f0000));
+
+	RF_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
+		" %-30s : %s = %d\n",
+		"Thermal Trim B",
+		"Offset",
+		halrf_get_thremal_trim_8852c(rf, RF_PATH_B));
+
+	RF_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
+		" %-30s : 0x%X = 0x%X\n",
+		"PABias 2G A Efuse",
+		PABIAS_TRIM_HIDE_EFUSE_A_8852C,
+		_halrf_get_1byte_efuse_8852c(rf, PABIAS_TRIM_HIDE_EFUSE_A_8852C, &tmp));
+
+	RF_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
+		" %-30s : %s = 0x%X\n",
+		"PABias 2G A RFC",
+		"0x60[15:12]",
+		halrf_rrf(rf, RF_PATH_A, 0x60, 0x0000f000));
+
+	RF_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
+		" %-30s : 0x%X = 0x%X\n",
+		"PABias 2G B Efuse",
+		PABIAS_TRIM_HIDE_EFUSE_B_8852C,
+		_halrf_get_1byte_efuse_8852c(rf, PABIAS_TRIM_HIDE_EFUSE_B_8852C, &tmp));
+
+	RF_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
+		" %-30s : %s = 0x%X\n",
+		"PABias 2G B RFC",
+		"0x60[15:12]",
+		halrf_rrf(rf, RF_PATH_B, 0x60, 0x0000f000));
+
+	RF_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
+		" %-30s : 0x%X = 0x%X\n",
+		"PABias 5G A Efuse",
+		PABIAS_TRIM_HIDE_EFUSE_A_8852C,
+		_halrf_get_1byte_efuse_8852c(rf, PABIAS_TRIM_HIDE_EFUSE_A_8852C, &tmp));
+
+	RF_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
+		" %-30s : %s = 0x%X\n",
+		"PABias 5G A RFC",
+		"0x60[19:16]",
+		halrf_rrf(rf, RF_PATH_A, 0x60, 0x000f0000));
+
+	RF_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
+		" %-30s : 0x%X = 0x%X\n",
+		"PABias 5G B Efuse",
+		PABIAS_TRIM_HIDE_EFUSE_B_8852C,
+		_halrf_get_1byte_efuse_8852c(rf, PABIAS_TRIM_HIDE_EFUSE_B_8852C, &tmp));
+
+	RF_DBG_CNSL(*_out_len, *_used, output + *_used, *_out_len - *_used,
+		" %-30s : %s = 0x%X\n",
+		"PABias 5G B RFC",
+		"0x60[19:16]",
+		halrf_rrf(rf, RF_PATH_B, 0x60, 0x000f0000));
+}
+
+#endif	/*RF_8852C_SUPPORT*/

3rd/devourer/hal/halrf/g6/vendor/halrf_8852c/halrf_kfree_8852c.h

@@ -0,0 +1,78 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2019 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef _HALRF_KFREE_8852C_H_
+#define _HALRF_KFREE_8852C_H_
+#ifdef RF_8852C_SUPPORT
+
+/*@--------------------------Define Parameters-------------------------------*/
+
+#define HIDE_EFUSE_START_ADDR_8852C	 0x590
+#define HIDE_EFUSE_END_ADDR_8852C	 0x5DF
+#define HIDE_EFUSE_SIZE_8852C		 HIDE_EFUSE_END_ADDR_8852C - HIDE_EFUSE_START_ADDR_8852C + 1
+
+#define THERMAL_TRIM_HIDE_EFUSE_A_8852C 0x5DF
+#define THERMAL_TRIM_HIDE_EFUSE_B_8852C 0x5DC
+
+#define PABIAS_TRIM_HIDE_EFUSE_A_8852C 0x5DE
+#define PABIAS_TRIM_HIDE_EFUSE_B_8852C 0x5DB
+
+#define TSSI_TRIM_HIDE_EFUSE_2GL_A_8852C 0x5D6
+#define TSSI_TRIM_HIDE_EFUSE_2GH_A_8852C 0x5D5
+#define TSSI_TRIM_HIDE_EFUSE_5GL1_A_8852C 0x5D4
+#define TSSI_TRIM_HIDE_EFUSE_5GL2_A_8852C 0x5D3
+#define TSSI_TRIM_HIDE_EFUSE_5GM1_A_8852C 0x5D2
+#define TSSI_TRIM_HIDE_EFUSE_5GM2_A_8852C 0x5D1
+#define TSSI_TRIM_HIDE_EFUSE_5GH1_A_8852C 0x5D0
+#define TSSI_TRIM_HIDE_EFUSE_5GH2_A_8852C 0x5CF
+
+#define TSSI_TRIM_HIDE_EFUSE_2GL_B_8852C 0x5AB
+#define TSSI_TRIM_HIDE_EFUSE_2GH_B_8852C 0x5AA
+#define TSSI_TRIM_HIDE_EFUSE_5GL1_B_8852C 0x5A9
+#define TSSI_TRIM_HIDE_EFUSE_5GL2_B_8852C 0x5A8
+#define TSSI_TRIM_HIDE_EFUSE_5GM1_B_8852C 0x5A7
+#define TSSI_TRIM_HIDE_EFUSE_5GM2_B_8852C 0x5A6
+#define TSSI_TRIM_HIDE_EFUSE_5GH1_B_8852C 0x5A5
+#define TSSI_TRIM_HIDE_EFUSE_5GH2_B_8852C 0x5A4
+
+#define TSSI_TRIM_HIDE_EFUSE_6GL1_A_8852C 0x5CE
+#define TSSI_TRIM_HIDE_EFUSE_6GL2_A_8852C 0x5CD
+#define TSSI_TRIM_HIDE_EFUSE_6GM1_A_8852C 0x5CC
+#define TSSI_TRIM_HIDE_EFUSE_6GM2_A_8852C 0x5CB
+#define TSSI_TRIM_HIDE_EFUSE_6GH1_A_8852C 0x5CA
+#define TSSI_TRIM_HIDE_EFUSE_6GH2_A_8852C 0x5C9
+#define TSSI_TRIM_HIDE_EFUSE_6GUH1_A_8852C 0x5C8
+#define TSSI_TRIM_HIDE_EFUSE_6GUH2_A_8852C 0x5C7
+
+#define TSSI_TRIM_HIDE_EFUSE_6GL1_B_8852C 0x5A3
+#define TSSI_TRIM_HIDE_EFUSE_6GL2_B_8852C 0x5A2
+#define TSSI_TRIM_HIDE_EFUSE_6GM1_B_8852C 0x5A1
+#define TSSI_TRIM_HIDE_EFUSE_6GM2_B_8852C 0x5A0
+#define TSSI_TRIM_HIDE_EFUSE_6GH1_B_8852C 0x59F
+#define TSSI_TRIM_HIDE_EFUSE_6GH2_B_8852C 0x59E
+#define TSSI_TRIM_HIDE_EFUSE_6GUH1_B_8852C 0x59D
+#define TSSI_TRIM_HIDE_EFUSE_6GUH2_B_8852C 0x59C
+
+/*@-----------------------End Define Parameters-----------------------*/
+
+void halrf_get_efuse_trim_8852c(struct rf_info *rf,
+					enum phl_phy_idx phy);
+
+s8 halrf_get_thremal_trim_8852c(struct rf_info *rf, enum rf_path path);
+
+void halrf_kfree_get_info_8852c(struct rf_info *rf, char input[][16], u32 *_used,
+			 char *output, u32 *_out_len);
+
+#endif
+#endif	/*_HALRF_SET_PWR_TABLE_8852C_H_*/

3rd/devourer/hal/halrf/g6/vendor/halrf_8852c/halrf_ops_rtl8852c.c

@@ -0,0 +1,55 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2020  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+#include "../halrf_precomp.h"
+#ifdef RF_8852C_SUPPORT
+
+static struct halrf_rfk_ops rfk_ops_8852c= {
+	.ops_rx_dck = halrf_rx_dck_8852c,
+	.ops_do_txgapk = halrf_do_txgapk_8852c,
+	.ops_tssi_disable = halrf_tssi_disable_8852c,
+	.ops_do_tssi = halrf_do_tssi_8852c,
+	.ops_dpk = halrf_dpk_8852c,
+	.ops_dack = halrf_dac_cal_8852c,
+	.ops_lck = halrf_lck_8852c,
+	.ops_lck_tracking = halrf_lck_tracking_8852c,
+	.ops_lo_test = halrf_lo_test_8852c,
+	.ops_config_radio_to_fw = halrf_config_8852c_radio_to_fw,
+	.ops_txgapk_w_table_default = halrf_txgapk_write_table_default_8852c,
+	.ops_txgapk_enable = NULL,
+	.ops_txgapk_init = halrf_txgapk_init_8852c,
+	.ops_adie_pow_ctrl = halrf_adie_pow_ctrl_8852c,
+	.ops_afe_pow_ctrl = halrf_afe_pow_ctrl_8852c,
+	.ops_set_gpio_by_ch = halrf_set_gpio_by_ch_8852c,
+#ifdef HALRF_MCC_DBCC
+	.ops_chlk_reload_check = halrf_chlk_reload_check_8852c,
+#endif
+};
+
+void rf_set_ops_8852c(struct rf_info *rf) {
+
+	rf->rf_rfk_ops = &rfk_ops_8852c;
+}
+
+#endif

3rd/devourer/hal/halrf/g6/vendor/halrf_8852c/halrf_ops_rtl8852c.h

@@ -0,0 +1,34 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2020  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+#ifndef __HALRF_OPS_RTL8852C_H__
+#define __HALRF_OPS_RTL8852C__
+#ifdef RF_8852C_SUPPORT
+
+
+void rf_set_ops_8852c(struct rf_info *rf) ;
+
+
+#endif
+#endif /*  __HALRF_OPS_RTL8852C_H__ */

3rd/devourer/hal/halrf/g6/vendor/halrf_8852c/halrf_psd_8852c.h

@@ -0,0 +1,45 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2019 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef _HALRF_PSD_TSSI_8852C_H_
+#define _HALRF_PSD_TSSI_8852C_H_
+
+#ifdef RF_8852C_SUPPORT
+#ifdef HALRF_PSD_SUPPORT
+
+#define PSD_VER_8852C 0x1
+#define PSD_BACKUP_NUM_8852C 36
+
+#define PSD_RF_PATH_MAX_8852C 2
+#define PSD_RF_REG_NUM_8852C 5
+
+
+/*@--------------------------Define Parameters-------------------------------*/
+/*@-----------------------End Define Parameters-----------------------*/
+
+void halrf_psd_init_8852c(struct rf_info *rf, enum phl_phy_idx phy,
+			u8 path, u8 iq_path, u32 avg, u32 fft);
+			
+void halrf_psd_restore_8852c(struct rf_info *rf, enum phl_phy_idx phy);	
+			
+u32 halrf_psd_get_point_data_8852c(struct rf_info *rf,
+			enum phl_phy_idx phy, s32 point);
+			
+void halrf_psd_query_8852c(struct rf_info *rf, enum phl_phy_idx phy,
+			u32 point, u32 start_point, u32 stop_point, u32 *outbuf);
+
+#endif	/*HALRF_PSD_SUPPORT*/
+#endif	/*RF_8852C_SUPPORT*/
+#endif	/*_HALRF_PSD_TSSI_8852C_H_*/
+

3rd/devourer/hal/halrf/g6/vendor/halrf_8852c/halrf_reg_cfg_8852c.c

@@ -0,0 +1,64 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#include "../halrf_precomp.h"
+#ifdef RF_8852C_SUPPORT
+
+void halrf_cfg_rf_radio_a_8852c(struct rf_info *rf, u32 addr, u32 data)
+{
+	/*laod radio a table*/
+	halrf_wrf(rf, RF_PATH_A, addr, MASKRF, data);
+	RF_DBG(rf, DBG_RF_INIT, "[RF_a] %08X %08X\n", addr, data);
+}
+
+void halrf_cfg_rf_radio_b_8852c(struct rf_info *rf, u32 addr, u32 data)
+{
+	/*laod radio b table*/
+	halrf_wrf(rf, RF_PATH_B, addr, MASKRF, data);
+	RF_DBG(rf, DBG_RF_INIT, "[RF_b] %08X %08X\n", addr, data);
+}
+
+void halrf_cfg_rf_nctl_8852c(struct rf_info *rf, u32 addr, u32 mask, u32 data)
+{
+/*laod NCTL table*/
+	if (addr == 0xfe)
+		halrf_delay_ms(rf, 50);
+	else if (addr == 0xfd)
+		halrf_delay_ms(rf, 5);
+	else if (addr == 0xfc)
+		halrf_delay_ms(rf, 1);
+	else if (addr == 0xfb)
+		halrf_delay_us(rf, 50);
+	else if (addr == 0xfa)
+		halrf_delay_us(rf, 5);
+	else if (addr == 0xf9)
+		halrf_delay_us(rf, 1);
+	else
+		halrf_wreg(rf, addr, mask, data);
+	
+	RF_DBG(rf, DBG_RF_INIT, "[RFK] %08X %08X\n", addr, data);
+}
+
+#endif

3rd/devourer/hal/halrf/g6/vendor/halrf_8852c/halrf_reg_cfg_8852c.h

@@ -0,0 +1,35 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+#ifndef _HALRF_REG_CFG_8852C_H_
+#define _HALRF_REG_CFG_8852C_H_
+
+#ifdef RF_8852C_SUPPORT
+
+void halrf_cfg_rf_radio_a_8852c(struct rf_info *rf, u32 addr, u32 data);
+void halrf_cfg_rf_radio_b_8852c(struct rf_info *rf, u32 addr, u32 data);
+void halrf_cfg_rf_nctl_8852c(struct rf_info *rf, u32 addr, u32 mask, u32 data);
+
+#endif
+#endif /* RTL8852C_SUPPORT*/

3rd/devourer/hal/halrf/g6/vendor/halrf_8852c/halrf_set_pwr_table_8852c.h

@@ -0,0 +1,68 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2019 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef _HALRF_SET_PWR_TABLE_8852C_H_
+#define _HALRF_SET_PWR_TABLE_8852C_H_
+
+#ifdef RF_8852C_SUPPORT
+
+/*@--------------------------Define Parameters-------------------------------*/
+#define MAX_TX_PATH	2
+#define TPU_SIZE_RUA	3 /*{26, 52, 106}*/
+#define TPU_SIZE_BW20_SC  8 /*8 * 20M = 160M*/
+
+/*@-----------------------End Define Parameters-----------------------*/
+
+bool halrf_set_power_by_rate_to_mac_8852c(struct rf_info *rf,
+						enum phl_phy_idx phy);
+
+void halrf_set_fix_power_to_struct_8852c(struct rf_info *rf,
+					enum phl_phy_idx phy, s8 dbm);
+
+bool halrf_set_power_limit_to_mac_8852c(struct rf_info *rf,
+	enum phl_phy_idx phy);
+
+void halrf_set_ref_power_to_struct_8852c(struct rf_info *rf,
+						enum phl_phy_idx phy);
+
+bool halrf_set_power_by_rate_to_struct_8852c(struct rf_info *rf, enum phl_phy_idx phy);
+
+bool halrf_set_power_limit_to_struct_8852c(struct rf_info *rf, enum phl_phy_idx phy);
+
+bool halrf_set_power_limit_ru_to_struct_8852c(struct rf_info *rf, enum phl_phy_idx phy);
+
+bool halrf_set_power_8852c(struct rf_info *rf, enum phl_phy_idx phy,
+	enum phl_pwr_table pwr_table);
+
+void halrf_pwr_by_rate_info_8852c(struct rf_info *rf,
+		char input[][16], u32 *_used, char *output, u32 *_out_len, enum phl_phy_idx phy);
+
+void halrf_pwr_limit_info_8852c(struct rf_info *rf,
+		char input[][16], u32 *_used, char *output, u32 *_out_len, enum phl_phy_idx phy);
+
+void halrf_pwr_limit_ru_info_8852c(struct rf_info *rf,
+		char input[][16], u32 *_used, char *output, u32 *_out_len, enum phl_phy_idx phy);
+
+void halrf_set_tx_shape_8852c(struct rf_info *rf, u8 tx_shape_idx);
+
+void halrf_set_bw160m_diff_8852c(struct rf_info *rf, enum phl_phy_idx phy);
+
+void halrf_set_power_limit_wa_8852c(struct rf_info *rf, enum phl_phy_idx phy);
+
+void halrf_set_bw_power_by_rate_offset_8852c(struct rf_info *rf, u32 pwr_by_rate_bw_ofst);
+
+s8 halrf_get_pwr_by_rate_bw_control_8852c(struct rf_info *rf, enum phl_phy_idx phy, u16 rate, u32 band, s8 pwr_by_rate);
+
+#endif	/*RF_8852C_SUPPORT*/
+#endif	/*_HALRF_SET_PWR_TABLE_8852C_H_*/

3rd/devourer/hal/halrf/g6/vendor/halrf_8852c/halrf_tssi_8852c.h

@@ -0,0 +1,88 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2019 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef _HALRF_TSSI_8852C_H_
+#define _HALRF_TSSI_8852C_H_
+#ifdef RF_8852C_SUPPORT
+
+#define TSSI_VER_8852C 0x30
+#define TSSI_PATH_MAX_8852C 2
+
+/*@--------------------------Define Parameters-------------------------------*/
+
+
+/*@-----------------------End Define Parameters-----------------------*/
+void halrf_tssi_get_efuse_8852c(struct rf_info *rf,
+						enum phl_phy_idx phy);
+bool halrf_tssi_check_efuse_data_8852c(struct rf_info *rf,
+						enum phl_phy_idx phy);
+void halrf_set_tssi_de_for_tx_verify_8852c(struct rf_info *rf,
+				enum phl_phy_idx phy, u32 tssi_de, u8 path);
+void halrf_set_tssi_de_offset_8852c(struct rf_info *rf,
+				enum phl_phy_idx phy, u32 tssi_de_offset, u8 path);
+void halrf_set_tssi_de_offset_zero_8852c(struct rf_info *rf,
+							enum phl_phy_idx phy);
+void halrf_do_tssi_8852c(struct rf_info *rf, enum phl_phy_idx phy, bool hwtx_en);
+void halrf_do_tssi_scan_8852c(struct rf_info *rf, enum phl_phy_idx phy);
+void halrf_tssi_enable_8852c(struct rf_info *rf, enum phl_phy_idx phy);
+void halrf_tssi_disable_8852c(struct rf_info *rf, enum phl_phy_idx phy);
+s32 halrf_get_online_tssi_de_8852c(struct rf_info *rf, enum phl_phy_idx phy_idx,
+				u8 path, s32 dbm, s32 puot);
+void halrf_tssi_cck_8852c(struct rf_info *rf, enum phl_phy_idx phy,
+				bool is_cck);
+void halrf_set_tssi_avg_mp_8852c(struct rf_info *rf,
+					enum phl_phy_idx phy_idx, s32 xdbm);
+void halrf_tssi_set_efuse_to_de_8852c(struct rf_info *rf,
+						enum phl_phy_idx phy);
+void halrf_tssi_set_efuse_to_slope_8852c(struct rf_info *rf,
+						enum phl_phy_idx phy);
+void halrf_tssi_default_txagc_8852c(struct rf_info *rf,
+					enum phl_phy_idx phy, bool enable);
+
+void halrf_tssi_scan_ch_setting_8852c(struct rf_info *rf,
+	enum phl_phy_idx phy, enum rf_path path);
+
+void halrf_tssi_scan_ch_8852c(struct rf_info *rf, enum rf_path path);
+
+void halrf_tssi_backup_txagc_8852c(struct rf_info *rf, enum phl_phy_idx phy, bool enable);
+
+u32 halrf_tssi_get_final_8852c(struct rf_info *rf, enum rf_path path);
+
+void halrf_tssi_hw_tx_8852c(struct rf_info *rf,
+			enum phl_phy_idx phy, u8 path, u16 cnt, s16 dbm, u32 rate, u8 bw,
+			bool enable);
+
+void halrf_tssi_ant_open_8852c(struct rf_info *rf);
+
+void halrf_tssi_slope_onoff_8852c(struct rf_info *rf, u8 tssi_slope_type);
+
+void halrf_get_tssi_info_8852c(struct rf_info *rf,
+		char input[][16], u32 *_used, char *output, u32 *_out_len);
+
+void halrf_tssi_do_slope_8852c(struct rf_info *rf);
+
+u32 halrf_tssi_get_cw_8852c(struct rf_info *rf, enum rf_path path);
+
+void halrf_tssi_slope_apply_8852c(struct rf_info *rf,
+	u32 gain_first, u32 gain_second,
+	u32 cw_first, u32 cw_second, enum rf_path path,
+	u32* gain_diff, u32* cw_diff);
+
+void halrf_tssi_current_slope_apply_8852c(struct rf_info *rf,
+	u32 gain_diff, u32 cw_diff, enum rf_path path);
+
+void halrf_tssi_finish_slope_8852c(struct rf_info *rf);
+
+#endif
+#endif	/*_HALRF_SET_PWR_TABLE_8852C_H_*/

3rd/devourer/hal/halrf/g6/vendor/halrf_8852c/halrf_txgapk_8852c.h

@@ -0,0 +1,71 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#ifndef __HALRF_TXGAPK_8852C_H__
+#define __HALRF_TXGAPK_8852C_H__
+
+#ifdef RF_8852C_SUPPORT
+
+#define TXGAPK_VER_8852C 0x19
+#define TXGAPK_NCTL_FINAL_LINE_8852C 0x8000
+
+
+#define TXGAPK_DBG 0
+/*--------------------------Define Parameters-------------------------------*/
+
+#define TXGAPK_KIP_REG_NUM_8852C 7
+#define TXGAPK_BB_REG_NUM_8852C 5
+#define TXGAPK_RF_REG_NUM_8852C 4
+
+
+#define TXGAPK_RF_PATH_MAX_8852C 2
+
+
+#define TXGAPK_DEBUGMASK_8852C		0x100EE
+
+#define TXGAP_TB_ADDR_8852C			0x10033
+	
+#define TXGAP_TB_VAL_8852C			0x1003F
+
+
+/*---------------------------End Define Parameters----------------------------*/
+
+
+
+/*
+void halrf_txgapk_enable_8852c
+	(struct rf_info *rf, enum phl_phy_idx phy);
+*/
+void halrf_txgapk_write_table_default_8852c
+	(struct rf_info *rf, enum phl_phy_idx phy);
+
+void halrf_do_txgapk_8852c(struct rf_info *rf, enum phl_phy_idx phy);
+
+
+void halrf_txgapk_init_8852c(struct rf_info *rf);
+
+
+#endif /* RF_8852C_SUPPORT */
+#endif /*#ifndef __HALRF_TXGAPK_8852C_H__*/

3rd/devourer/hal/halrf/g6/vendor/halrf_8852c/halrf_version_rtl8852c.h

@@ -0,0 +1,26 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+/*RTL8852C RF Parameters*/
+#define	RF_RELEASE_VERSION_8852C	0x78

3rd/devourer/hal/halrf/g6/vendor/halrf_api.h

@@ -0,0 +1,167 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2019 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef _HALRF_API_H_
+#define _HALRF_API_H_
+/*@--------------------------[Define] ---------------------------------------*/
+#define HALRF_ABS(a,b) ((a>b) ? (a-b) : (b-a))
+/*@--------------------------[Enum]------------------------------------------*/
+enum phlrf_lna_set {
+	PHLRF_LNA_DISABLE = 0,
+	PHLRF_LNA_ENABLE = 1,
+};
+
+enum halrf_rfk_type {
+	RF_BTC_IQK		= 0,
+	RF_BTC_LCK		= 1,
+	RF_BTC_DPK		= 2,
+	RF_BTC_TXGAPK		= 3,
+	RF_BTC_DACK		= 4,
+	RF_BTC_RXDCK		= 5,
+	RF_BTC_TSSI		= 6,
+	RF_BTC_CHLK		= 7
+};
+
+enum halrf_rfk_fwlog {
+	RFK_LOG_IQK		= 0,
+	RFK_LOG_DPK		= 1,
+	RFK_LOG_DACK		= 2,
+	RFK_LOG_RXDCK		= 3,
+	RFK_LOG_TXGAPK	= 4,
+	RFK_LOG_TSSI		= 5,
+	RFK_LOG_TXTABLE	= 6,
+	RFK_LOG_TAS_PWR = 9,
+};
+
+enum halrf_rfk_process {
+	RFK_STOP		= 0,
+	RFK_START		= 1,
+	RFK_ONESHOT_START	= 2,
+	RFK_ONESHOT_STOP	= 3
+};
+
+enum adc_ck {
+	ADC_NA	= 0,
+	ADC_480M	= 1,
+	ADC_960M	= 2,
+	ADC_1920M	= 3,
+};
+
+enum dac_ck {
+	DAC_40M	= 0,
+	DAC_80M	= 1,
+	DAC_120M	= 2,
+	DAC_160M	= 3,
+	DAC_240M	= 4,
+	DAC_320M	= 5,
+	DAC_480M	= 6,
+	DAC_960M	= 7,
+};
+
+enum halrf_event_idx {
+	RF_EVENT_PWR_TRK = 0,
+	RF_EVENT_IQK = 1,
+	RF_EVENT_DPK = 2,
+	RF_EVENT_TXGAPK = 3,
+	RF_EVENT_DACK = 4,
+	RF_EVENT_RXDCK = 5
+};
+
+enum halrf_event_func {
+	RF_EVENT_OFF = 0,
+	RF_EVENT_ON = 1,
+	RF_EVENT_TRIGGER = 2
+};
+
+
+/*@--------------------------[Structure]-------------------------------------*/
+ 
+/*@--------------------------[Prptotype]-------------------------------------*/
+struct rf_info;
+
+u32 phlrf_psd_log2base(struct rf_info *rf, u32 val);
+
+void phlrf_rf_lna_setting(struct rf_info *rf, enum phlrf_lna_set type);
+
+void halrf_bkp(struct rf_info *rf, u32 *bp_reg, u32 *bp, u32 reg_num);
+
+void halrf_bkprf(struct rf_info *rf, u32 *bp_reg, u32 bp[][4], u32 reg_num, u32 path_num);
+
+void halrf_reload_bkp(struct rf_info *rf, u32 *bp_reg, u32 *bp, u32 reg_num);
+	
+void halrf_reload_bkprf(struct rf_info *rf,
+		       u32 *bp_reg,
+		       u32 bp[][4],
+		       u32 reg_num,
+		       u8 path_num);
+
+u8 halrf_kpath(struct rf_info *rf, enum phl_phy_idx phy_idx);
+
+void halrf_tmac_tx_pause(struct rf_info *rf, enum phl_phy_idx band_idx, bool pause);
+
+void halrf_trigger_thermal(struct rf_info *rf);
+
+u8 halrf_only_get_thermal(struct rf_info *rf, enum rf_path path);
+
+void halrf_thermal_period(struct rf_info *rf);
+
+void halrf_btc_rfk_ntfy(struct rf_info *rf, u8 phy_map, enum halrf_rfk_type type,
+			enum halrf_rfk_process process);
+void halrf_fcs_init(struct rf_info *rf);
+void halrf_fast_chl_sw_backup(struct rf_info *rf, u8 chl_index, u8 t_index);
+void halrf_fast_chl_sw_reload(struct rf_info *rf, u8 chl_index, u8 t_index);
+
+/*FW Offload*/
+void halrf_write_fwofld_start(struct rf_info *rf);
+void halrf_write_fwofld_trigger(struct rf_info *rf);
+void halrf_write_fwofld_end(struct rf_info *rf);
+
+void  halrf_quick_check_rf(void *rf_void);
+
+/*MCC function*/
+void halrf_mcc_info_init(void *rf_void, enum phl_phy_idx phy);
+void halrf_mcc_get_ch_info(void *rf_void, enum phl_phy_idx phy);
+void halrf_watchdog_stop(struct rf_info *rf, bool is_stop);
+/*DBCC*/
+void halrf_chlk_backup_dbcc(struct rf_info *rf, enum phl_phy_idx phy);
+void halrf_chlk_reload_dbcc(struct rf_info *rf, enum phl_phy_idx phy, u8 idx);
+bool halrf_chlk_reload_check_dbcc(struct rf_info *rf, enum phl_phy_idx phy);
+void halrf_reset_io_count(struct rf_info *rf);
+void halrf_common_setting_chl_rfk(struct rf_info *rf, enum phl_phy_idx phy, bool is_before_k);
+bool halrf_is_under_cac(struct rf_info *rf, enum phl_phy_idx phy);
+//
+void halrf_ops_rx_dck(struct rf_info *rf, enum phl_phy_idx phy, bool is_afe);
+//---- txgapk ---
+void halrf_ops_do_txgapk(struct rf_info *rf, enum phl_phy_idx phy);
+void halrf_ops_txgapk_w_table_default(struct rf_info *rf, enum phl_phy_idx phy);
+void halrf_ops_txgapk_enable(struct rf_info *rf, enum phl_phy_idx phy);
+void halrf_ops_txgapk_init(struct rf_info *rf);
+//---------------
+void halrf_ops_tssi_disable(struct rf_info *rf, enum phl_phy_idx phy);
+void halrf_ops_do_tssi(struct rf_info *rf, enum phl_phy_idx phy, bool hwtx_en);
+void halrf_ops_dpk(struct rf_info *rf, enum phl_phy_idx phy, bool force);
+void halrf_ops_dack(struct rf_info *rf, bool force);
+void halrf_ops_lck(struct rf_info *rf);
+void halrf_ops_lck_tracking(struct rf_info *rf);
+void halrf_ops_lo_test(struct rf_info *rf, bool is_on, enum rf_path path);
+void halrf_ops_config_radio_to_fw(struct rf_info *rf);
+void halrf_ops_adie_pow_ctrl(struct rf_info *rf, bool rf_off, bool others_off);
+void halrf_ops_afe_pow_ctrl(struct rf_info *rf, bool adda_off, bool pll_off);
+void halrf_ops_set_gpio_by_ch(struct rf_info *rf, enum phl_phy_idx phy, enum band_type band);
+void halrf_rpt_rt_rfk_info(struct rf_info *rf, enum phl_phy_idx phy, u32 type);
+void halrf_bb_reset(struct rf_info *rf, enum phl_phy_idx phy_idx);
+bool halrf_chlk_reload_check(struct rf_info *rf, enum phl_phy_idx phy);
+void halrf_long_pkt_comp(struct rf_info *rf, enum phl_phy_idx phy_idx);
+void halrf_rfk_dz_err_notify(struct rf_info *rf, u32 err_code, u32 err_type);
+#endif

3rd/devourer/hal/halrf/g6/vendor/halrf_dack.h

@@ -0,0 +1,60 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2019 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef _HALRF_DACK_H_
+#define _HALRF_DACK_H_
+
+/*@--------------------------Define Parameters-------------------------------*/
+
+enum halrf_dack_dz{
+	DZ_ADDCK0_TIMEOUT	= BIT(0),
+	DZ_DADCK0_TIMEOUT	= BIT(1),
+	DZ_MSBK0_TIMEOUT	= BIT(2),
+	DZ_ADDCK1_TIMEOUT	= BIT(16),
+	DZ_DADCK1_TIMEOUT	= BIT(17),
+	DZ_MSBK1_TIMEOUT	= BIT(18),
+};
+/*@-----------------------End Define Parameters-----------------------*/
+
+struct halrf_dack_rpt {
+	u8 msbk_d[2][2][16];
+	u8 dadck_d[2][2];		/*path/IQ*/
+	u16 addck_d[2][2];	/*path/IQ*/
+	u16 biask_d[2][2];		/*path/IQ*/
+	u8 addck_timeout_s0: 1;
+	u8 addck_timeout_s1: 1;
+	u8 dadck_timeout_s0: 1;
+	u8 dadck_timeout_s1: 1;
+	u8 msbk_timeout_s0: 1;
+	u8 msbk_timeout_s1: 1;
+	u8 dack_fail: 1;
+	u8 rsvd: 1;
+};
+
+struct halrf_dack_info {
+	bool dack_done;
+	u8 msbk_d[2][2][16];
+	u8 dadck_d[2][2];		/*path/IQ*/
+	u16 addck_d[2][2];	/*path/IQ*/
+	u16 biask_d[2][2];		/*path/IQ*/
+	u32 dack_cnt;
+	u32 dack_time;
+	bool addck_timeout[2];
+	bool dadck_timeout[2];
+	bool msbk_timeout[2];
+	bool dack_fail;
+	struct halrf_dack_rpt dack_rpt;
+};
+
+#endif

3rd/devourer/hal/halrf/g6/vendor/halrf_dbg.h

@@ -0,0 +1,122 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2020  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+#ifndef __HALRF_DBG_H__
+#define __HALRF_DBG_H__
+
+/*@--------------------------[Define] ---------------------------------------*/
+#define HALRF_WATCHDOG_PERIOD	2 /*second*/
+
+#define RFDBG_DBG_EN
+#ifdef RFDBG_DBG_EN
+#define RF_DBG(rf, comp, fmt, ...)	   \
+	do {\
+		if(rf->dbg_component & comp)\
+			_os_dbgdump("[RF]" fmt, ##__VA_ARGS__);\
+	} while (0)
+#else
+	#define RF_DBG
+#endif
+
+
+
+#define RFDBG_TRACE_EN
+#ifdef RFDBG_TRACE_EN
+	#define RF_TRACE(fmt, ...)     \
+		do {\
+			_os_dbgdump("[RF]" fmt, ##__VA_ARGS__);\
+		} while (0)
+		
+	#define RF_WARNING(fmt, ...)     \
+		do {\
+			_os_dbgdump("[WARNING][RF]" fmt, ##__VA_ARGS__);\
+		} while (0)
+
+	#define RF_DBG_VAST(max_buff_len, used_len, buff_addr, remain_len, fmt, ...)\
+		do {\
+			_os_dbgdump(fmt, ##__VA_ARGS__);\
+		} while (0)
+
+	#define	RF_DBG_CNSL(max_buff_len, used_len, buff_addr, remain_len, fmt, ...)\
+		do {									\
+			u32 *used_len_tmp = &(used_len);				\
+			if (*used_len_tmp < max_buff_len)				\
+				*used_len_tmp += _os_snprintf(buff_addr, remain_len, fmt, ##__VA_ARGS__);\
+		} while (0)
+#else
+	#define RF_TRACE
+	#define RF_WARNING
+	#define RF_DBG_CNSL		/*Print on Consol,CLI */
+	#define RF_DBG_VAST		/*Print to Comport, Debug View*/
+#endif	
+
+
+/*@--------------------------[Enum]------------------------------------------*/
+ 
+/*@--------------------------[Structure]-------------------------------------*/
+ 
+/*@--------------------------[Prptotype]-------------------------------------*/
+struct rf_info;
+void halrf_dbg_setting_init(struct rf_info *rf);
+void halrf_iqk_log(struct rf_info *rf);
+void halrf_lck_log(struct rf_info *rf);
+void halrf_dump_rfk_reg(struct rf_info *rf, char input[][16], u32 *_used, char *output, u32 *_out_len);
+void halrf_support_ability(struct rf_info *rf, char input[][16], u32 *_used, char *output, u32 *_out_len);
+void halrf_dbg_trace(struct rf_info *rf, char input[][16], u32 *_used, char *output, u32 *_out_len);
+void halrf_dpk_dbg_cmd(struct rf_info *rf, char input[][16], u32 *_used, char *output, u32 *_out_len);
+void halrf_dpk_track_dbg_cmd(struct rf_info *rf, char input[][16], u32 *_used, char *output, u32 *_out_len);
+void halrf_rx_dck_dbg_cmd(struct rf_info *rf, char input[][16], u32 *_used, char *output, u32 *_out_len);
+void halrf_dack_dbg_cmd(struct rf_info *rf, char input[][16], u32 *_used, char *output, u32 *_out_len);
+void halrf_tssi_dbg_cmd(struct rf_info *rf, char input[][16], u32 *_used, char *output, u32 *_out_len);
+void halrf_iqk_dbg_cmd(struct rf_info *rf, char input[][16], u32 *_used,
+		       char *output, u32 *_out_len);
+void halrf_iqk_bypass_cmd(struct rf_info *rf, char input[][16], u32 *_used,
+			 char *output, u32 *_out_len);
+void halrf_iqk_klog_cmd(struct rf_info *rf, char input[][16], u32 *_used,
+			 char *output, u32 *_out_len);
+void halrf_pwr_table_dbg_cmd(struct rf_info *rf, char input[][16], u32 *_used, char *output, u32 *_out_len);
+void halrf_rfk_check_reg_cmd(struct rf_info *rf, char input[][16], u32 *_used, char *output, u32 *_out_len);
+void halrf_test_cmd(struct rf_info *rf, char input[][16], u32 *_used,  char *output, u32 *_out_len);
+void halrf_scanf(char *in, enum rf_scanf_type type, u32 *out);
+void halrf_txgapk_dbg_cmd(struct rf_info *rf, char input[][16], u32 *_used, char *output, u32 *_out_len);
+void halrf_dump_rf_reg_cmd(struct rf_info *rf, char input[][16], u32 *_used, char *output, u32 *_out_len);
+void halrf_thermal_cmd(struct rf_info *rf, char input[][16], u32 *_used, char *output, u32 *_out_len);
+void halrf_hwtx_dbg_cmd(struct rf_info *rf, char input[][16], u32 *_used, char *output, u32 *_out_len);
+void halrf_kfree_dbg_cmd(struct rf_info *rf, char input[][16], u32 *_used, char *output, u32 *_out_len);
+void halrf_chl_rfk_dbg_cmd(struct rf_info *rf, char input[][16], u32 *_used, char *output, u32 *_out_len);
+#ifdef HALRF_OP5K_SUPPORT
+void halrf_op5k_dbg_cmd(struct rf_info *rf, char input[][16], u32 *_used, char *output, u32 *_out_len);
+#endif
+void halrf_rfk_dbg_cmd(struct rf_info *rf, char input[][16], u32 *_used, char *output, u32 *_out_len);
+
+#ifdef HALRF_PSD_SUPPORT
+void halrf_psd_cmd(struct rf_info *rf, char input[][16], u32 *_used, char *output, u32 *_out_len);
+#endif	/*HALRF_PSD_SUPPORT*/
+
+void halrf_dz_dbg_cmd(struct rf_info *rf, char input[][16], u32 *_used, char *output, u32 *_out_len);
+void halrf_ft_rfq_cmd(struct rf_info *rf, char input[][16], u32 *_used, char *output, u32 *_out_len);
+void halrf_lps_cfg_cmd(struct rf_info *rf, char input[][16], u32 *_used, char *output, u32 *_out_len);
+void halrf_tas_dbg_cmd(struct rf_info *rf, char input[][16], u32 *_used, char *output, u32 *_out_len);
+
+#endif

3rd/devourer/hal/halrf/g6/vendor/halrf_dbg_cmd.h

@@ -0,0 +1,39 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2019 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef _HALRF_DBG_CMD_H_
+#define _HALRF_DBG_CMD_H_
+/*@--------------------------[Define] ---------------------------------------*/
+#define	RF_MAX_ARGC		20
+#define	RF_MAX_ARGV		16
+
+#define HALRF_SCAN halrf_scanf
+#define HALRF_DCMD_SCAN_LIMIT 10
+/*@--------------------------[Enum]------------------------------------------*/
+ enum rf_scanf_type
+{
+	DCMD_DECIMAL	= 1,
+	DCMD_HEX	= 2,
+	DCMD_CHAR	= 3,
+};
+/*@--------------------------[Structure]-------------------------------------*/
+
+struct rf_dbg_cmd_info {
+	u8 cmd_size;
+};
+
+/*@--------------------------[Prptotype]-------------------------------------*/
+void halrf_cmd_parser_init(struct rf_info *rf);
+
+#endif

3rd/devourer/hal/halrf/g6/vendor/halrf_dbg_cmd_ex.h

@@ -0,0 +1,37 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2020  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#ifndef __HALRF_DBG_CMD_EX_H__
+#define __HALRF_DBG_CMD_EX_H__
+#define	RF_MAX_ARGV		16
+
+struct rf_info;
+
+s32 halrf_cmd(struct rf_info *rf, char *input, char *output, u32 out_len);
+
+void halrf_cmd_parser(struct rf_info *rf, char input[][RF_MAX_ARGV],
+		      u32 input_num, char *output, u32 out_len);
+
+#endif

3rd/devourer/hal/halrf/g6/vendor/halrf_dpk.h

@@ -0,0 +1,119 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2019 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __HALRF_DPK_H__
+#define __HALRF_DPK_H__
+
+/*@--------------------------Define Parameters-------------------------------*/
+#define AVG_THERMAL_NUM_DPK 8
+#define THERMAL_DPK_AVG_NUM 1
+#define DPK_BKUP_NUM 2
+
+enum dpk_id {
+	LBK_RXIQK	= 0x06,
+	SYNC		= 0x10,
+	MDPK_IDL	= 0x11,
+	MDPK_MPA	= 0x12,
+	GAIN_LOSS	= 0x13,
+	GAIN_CAL	= 0x14,
+	DPK_RXAGC	= 0x15,
+	KIP_PRESET	= 0x16,
+	KIP_RESTORE	= 0x17,
+	DPK_TXAGC	= 0x19,
+	D_KIP_PRESET	= 0x28,
+	D_TXAGC		= 0x29,
+	D_RXAGC		= 0x2a,
+	D_SYNC		= 0x2b,
+	D_GAIN_LOSS	= 0x2c,
+	D_MDPK_IDL	= 0x2d,
+	D_MDPK_LDL	= 0x2e,
+	D_GAIN_NORM	= 0x2f,
+	D_KIP_THERMAL	= 0x30,
+	D_KIP_RESTORE	= 0x31
+};
+
+struct dpk_bkup_para {
+	enum band_type	band;		/* 2.4G,5G,6G*/
+	enum channel_width	bw;
+	u8	ch;
+	u8	path_ok;
+	u8	txagc_dpk;		/*txagc@dpk with path*/	
+	u8	ther_dpk;		/*thermal@dpk with path*/	
+	//u8	trk_idx_dpk;		/*track_idx@dpk with path*/	
+	//u8	ther_tssi;		/*thermal@tssi with path*/
+	u8	gs;
+	u16	pwsf;
+};
+
+/*@---------------------------End Define Parameters---------------------------*/
+
+struct halrf_dpk_info {
+
+	bool	is_dpk_enable;
+	bool	is_dpk_track_en;
+	bool	is_dpk_reload_en;
+	bool	is_dpk_pwr_unlmt;
+	bool	is_limited_txagc[KPATH];
+	u8	dpk_gs[2];			/*PHY*/
+	u8	ther_avg[KPATH][AVG_THERMAL_NUM_DPK];	/*path*/
+	u8	pre_pwsf[KPATH];
+	u8	ther_avg_idx;
+	u32	dpk_cal_cnt;
+	u32	dpk_ok_cnt;
+	u32	dpk_reload_cnt;
+	u16	dc_i[KPATH][DPK_BKUP_NUM];		/*path*/
+	u16	dc_q[KPATH][DPK_BKUP_NUM];		/*path*/
+	u8	corr_val[KPATH][DPK_BKUP_NUM];		/*path*/
+	u8	corr_idx[KPATH][DPK_BKUP_NUM];		/*path*/
+	u8	cur_idx[KPATH];				/*path*/
+	u8	cur_k_set;
+	u32	dpk_time;
+	u8	max_dpk_txagc[KPATH];
+	u8	ov_flag[KPATH];				/*path*/
+	u32	dpk_sync[KPATH];			/*path*/
+	u8	rxbb_ov[KPATH];				/*path*/
+	u32	rek_cnt[KPATH][2];			/*path/is_first*/
+	u32	rc_mtx[KPATH][434][2];			/*path/addr/rpt*/
+	u32	rx_sram[KPATH][512];			/*path/addr/rpt*/
+	u32	dpk_dciq[KPATH];
+	u32	dpk_pas[KPATH][32];
+	u32	dpk_coef[KPATH][2][28];		/*path/is_first/addr*/
+	s16	dpk_coef_i[2][20];			/*is_first/addr*/
+	s16	dpk_coef_q[2][20];			/*is_first/addr*/
+	u8	c_chk[KPATH];
+	u8	rek_chk[KPATH][2][5];			/*path/is_first/rek_cnt*/
+	u32	dpk_rxiqc[KPATH];			/*path*/
+	u8	dpk_order[KPATH];			/*path*/
+	u8	limited_txagc[KPATH];			/*path*/
+#if 0
+	u8	ov_pa[KPATH];				/*path*/
+	u32	dpk_pwr[KPATH];
+	u32	dpk_frac[KPATH][9];
+	u32	dpk_sync_cfg[KPATH];			/*path*/
+	u32	tpg_setting[KPATH];			/*path*/
+	u32	mdpk_filter_set[KPATH];			/*path*/
+	u32	dpk_sync1[KPATH];			/*path*/
+	u32	dpk_dciq1[KPATH];
+	u32	dpk_pwr1[KPATH];
+	u32	dpk_sync_cfg1[KPATH];			/*path*/
+	u32	dpk_frac1[KPATH][9];
+	u32	tpg_setting1[KPATH];			/*path*/
+	u32	mdpk_filter_set1[KPATH];		/*path*/
+#endif
+
+	struct dpk_bkup_para bp[KPATH][DPK_BKUP_NUM];	/*path/index*/
+};
+
+#endif /*__HALRF_DPK_H__*/
+

3rd/devourer/hal/halrf/g6/vendor/halrf_ex.h

@@ -0,0 +1,447 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2020  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#ifndef __HALRF_EX_H__
+#define __HALRF_EX_H__
+
+struct rf_info;
+
+/**************halrf.c**************/
+void halrf_watchdog(void *rf_void);
+enum rtw_hal_status halrf_chl_rfk_trigger(void *rf_void,
+			   enum phl_phy_idx phy_idx,
+			   enum rfk_tri_type rfk_tri_typ);
+enum rtw_hal_status halrf_chl_rfk_trigger_traditional(void *rf_void,
+			   enum phl_phy_idx phy_idx,
+			   enum rfk_tri_type rfk_tri_typ);
+enum rtw_hal_status halrf_dack_trigger(void *rf_void, bool force);
+enum rtw_hal_status halrf_rx_dck_trigger(void *rf_void,
+				enum phl_phy_idx phy_idx, bool is_afe);
+enum rtw_hal_status halrf_thermal_rx_dck_trigger(void *rf_void,
+				enum phl_phy_idx phy_idx, bool is_afe);
+enum rtw_hal_status halrf_scan_rx_dck_trigger(void *rf_void, enum phl_phy_idx phy_idx,
+				enum rfk_tri_type tri_type);
+enum rtw_hal_status halrf_iqk_trigger(void *rf_void,
+		       enum phl_phy_idx phy_idx,
+		       bool force);
+void halrf_lck_trigger(void *rf_void);
+enum rtw_hal_status halrf_dpk_trigger(void *rf_void,
+		       enum phl_phy_idx phy_idx,
+		       bool force);
+enum rtw_hal_status halrf_tssi_trigger(void *rf_void, enum phl_phy_idx phy_idx, bool hwtx_en);
+void halrf_do_tssi_scan(void *rf_void, enum phl_phy_idx phy_idx);
+void halrf_tssi_enable(void *rf_void, enum phl_phy_idx phy_idx);
+void halrf_tssi_disable(void *rf_void, enum phl_phy_idx phy_idx);
+void halrf_tssi_init(void *rf_void);
+void halrf_tssi_slope_onoff(void *rf_void, u8 tssi_slope_type);
+void halrf_tssi_do_slope(void *rf_void);
+u32 halrf_tssi_get_cw(void *rf_void, enum rf_path path);
+void halrf_tssi_slope_apply(void *rf_void,
+	u32 gain_first, u32 gain_second,
+	u32 cw_first, u32 cw_second, enum rf_path path,
+	u32* gain_diff, u32* cw_diff);
+void halrf_tssi_current_slope_apply(void *rf_void,
+	u32 gain_diff, u32 cw_diff, enum rf_path path);
+void halrf_tssi_finish_slope(void *rf_void);
+u32 halrf_tssi_get_current_power(void *rf_void, enum rf_path path);
+enum rtw_hal_status halrf_gapk_trigger(void *rf_void,
+			enum phl_phy_idx phy_idx, bool force);
+enum rtw_hal_status halrf_gapk_enable(void *rf_void,
+			enum phl_phy_idx phy_idx);
+enum rtw_hal_status halrf_gapk_disable(void *rf_void,
+			enum phl_phy_idx phy_idx);
+void halrf_rck_trigger(void *rf_void, enum phl_phy_idx phy_idx);
+void halrf_iqk_onoff(void *rf_void, bool is_enable);
+void halrf_dpk_onoff(void *rf_void, bool is_enable);
+void halrf_dpk_track_onoff(void *rf_void, bool is_enable);
+void halrf_dpk_switch(void *rf_void, bool is_enable);
+void halrf_dpk_init(void *rf_void);
+void halrf_rx_dck_onoff(void *rf_void, bool is_enable);
+void halrf_rx_dck_track_onoff(void *rf_void, bool is_enable);
+void halrf_rx_dck_init(void *rf_void);
+//void halrf_gapk_onoff(void *rf_void, bool is_enable);
+void halrf_dack_onoff(void *rf_void, bool is_enable);
+void halrf_tssi_onoff(void *rf_void, bool is_enable);
+bool halrf_get_iqk_onoff(void *rf_void);
+bool halrf_get_dpk_onoff(void *rf_void);
+bool halrf_get_dpk_track_onoff(void *rf_void);
+//bool halrf_get_gapk_onoff(void *rf_void);
+bool halrf_get_dack_onoff(void *rf_void);
+bool halrf_get_tssi_onoff(void *rf_void);
+void halrf_lo_test(void *rf_void, bool is_on, enum rf_path path);
+int halrf_get_predefined_pw_lmt_regu_type_from_str(const char *str);
+const char * const *halrf_get_predefined_pw_lmt_regu_type_str_array(u8 *num);
+const char *halrf_get_pw_lmt_regu_type_str(struct rf_info *rf, u8 band);
+int halrf_get_predef_pw_lmt_regu_type_of_band_from_str(enum band_type band, const char *str);
+const char * const *halrf_get_predef_pw_lmt_regu_type_of_band_str_array(enum band_type band, u8 *num);
+u8 halrf_get_regulation_info(struct rf_info *rf, u8 band);
+bool halrf_reg_tbl_exist(struct rf_info *rf, u8 band, u8 reg);
+void halrf_set_reg_tbl_exist(struct rf_info *rf, u8 band, u8 reg);
+void halrf_force_regulation(struct rf_info *rf, bool enable,
+	u8 reg_2g[], u8 reg_2g_len, u8 reg_5g[], u8 reg_5g_len, u8 reg_6g[], u8 reg_6g_len);
+#ifndef RF_8730A_SUPPORT
+u8 halrf_file_regd_ext_search(struct rf_info *rf, u16 domain_code, char *country, int *aidx_match);
+u8 halrf_file_regd_ext_of_band_search(struct rf_info *rf, enum band_type band, u16 domain_code, char *country
+	, enum rtw_power_limit_6g_info cate_6g, int *aidx_match);
+#endif
+u8 halrf_get_tx_tbl_to_tx_pwr_times(struct rf_info *rf);
+s8 halrf_get_power_by_rate(struct rf_info *rf,
+	enum phl_phy_idx phy,
+	u8 rf_path, u16 rate, u8 dcm, u8 offset);
+s8 halrf_get_power_by_rate_band(struct rf_info *rf,
+	enum phl_phy_idx phy, u16 rate, u8 dcm, u8 offset, u32 band);
+s8 halrf_get_power_limit(struct rf_info *rf,
+	enum phl_phy_idx phy, u8 rf_path, u16 rate, u8 bandwidth,
+	u8 beamforming, u8 tx_num, u8 channel);
+s8 halrf_get_power_limit_option(struct rf_info *rf,
+	enum phl_phy_idx phy, u8 rf_path, u16 rate, u8 bandwidth,
+	u8 beamforming, u8 tx_num, u8 channel, u32 band, u8 reg);
+s8 halrf_get_power_limit_ru(struct rf_info *rf,
+	enum phl_phy_idx phy, u8 rf_path, u16 rate, u8 bandwidth,
+	u8 tx_num, u8 channel);
+s8 halrf_get_power_limit_ru_option(struct rf_info *rf,
+	enum phl_phy_idx phy, u8 rf_path, u16 rate, u8 bandwidth,
+	u8 tx_num, u8 channel, u32 band, u8 reg);
+s16 halrf_get_power(void *rf_void,
+	u8 rf_path, u16 rate, u8 dcm, u8 offset, u8 bandwidth,
+	u8 beamforming, u8 channel);
+s16 halrf_get_band_power(void *rf_void, enum phl_phy_idx phy,
+	u8 rf_path, u16 rate, u8 dcm, u8 offset, u8 bandwidth,
+	u8 beamforming, u8 channel);
+s16 halrf_get_power_by_rate_and_limit_ru_smaller(void *rf_void,
+	u8 rf_path, u16 rate, u8 dcm, u8 offset, u8 bandwidth,
+	u8 beamforming, u8 channel, u8 band);
+u8 halrf_get_thermal(void *rf_void, u8 rf_path);
+u8 halrf_get_thermal_without_trigger(void *rf_void, enum phl_phy_idx phy, u8 rf_path);
+u32 halrf_get_tssi_de(void *rf_void, enum phl_phy_idx phy_idx, u8 path);
+s32 halrf_get_online_tssi_de(void *rf_void, enum phl_phy_idx phy_idx, u8 path, s32 dbm, s32 puot);
+void halrf_set_tssi_de_for_tx_verify(void *rf_void, enum phl_phy_idx phy_idx, u32 tssi_de, u8 path);
+void halrf_set_tssi_de_offset(void *rf_void, enum phl_phy_idx phy_idx, u32 tssi_de_offset, u8 path);
+void halrf_set_tssi_avg_mp(void *rf_void, enum phl_phy_idx phy_idx, s32 xdbm);
+
+void halrf_set_rx_gain_offset_for_rx_verify(void *rf_void, enum phl_phy_idx phy,
+					s8 rx_gain_offset, u8 path);
+void halrf_set_power_track(void *rf_void, enum phl_phy_idx phy_idx, u8 value);
+u8 halrf_get_power_track(void *rf_void);
+u8 halrf_get_power_track_phy(void *rf_void, enum phl_phy_idx phy_idx);
+void halrf_tssi_get_efuse_ex(void *rf_void, enum phl_phy_idx phy_idx);
+bool halrf_tssi_check_efuse_data(void *rf_void, enum phl_phy_idx phy_idx);
+void halrf_set_ref_power_to_struct(void *rf_void, enum phl_phy_idx phy_idx);
+bool halrf_set_power_constraint (void *rf_void, enum phl_phy_idx phy_idx, u16 mb, bool apply_to_hw);
+bool halrf_control_tx_rate_power (void *rf_void, enum phl_phy_idx phy_idx, s32 mb);
+s8 halrf_get_pwr_by_rate_bw_control(struct rf_info *rf, enum phl_phy_idx phy, u16 rate, u32 band, s8 pwr_by_rate);
+void halrf_set_bw_power_by_rate_offset(void *rf_void, u32 pwr_by_rate_bw_ofst);
+void halrf_bf_config_rf(void *rf_void);
+void halrf_rfk_reg_backup(void *rf_void);
+void halrf_rfc_reg_backup(void *rf_void);
+bool halrf_rfc_reg_check_fail(void *rf_void);
+bool halrf_rfk_reg_check_fail(void *rf_void);
+bool halrf_dack_reg_check_fail(void *rf_void);
+bool halrf_rfk_chl_thermal(void *rf_void, u8 chl_index, u8 ther_index);
+void halrf_rfk_recovery_chl_thermal(void *rf_void, u8 chl_index);
+u8 halrf_fcs_get_thermal_index(void *rf_void);
+
+/**************halrf_init.c**************/
+enum rtw_hal_status halrf_dm_init(void *rf_void);
+enum rtw_hal_status  halrf_init(struct rtw_phl_com_t *phl_com,
+				struct rtw_hal_com_t *hal_com, void **rf_out);
+void halrf_deinit(struct rtw_phl_com_t *phl_com,
+		  struct rtw_hal_com_t *hal_com, void *rf);
+enum rtw_hal_status halrf_ic_cfg_init(void *rf_void);
+/**************halrf_hw_cfg.c**************/
+bool halrf_config_store_power_limit(void *rf_void);
+bool halrf_config_store_power_limit_ru(void *rf_void);
+bool halrf_config_radio(void *rf_void, enum phl_phy_idx phy);
+void halrf_config_rf_parameter(void *rf_void, enum phl_phy_idx phy);
+
+//void halrf_gapk_save_tx_gain(struct rf_info *rf);
+//void halrf_gapk_reload_tx_gain(struct rf_info *rf);
+/*******************************************/
+void halrf_dack_recover(void *rf_void,
+			u8 offset,
+			enum rf_path path,
+			u32 val,
+			bool reload);
+
+bool halrf_set_power(struct rf_info *rf, enum phl_phy_idx phy,
+	enum phl_pwr_table pwr_table);
+
+bool halrf_get_efuse_power_table_switch(struct rf_info *rf, enum phl_phy_idx phy_idx);
+
+void halrf_set_power_limit_to_struct(struct rf_info *rf, enum phl_phy_idx phy);
+
+void halrf_set_power_limit_ru_to_struct(struct rf_info *rf, enum phl_phy_idx phy);
+
+bool halrf_get_efuse_power_table_switch(struct rf_info *rf, enum phl_phy_idx phy_idx);
+
+void halrf_set_power_table_switch(struct rf_info *rf,
+	enum phl_phy_idx phy, u8 pwr_by_rate, u8 pwr_limt);
+
+bool halrf_get_efuse_info(void *rf_void, u8 *efuse_map,
+		       enum rtw_efuse_info id, void *value, u32 length,
+		       u8 autoload_status);
+
+bool halrf_set_dbcc(void *rf_void, bool dbcc_en);
+
+void halrf_wlan_tx_power_control(void *rf_void, enum phl_phy_idx phy,
+	enum phl_pwr_ctrl pwr_ctrl_idx, u32 tx_power_val, bool enable);
+
+bool halrf_wl_tx_power_control(void *rf_void, u32 tx_power_val);
+
+void halrf_get_efuse_rx_gain_k(void *rf_void, enum phl_phy_idx phy_idx);
+
+void halrf_get_efuse_trim(void *rf_void, enum phl_phy_idx phy_idx);
+
+void halrf_do_rx_gain_k(void *rf_void, enum phl_phy_idx phy_idx);
+
+enum rtw_hal_status halrf_dpk_tracking(void *rf_void);
+
+enum rtw_hal_status halrf_tssi_tracking(void *rf_void);
+
+enum rtw_hal_status halrf_tssi_tracking_clean(void *rf_void, s16 power_dbm);
+
+u8 halrf_get_default_rfe_type(void *rf_void);
+
+u8 halrf_get_default_xtal(void *rf_void);
+
+void halrf_power_limit_set_ext_pwr_limit_table(struct rf_info *rf,
+						enum phl_phy_idx phy);
+
+void halrf_power_limit_set_ext_pwr_limit_ru_table(struct rf_info *rf,
+						enum phl_phy_idx phy);
+enum rtw_hal_status halrf_iqk_tracking(void *rf_void);
+
+bool halrf_iqk_get_ther_rek(void *rf_void);
+
+void halrf_psd_init(void *rf_void, enum phl_phy_idx phy,
+			u8 path, u8 iq_path, u32 avg, u32 fft);
+			
+void halrf_psd_restore(void *rf_void, enum phl_phy_idx phy);	
+			
+u32 halrf_psd_get_point_data(void *rf_void, enum phl_phy_idx phy, s32 point);
+			
+void halrf_psd_query(void *rf_void, enum phl_phy_idx phy,
+			u32 point, u32 start_point, u32 stop_point, u32 *outbuf);
+
+void halrf_config_radio_to_fw(void *rf_void);
+
+void halrf_set_fix_power_to_struct(void *rf_void,
+					enum phl_phy_idx phy, s8 dbm);
+
+void halrf_pwr_by_rate_info(struct rf_info *rf,
+		char input[][16], u32 *_used, char *output, u32 *_out_len, enum phl_phy_idx phy);
+
+void halrf_pwr_limit_info(struct rf_info *rf,
+		char input[][16], u32 *_used, char *output, u32 *_out_len, enum phl_phy_idx phy);
+
+void halrf_pwr_limit_ru_info(struct rf_info *rf,
+		char input[][16], u32 *_used, char *output, u32 *_out_len, enum phl_phy_idx phy);
+
+void halrf_get_tssi_info(struct rf_info *rf, char input[][16], u32 *_used,
+			 char *output, u32 *_out_len);
+void halrf_get_tssi_trk_info(struct rf_info *rf, char input[][16], u32 *_used,
+			 char *output, u32 *_out_len);
+
+void halrf_set_tx_shape(struct rf_info *rf, u8 tx_shape_idx);
+
+void halrf_disconnect_notify(void *rf_void, struct rtw_chan_def *chandef);
+bool halrf_check_mcc_ch(void *rf_void, struct rtw_chan_def *chandef);
+void halrf_ctl_bw(void *rf_void, enum phl_phy_idx phy, enum channel_width bw);
+void halrf_ctl_ch(void *rf_void, enum phl_phy_idx phy, u8 central_ch, enum band_type band);
+void halrf_ctl_band_ch_bw(void *rf_void, enum phl_phy_idx phy, enum band_type band, u8 central_ch, enum channel_width bw);
+void halrf_rxbb_bw(void *rf_void, enum phl_phy_idx phy, enum channel_width bw);
+void halrf_ctrl_bw_ch(void *rf_void, enum phl_phy_idx phy, u8 central_ch,
+				enum band_type band, enum channel_width bw);
+void  halrf_fw_ntfy(void *rf_void, enum phl_phy_idx phy_idx);
+u32 halrf_get_nctl_reg_ver(struct rf_info *rf);
+u32 halrf_get_radio_reg_ver(struct rf_info *rf);
+u32 halrf_get_radio_ver_from_reg(struct rf_info *rf);
+u32 halrf_get_extra_para_ver_from_reg(struct rf_info *rf);
+u32 halrf_get_rfe_type_ver_from_reg(struct rf_info *rf);
+u32 halrf_get_fem_id_from_reg(struct rf_info *rf);
+void halrf_config_nctl_reg(struct rf_info *rf);
+void halrf_set_gpio(void *rf_void, enum phl_phy_idx phy, u8 band);
+void halrf_set_gpio_by_ch(void *rf_void, enum phl_phy_idx phy, u8 band);
+bool halrf_check_efem(void *rf_void, enum phl_phy_idx phy_idx);
+void halrf_set_regulation_from_driver(void *rf_void, u8 regulation_idx);
+void halrf_set_regulation_init(void *rf_void, enum phl_phy_idx phy_idx);
+void halrf_tssi_default_txagc(void *rf_void,
+				enum phl_phy_idx phy_idx, bool enable);
+void halrf_tssi_set_avg(void *rf_void,
+			enum phl_phy_idx phy_idx, bool enable);
+void halrf_wifi_event_notify(void *rf_void,
+			enum phl_msg_evt_id event, enum phl_phy_idx phy_idx);
+void halrf_2g_rxant(void *rf_void, enum halrf_ant ant);
+s8 halrf_get_ther_protected_threshold(void *rf_void);
+
+void halrf_tssi_set_efuse_to_de(void *rf_void,
+					enum phl_phy_idx phy_idx);
+
+void halrf_tssi_scan_ch(void *rf_void, enum rf_path path);
+
+void halrf_tssi_scan_setting_ch(void *rf_void,
+	enum phl_phy_idx phy_idx, enum rf_path path);
+
+void halrf_tssi_cck_by_pass(void *rf_void,
+			enum phl_phy_idx phy, bool by_pass_en);
+
+bool halrf_mac_set_pwr_reg(void *rf_void, enum phl_phy_idx phy,
+	u32 addr, u32 mask, u32 val);
+
+u32 halrf_mac_get_pwr_reg(void *rf_void, enum phl_phy_idx phy,
+	u32 addr, u32 mask);
+
+s8 halrf_xtal_tracking_offset(void *rf_void, enum phl_phy_idx phy_idx);
+
+void halrf_hw_tx(void *rf_void, u8 path, u16 cnt, s16 dbm, u32 rate, u8 bw,
+				bool enable);
+
+void halrf_kfree_get_info(void *rf_void, char input[][16], u32 *_used,
+			 char *output, u32 *_out_len);
+
+void halrf_set_mp_regulation(void *rf_void, enum phl_phy_idx phy, u8 regulation);
+u32 halrf_tssi_get_final(void *rf_void, enum phl_phy_idx phy_idx, u8 path);
+
+void halrf_tssi_backup_txagc(struct rf_info *rf, enum phl_phy_idx phy, bool enable);
+
+u32 halrf_get_rfk_cap(void *rf_void);
+
+void halrf_syn1_onoff(void *rf_void, enum phl_phy_idx phy, u8 path, bool syn1_turn_on);
+
+void halrf_reload_pwr_limit_tbl_and_set(struct rf_info *rf,
+	enum phl_phy_idx phy, enum phl_pwr_table pwr_table);
+
+void halrf_rfk_reg_reload(void *rf_void);
+
+u32 halrf_test_event_trigger(void *rf_void,
+	enum phl_phy_idx phy, enum halrf_event_idx idx, enum halrf_event_func func);
+void halrf_rfe_ant_num_chk(void *rf_void);
+
+bool halrf_check_if_dowatchdog(void *rf_void);
+
+#ifdef HALRF_OP5K_SUPPORT
+void halrf_op5k_init(void *rf_void);
+
+void halrf_op5k_trigger(void *rf_void);
+
+void halrf_op5k_trigger_by_bw(void *rf_void, enum channel_width bw);
+#endif
+
+void halrf_set_tpe_control(struct rf_info *rf);
+
+void halrf_set_tpe_control_dbcc(struct rf_info *rf, enum phl_phy_idx phy);
+
+bool halrf_tpe_is_required(struct rtw_tpe_info_t *tpe_info);
+
+bool halrf_check_tpe_allow(struct rf_info *rf, struct rtw_tpe_info_t *tpe_info);
+
+u32 halrf_get_iqk_times(void *rf_void);
+
+u32 halrf_get_lck_times(void *rf_void);
+
+void halrf_cfg_radio_b_w_bt_status(void *rf_void, bool bt_connect);
+
+void halrf_adie_pow_ctrl(void *rf_void, bool rf_off, bool others_off);
+
+void halrf_afe_pow_ctrl(void *rf_void, bool adda_off, bool pll_off);
+
+void halrf_set_dynamic_ant_gain(struct rf_info *rf,
+	enum phl_phy_idx phy, struct rtw_phl_regu_dyn_ant_gain *regu);
+
+void halrf_set_pwr_lmt_main_or_aux(void *rf_void, u8 ant);
+
+void halrf_set_ext_ant12_pwr_limit_table(void *rf_void, enum phl_phy_idx phy);
+
+void halrf_set_ext_ant12_pwr_limit_ru_table(void *rf_void, enum phl_phy_idx phy);
+
+void halrf_aack_trigger(void *rf_void, enum phl_phy_idx phy_idx);
+
+void halrf_set_ant_main_or_aux(void *rf_void, enum rf_path path, bool main);
+
+u32 halrf_c2h_parsing(struct rf_info *rf, u8 classid, u8 cmdid, u16 len, u8 *c2h);
+
+#ifdef  HALRF_DZ_LOG
+void halrf_ex_rt_rfk_info(struct rf_info *rf);
+#endif
+
+void halrf_ex_rfk_info(struct rf_info *rf);
+
+u8 halrf_max_path_num(struct rf_info *rf);
+
+void halrf_set_scan_power_table_to_fw(struct rf_info *rf);
+
+bool halrf_get_dpk_by_rate(void *rf_void,
+	enum phl_phy_idx phy, enum packet_format_t vector_index, u32 rate_index);
+
+void halrf_set_dpk_by_rate(void *rf_void,
+	enum phl_phy_idx phy, enum packet_format_t vector_index, u32 rate_index);
+
+void halrf_wowlan_config(void *rf_void, enum phl_phy_idx phy_idx);
+
+u32 halrf_get_regulation_max_num(struct rf_info * rf, enum band_type band);
+
+u32 halrf_get_regulation_null_num(struct rf_info * rf);
+
+u32 halrf_get_regulation_na_num(struct rf_info * rf);
+
+s8 halrf_get_power_limit_value_ww(struct rf_info * rf);
+
+s8 halrf_get_power_limit_value_na(struct rf_info * rf);
+
+void halrf_power_by_rate_store_to_array(struct rf_info *rf,
+			u32 band, u32 tx_num, u32 rate_id, u32 data);
+void halrf_power_limit_store_to_array(struct rf_info *rf,
+			u8 regulation, u8 band, u8 bandwidth, u8 rate,
+			u8 tx_num, u8 beamforming, u8 chnl, s8 val);
+void halrf_power_limit_shape_store_to_array(struct rf_info *rf,
+			u8 regulation, u8 band, u8 bandwidth, u8 rate,
+			u8 tx_num, u8 beamforming, u8 val);
+void halrf_power_limit_ru_store_to_array(struct rf_info *rf,
+			u8 band, u8 bandwidth, u8 tx_num, u8 rate,
+			u8 regulation, u8 chnl, s8 val);
+void halrf_power_limit_ru_shape_store_to_array(struct rf_info *rf,
+			u8 band, u8 bandwidth, u8 tx_num, u8 rate,
+			u8 regulation, u8 val);
+void halrf_config_limit_default_option(struct rf_info *rf, u8 band_bitmap
+	, enum phl_pwr_table pwr_table);
+
+// FCS
+void halrf_fcs_backup(struct rf_info *rf, u32 chl_index);
+void halrf_fcs_reload(struct rf_info *rf, u32 chl_index);
+bool halrf_fcs_reloadk_check(struct rf_info *rf);
+void halrf_fcs_trigger(struct rf_info *rf, u32 chl_index, bool reloadk);
+
+//FT
+bool halrf_check_ft_result(void *rf_void);
+bool halrf_SRAM_MBIST_normal(void *rf_void);
+bool halrf_SRAM_MBIST_DS(void *rf_void);
+
+/*TAS*/
+void halrf_tas_start(struct rf_info *rf);
+void halrf_tas_stop(struct rf_info *rf);
+void halrf_update_tas_def_setting(struct rf_info *rf, u32 tas_config);
+u32 halrf_c2h_parsing(struct rf_info *rf, u8 classid, u8 cmdid, u16 len, u8 *c2h);
+
+#endif

3rd/devourer/hal/halrf/g6/vendor/halrf_export_fun.h

@@ -0,0 +1,38 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2020  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+#ifndef __HALRF_EXPORT_FUN_H__
+#define __HALRF_EXPORT_FUN_H__
+#if 1
+#include "halrf_ic_hw_info.h"
+#include "halrf_hw_cfg_ex.h"
+#include "halrf_init_ex.h"
+#include "halrf_ex.h"
+#include "halrf_dbg_cmd_ex.h"
+#ifdef RF_8852A_SUPPORT
+#include "halrf_8852a/halrf_8852a_api_ex.h"
+#endif
+#endif
+#endif
+

3rd/devourer/hal/halrf/g6/vendor/halrf_headers.h

@@ -0,0 +1,20 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2019 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef _HALRF_HEADERS_H_
+#define _HALRF_HEADERS_H_
+#include "../../hal_headers_le.h"
+#include "halrf_struct.h"
+
+#endif /*_HALRF_HEADERS_H_*/

3rd/devourer/hal/halrf/g6/vendor/halrf_hw_cfg.h

@@ -0,0 +1,40 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2020  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+#ifndef __HALRF_HW_CFG_H__
+#define __HALRF_HW_CFG_H__
+
+/*@--------------------------[Define] ---------------------------------------*/
+
+/*@--------------------------[Enum]------------------------------------------*/
+ 
+/*@--------------------------[Structure]-------------------------------------*/
+
+/*@--------------------------[Prptotype]-------------------------------------*/
+
+bool halrf_config_power_limit(void *rf_void, enum phl_phy_idx phy);
+
+bool halrf_config_power_limit_ru(void *rf_void, enum phl_phy_idx phy);
+
+#endif

3rd/devourer/hal/halrf/g6/vendor/halrf_hw_cfg_ex.h

@@ -0,0 +1,39 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2020  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+#ifndef _HALRF_HW_CFG_EX_H_
+#define _HALRF_HW_CFG_EX_H_
+
+/*@--------------------------[Define] ---------------------------------------*/
+
+/*@--------------------------[Enum]------------------------------------------*/
+
+/*@--------------------------[Structure]-------------------------------------*/
+
+/*@--------------------------[Prptotype]-------------------------------------*/
+struct rf_info;
+bool halrf_config_power_limit_6g(void *rf_void, enum phl_phy_idx phy);
+bool halrf_config_power_limit_ru_6g(void *rf_void, enum phl_phy_idx phy);
+
+#endif

3rd/devourer/hal/halrf/g6/vendor/halrf_hwimg.h

@@ -0,0 +1,43 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2020  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+#ifndef _HALRF_HWIMG_H_
+#define _HALRF_HWIMG_H_
+
+#define RADIO_TO_FW_PAGE_SIZE 6
+#define RADIO_TO_FW_DATA_SIZE 500
+
+struct halrf_radio_info {
+	u32 write_times_a;
+	u32 write_times_b;
+	u32 radio_a_parameter[RADIO_TO_FW_PAGE_SIZE][RADIO_TO_FW_DATA_SIZE];
+	u32 radio_b_parameter[RADIO_TO_FW_PAGE_SIZE][RADIO_TO_FW_DATA_SIZE];
+	bool radio_a_form_folder;
+	bool radio_b_form_folder;
+	bool radio_c_form_folder;
+	bool radio_d_form_folder;
+	bool radio_e_form_folder;
+};
+
+#endif /*  _HALRF_HW_IMG_8852A_H_ */

3rd/devourer/hal/halrf/g6/vendor/halrf_ic_hw_info.h

@@ -0,0 +1,148 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2020  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+#ifndef __HALRF_IC_HW_INFO_H__
+#define __HALRF_IC_HW_INFO_H__
+
+enum halrf_ic {
+	RF_RTL8852A	=	BIT(0),
+	RF_RTL8852B	=	BIT(1),
+	RF_RTL8834A	=	BIT(2),
+	RF_RTL8852C	=	BIT(3),
+	RF_RTL8832BR	=	BIT(4),
+	RF_RTL8192XB	=	BIT(5),
+	RF_RTL8852BP	=	BIT(6),
+	RF_RTL8730A	=	BIT(7),
+	RF_RTL8720E	=	BIT(8),
+	RF_RTL8851B	=	BIT(9),
+	RF_RTL8922A	=	BIT(10),
+	RF_RTL8832CR_VU	=	BIT(11),	
+	RF_RTL8832BR_VT	=	BIT(12),
+	RF_RTL8852D =	BIT(13),
+	RF_RTL8852BT	=	BIT(14),
+	RF_RTL8832D	=	BIT(15),
+	RF_RTL8852BPT	=	BIT(16),
+	RF_RTL8842A	=	BIT(17),
+};
+
+enum halrf_subdid {
+	RF_SUBDID_RTL8832CRVU = 0xc832,
+	RF_SUBDID_RTL8832BRVT = 0xb83b,
+};
+
+enum halrf_aid {
+	RF_AID_RL6967A = 0x6967
+};
+
+#define RF_N_1SS		0
+#define RF_N_2SS		0
+#define RF_N_3SS		0
+#define RF_N_4SS		0
+
+#define RF_AC_1SS		0
+#define RF_AC_2SS		0
+#define RF_AC_3SS		0
+#define RF_AC_4SS		0
+
+#define RF_AX_1SS		(RF_RTL8851B)
+#define RF_AX_2SS		(RF_RTL8852A | RF_RTL8852B | RF_RTL8852C | RF_RTL8842A |\
+				 RF_RTL8832BR | RF_RTL8192XB | RF_RTL8852BP | RF_RTL8852D | RF_RTL8832D | RF_RTL8852BT | RF_RTL8852BPT)
+#define RF_AX_3SS		0
+#define RF_AX_4SS		(RTL8834A)
+
+/*@====the following macro DO NOT need to update when adding a new IC======= */
+#define RF_1SS		(RF_N_1SS | RF_AC_1SS | RF_AX_1SS)
+#define RF_2SS		(RF_N_2SS | RF_AC_2SS | RF_AX_2SS)
+#define RF_3SS		(RF_N_3SS | RF_AC_3SS | RF_AX_3SS)
+#define RF_4SS		(RF_N_4SS | RF_AC_4SS | RF_AX_4SS)
+
+
+#define RF_N_SERIES		(RF_N_1SS | RF_N_2SS | RF_N_3SS |\
+				 RF_N_4SS)
+#define RF_AC_SERIES	(RF_AC_1SS | RF_AC_2SS |\
+				 RF_AC_3SS | RF_AC_4SS)
+#define RF_AX_SERIES	(RF_AX_1SS | RF_AX_2SS |\
+				 RF_AX_3SS | RF_AX_4SS)
+/*@==========================================================================*/
+#if (defined(RF_8851B_SUPPORT))
+#define KIP_REG 3264
+#elif (defined(RF_8852C_SUPPORT) || defined(RF_8842A_SUPPORT) || defined(RF_8852D_SUPPORT) || defined(RF_8832D_SUPPORT) || defined(RF_8852BP_SUPPORT))
+#define KIP_REG 3136
+#elif (defined (RF_8852B_SUPPORT) || defined (RF_8852BT_SUPPORT) || defined (RF_8852BPT_SUPPORT))
+#define KIP_REG 2560
+#else
+#define KIP_REG 2048
+#endif
+
+#if defined(RF_8834A_SUPPORT)
+#define KPATH 4
+#elif (defined(RF_8852A_SUPPORT) || defined(RF_8852B_SUPPORT) ||\
+       defined(RF_8852C_SUPPORT) || defined(RF_8842A_SUPPORT) || defined(RF_8832BR_SUPPORT) ||\
+       defined(RF_8192XB_SUPPORT) || defined(RF_8852BP_SUPPORT) || defined(RF_8852D_SUPPORT) || defined(RF_8832D_SUPPORT) || defined(RF_8852BT_SUPPORT) || defined(RF_8852BPT_SUPPORT))
+#define KPATH 2
+#else
+#define KPATH 1
+#endif
+
+/*@==========================================================================*/
+
+/*@==========================================================================*/
+
+
+
+/*@==========================================================================*/
+
+/****************************************************************
+ * 1 ============================================================
+ * 1  enumeration
+ * 1 ============================================================
+ ***************************************************************/
+
+enum rf_path_bit {
+	RF_A	= BIT(0),
+	RF_B	= BIT(1),
+	RF_C	= BIT(2),
+	RF_D	= BIT(3),
+
+	RF_AB	= (RF_A | RF_B),
+	RF_AC	= (RF_A | RF_C),
+	RF_AD	= (RF_A | RF_D),
+	RF_BC	= (RF_B | RF_C),
+	RF_BD	= (RF_B | RF_D),
+	RF_CD	= (RF_C | RF_D),
+
+	RF_ABC	= (RF_A | RF_B | RF_C),
+	RF_ABD	= (RF_A | RF_B | RF_D),
+	RF_ACD	= (RF_A | RF_C | RF_D),
+	RF_BCD	= (RF_B | RF_C | RF_D),
+
+	RF_ABCD	= (RF_A | RF_B | RF_C | RF_D),
+};
+
+enum halrf_ant {
+	RF_MAIN_ANT	= 1,
+	RF_AUX_ANT	= 2,
+};
+
+#endif

3rd/devourer/hal/halrf/g6/vendor/halrf_ic_sw_info.h

@@ -0,0 +1,42 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2020  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+#ifndef __HALRF_IC_SW_INFO_H__
+#define __HALRF_IC_SW_INFO_H__
+
+#define HLARF_CODE_BASE			"HALRF_TRUNK"
+#define HALRF_RELEASE_DATE		"20200106.0"
+
+
+/****************************************************************
+ * 1 ============================================================
+ * 1  enumeration
+ * 1 ============================================================
+ ***************************************************************/
+
+enum halrf_api_host {
+	RUN_IN_FW		= 0,
+	RUN_IN_DRIVER		= 1
+};
+#endif

3rd/devourer/hal/halrf/g6/vendor/halrf_init.c

@@ -0,0 +1,815 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2019 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#include "halrf_precomp.h"
+
+void halrf_show_rf_ic_info(struct rf_info *rf) 
+{
+	char *ic_name = NULL;
+	
+	switch (rf->ic_type) {
+#ifdef RF_8852A_SUPPORT
+	case RF_RTL8852A:
+		ic_name = "RF_RTL8852A";
+	break;
+#endif
+#ifdef RF_8852B_SUPPORT
+	case RF_RTL8852B:
+		ic_name = "RF_RTL8852B";
+	break;
+#endif
+#ifdef RF_8852C_SUPPORT
+	case RF_RTL8852C:
+		ic_name = "RF_RTL8852C";
+		break;
+#endif
+#ifdef RF_8842A_SUPPORT
+	case RF_RTL8842A:
+		ic_name = "RF_RTL8842A";
+		break;
+#endif
+#ifdef RF_8852D_SUPPORT
+	case RF_RTL8852D:
+		ic_name = "RF_RTL8852D";
+		break;
+#endif
+#ifdef RF_8832D_SUPPORT
+	case RF_RTL8832D:
+		ic_name = "RF_RTL8832D";
+		break;
+#endif
+
+#ifdef RF_8832BR_SUPPORT
+	case RF_RTL8832BR:
+		ic_name = "RF_RTL8832BR";
+	break;
+#endif
+#ifdef RF_8192XB_SUPPORT
+	case RF_RTL8192XB:
+		ic_name = "RF_RTL8192XB";
+	break;
+#endif
+#ifdef RF_8852BP_SUPPORT
+	case RF_RTL8852BP:
+		ic_name = "RF_RTL8852BP";
+	break;
+#endif
+#ifdef RF_8832CRVU_SUPPORT
+	case RF_RTL8832CR_VU:
+		ic_name = "RF_RTL8832CR_VU";
+		break;
+#endif
+#ifdef RF_8832BRVT_SUPPORT
+	case RF_RTL8832BR_VT:
+		ic_name = "RF_RTL8832BR_VT";
+	break;
+#endif
+
+	default:
+		ic_name = "no_info";
+	break;
+	}
+	RF_DBG(rf, DBG_RF_INIT, "[HALRF] rf->ic_type = %s\n", ic_name);
+}
+void halrf_cmn_info_self_init(struct rf_info *rf)
+{
+	struct rtw_hal_com_t *hal_i = rf->hal_com;
+	#ifdef CONFIG_RTL8852D
+	RF_DBG(rf, DBG_RF_INIT, "[HALRF] CONFIG_RTL8852D is defined !!\n");
+	#endif
+	
+	#ifdef CONFIG_RTL8832D
+	RF_DBG(rf, DBG_RF_INIT, "[HALRF] CONFIG_RTL8832D is defined !!\n");
+	#endif
+
+	RF_TRACE("hal_i->chip_id = %d !!\n", hal_i->chip_id);
+
+	if (hal_i->chip_id == CHIP_WIFI6_8852A)
+		rf->ic_type = RF_RTL8852A;
+	else if (hal_i->chip_id == CHIP_WIFI6_8834A)
+		rf->ic_type = RF_RTL8834A;
+	else if (hal_i->chip_id == CHIP_WIFI6_8852B)
+		rf->ic_type = RF_RTL8852B;
+
+#ifdef RF_8852C_SUPPORT
+	else if (hal_i->chip_id == CHIP_WIFI6_8852C)
+		rf->ic_type = RF_RTL8852C;
+#endif
+
+#ifdef RF_8842A_SUPPORT
+	else if (hal_i->chip_id == CHIP_WIFI6_8842A) {
+		if (hal_i->aid == RF_AID_RL6967A) 
+			rf->ic_type = RF_RTL8842A; //B cut
+		else
+			rf->ic_type = RF_RTL8852C; //A cut
+	}
+#endif
+
+#if defined (RF_8852D_SUPPORT) || defined (RF_8832D_SUPPORT)
+	else if (hal_i->chip_id == CHIP_WIFI6_8852D) {
+	#ifdef PHL_PLATFORM_AP
+		rf->ic_type = RF_RTL8832D;
+	#else
+		if (hal_i->aid == RF_AID_RL6967A)
+			rf->ic_type = RF_RTL8832D;
+		else
+			rf->ic_type = RF_RTL8852D;
+	#endif
+		RF_TRACE("hal_i->aid = 0x%x, RF_AID_RL6967A = 0x%x !!\n",hal_i->aid, RF_AID_RL6967A);
+	}
+#endif
+	else if (hal_i->chip_id == CHIP_WIFI6_8852BT)
+		rf->ic_type = RF_RTL8852BT;
+	else if (hal_i->chip_id == CHIP_WIFI6_8852BPT)
+		rf->ic_type = RF_RTL8852BPT;
+
+#ifdef RF_8832BR_SUPPORT
+	if (hal_i->chip_id == CHIP_WIFI6_8832BR)
+		rf->ic_type = RF_RTL8832BR;
+#endif
+#ifdef RF_8192XB_SUPPORT
+	if (hal_i->chip_id == CHIP_WIFI6_8192XB)
+		rf->ic_type = RF_RTL8192XB;
+#endif
+#ifdef RF_8852BT_SUPPORT
+	else if (hal_i->chip_id == CHIP_WIFI6_8852BT)
+		rf->ic_type = RF_RTL8852BT;
+#endif
+#ifdef RF_8852BPT_SUPPORT
+	else if (hal_i->chip_id == CHIP_WIFI6_8852BPT)
+		rf->ic_type = RF_RTL8852BPT;
+#endif
+#ifdef RF_8852BP_SUPPORT
+	else if (hal_i->chip_id == CHIP_WIFI6_8852BP)
+		rf->ic_type = RF_RTL8852BP;
+#endif
+
+#ifdef RF_8730A_SUPPORT
+	if (hal_i->chip_id == CHIP_WIFI6_8730A)
+		rf->ic_type = RF_RTL8730A;
+#endif
+
+#ifdef RF_8851B_SUPPORT
+	if (hal_i->chip_id == CHIP_WIFI6_8851B)
+		rf->ic_type = RF_RTL8851B;
+#endif
+
+	RF_TRACE("rf->ic_type = 0x%x !!\n",rf->ic_type);
+
+	if (rf->ic_type & RF_AX_1SS)
+		rf->num_rf_path = 1;
+	else if (rf->ic_type & RF_AX_2SS)
+		rf->num_rf_path = 2;
+#if RF_AX_3SS
+	else if (rf->ic_type & RF_AX_3SS)
+		rf->num_rf_path = 3;
+#endif
+	else if (rf->ic_type & RF_AX_4SS)
+		rf->num_rf_path = 4;
+	else
+		rf->num_rf_path = 1;
+
+	rf->support_ability = 0xffffffff;
+	rf->rf_init_ready = false;
+	rf->rf_sys_up_time = 0;
+	rf->rf_watchdog_en = true;
+	rf->rf_ic_api_en = true;
+	
+
+	//log
+	halrf_show_rf_ic_info(rf);
+	/*@=== [HALRF Structure] ============================================*/
+
+	switch (rf->ic_type) {
+#ifdef RF_8852A_SUPPORT
+	case RF_RTL8852A:
+		rf->rfk_iqk_info = &rf_iqk_hwspec_8852a;
+		rf_set_ops_8852a(rf);
+	break;
+#endif
+#ifdef RF_8852B_SUPPORT
+	case RF_RTL8852B:
+		rf->rfk_iqk_info = &rf_iqk_hwspec_8852b;
+		rf_set_ops_8852b(rf);
+	break;
+#endif
+#ifdef RF_8852BT_SUPPORT
+	case RF_RTL8852BT:
+		rf->rfk_iqk_info = &rf_iqk_hwspec_8852bt;
+		rf_set_ops_8852bt(rf);
+	break;
+#endif
+#ifdef RF_8852BPT_SUPPORT
+	case RF_RTL8852BPT:
+		rf_set_ops_8852bpt(rf);
+	break;
+#endif
+#ifdef RF_8852C_SUPPORT
+	case RF_RTL8852C:
+		rf->rfk_iqk_info = &rf_iqk_hwspec_8852c;
+		rf_set_ops_8852c(rf);
+		break;
+#endif
+#ifdef RF_8842A_SUPPORT
+	case RF_RTL8842A:
+		rf->rfk_iqk_info = &rf_iqk_hwspec_8842a;
+		rf_set_ops_8842a(rf);
+		break;
+#endif
+#ifdef RF_8852D_SUPPORT
+	case RF_RTL8852D:
+		rf->rfk_iqk_info = &rf_iqk_hwspec_8852d;
+		rf_set_ops_8852d(rf);
+		break;
+#endif
+#ifdef RF_8832D_SUPPORT
+	case RF_RTL8832D:
+		rf->rfk_iqk_info = &rf_iqk_hwspec_8832d;
+		rf_set_ops_8832d(rf);
+		break;
+#endif
+#ifdef RF_8832BR_SUPPORT
+	case RF_RTL8832BR:
+		rf->rfk_iqk_info = &rf_iqk_hwspec_8832br;
+		rf_set_ops_8832br(rf);
+	break;
+#endif
+#ifdef RF_8192XB_SUPPORT
+	case RF_RTL8192XB:
+		rf->rfk_iqk_info = &rf_iqk_hwspec_8192xb;
+		rf_set_ops_8192xb(rf);
+	break;
+#endif
+#ifdef RF_8852BP_SUPPORT
+	case RF_RTL8852BP:
+		rf->rfk_iqk_info = &rf_iqk_hwspec_8852bp;
+		rf_set_ops_8852bp(rf);
+	break;
+#endif
+#ifdef RF_8730A_SUPPORT
+	case RF_RTL8730A:
+		rf->rfk_iqk_info = &rf_iqk_hwspec_8730a;
+	break;
+#endif
+#ifdef RF_8851B_SUPPORT
+	case RF_RTL8851B:
+		rf_set_ops_8851b(rf);
+	break;
+#endif
+
+
+	default:
+	break;
+	}
+}
+
+void halrf_rfk_self_init(struct rf_info *rf)
+{
+	struct halrf_iqk_info *iqk_info = &rf->iqk;
+	struct halrf_gapk_info *txgapk_info = &rf->gapk;
+
+	u8 path;
+
+	RF_DBG(rf, DBG_RF_RFK, "===> %s\n", __func__);
+
+	/* [TXGAPK init] */
+	txgapk_info->is_gapk_init = false;
+
+	rf->chlk_map = 0xffffffff;
+	
+	/*[RXDCK_init*/
+	halrf_rx_dck_init(rf);
+
+	/*[IQK init]*/
+	iqk_info->is_iqk_init = false;
+
+	/*[TSSI init]*/
+	halrf_tssi_init(rf);
+
+	/*[DPK init]*/
+	halrf_dpk_init(rf);
+
+	/*[RXBB BW]*/
+	for (path = 0; path < KPATH; path++)
+		rf->pre_rxbb_bw[path] = 0xff;
+}
+
+void halrf_rfability_init(struct rf_info *rf)
+{
+
+	switch (rf->ic_type) {
+#ifdef RF_8852A_SUPPORT
+	case RF_RTL8852A:
+		rf->hw_rf_ability =
+			HAL_RF_TX_PWR_TRACK |
+			HAL_RF_TSSI_TRK |
+			HAL_RF_IQK |
+			/*HAL_RF_LCK |*/
+			HAL_RF_DPK |
+			HAL_RF_DACK |
+			HAL_RF_TXGAPK |
+			HAL_RF_DPK_TRACK |
+			HAL_RF_RXDCK |
+			HAL_RF_RXGAINK |
+			HAL_RF_THER_TRIM |
+			HAL_RF_PABIAS_TRIM |
+			HAL_RF_TSSI_TRIM |
+			HAL_RF_XTAL_TRACK |
+			HAL_RF_WATCHDOG |
+			0;
+		break;
+#endif
+#ifdef RF_8852B_SUPPORT
+	case RF_RTL8852B:
+		rf->hw_rf_ability |=
+			HAL_RF_TX_PWR_TRACK |
+			HAL_RF_IQK |
+			/*HAL_RF_LCK |*/
+			HAL_RF_DPK |
+			HAL_RF_DACK |
+			HAL_RF_TXGAPK |
+			HAL_RF_DPK_TRACK |
+			HAL_RF_RXDCK |
+			/*HAL_RF_RXGAINK |*/
+			HAL_RF_THER_TRIM |
+			HAL_RF_PABIAS_TRIM |
+			HAL_RF_TSSI_TRIM |
+			/*HAL_RF_XTAL_TRACK |*/
+			HAL_RF_TX_SHAPE |
+			HAL_RF_WATCHDOG |
+			0;
+		break;
+#endif
+#ifdef RF_8852BT_SUPPORT
+	case RF_RTL8852BT:
+		rf->hw_rf_ability |=
+			 HAL_RF_TX_PWR_TRACK |
+			 HAL_RF_IQK |
+			/*HAL_RF_LCK |*/
+			 HAL_RF_DPK | 
+			 HAL_RF_DACK |
+			 HAL_RF_TXGAPK | 
+			 HAL_RF_DPK_TRACK | 
+			 HAL_RF_RXDCK | 
+			/*HAL_RF_RXGAINK |*/
+			 HAL_RF_THER_TRIM |
+			 HAL_RF_PABIAS_TRIM |
+			 HAL_RF_TSSI_TRIM |
+			/*HAL_RF_XTAL_TRACK |*/
+			 HAL_RF_TX_SHAPE |
+			 HAL_RF_WATCHDOG | 
+			 HAL_RF_TAS |
+			0;
+		break;
+#endif
+#ifdef RF_8852BPT_SUPPORT
+	case RF_RTL8852BPT:
+		rf->hw_rf_ability |=
+			HAL_RF_TX_PWR_TRACK |
+			HAL_RF_IQK |
+			HAL_RF_LCK |
+			HAL_RF_DPK |
+			HAL_RF_DACK |
+			HAL_RF_TXGAPK | 
+			HAL_RF_DPK_TRACK | 
+			HAL_RF_RXDCK |
+			/* HAL_RF_RXGAINK |*/
+			/* HAL_RF_THER_TRIM | */
+			/* HAL_RF_PABIAS_TRIM | */
+			/* HAL_RF_TSSI_TRIM | */
+			/* HAL_RF_XTAL_TRACK | */
+			/* HAL_RF_TX_SHAPE | */
+			HAL_RF_RXDCK_TRACK |
+			HAL_RF_WATCHDOG | 
+			0;
+		break;
+#endif
+#ifdef RF_8852C_SUPPORT
+	case RF_RTL8852C:
+		rf->hw_rf_ability |=
+			HAL_RF_TX_PWR_TRACK |
+			HAL_RF_IQK |
+			HAL_RF_LCK |
+			HAL_RF_DPK |
+			HAL_RF_DACK |
+			HAL_RF_TXGAPK |
+			HAL_RF_DPK_TRACK |
+			HAL_RF_RXDCK |
+			HAL_RF_THER_TRIM |
+			HAL_RF_PABIAS_TRIM |
+			HAL_RF_TSSI_TRIM |
+			/*HAL_RF_XTAL_TRACK |*/
+			HAL_RF_TX_SHAPE |
+			HAL_RF_TPE_CTRL |
+			HAL_RF_RXDCK_TRACK |
+			HAL_RF_WATCHDOG |
+			0;
+		break;
+#endif
+#ifdef RF_8842A_SUPPORT
+	case RF_RTL8842A:
+		rf->hw_rf_ability |=
+		/*	HAL_RF_TX_PWR_TRACK |*/
+		/*	HAL_RF_IQK |*/
+		/*	HAL_RF_LCK |*/
+			HAL_RF_DPK |
+		/*	HAL_RF_DACK |*/
+		/*	HAL_RF_TXGAPK |*/
+			HAL_RF_DPK_TRACK |
+		/*	HAL_RF_RXDCK |*/
+		/*	HAL_RF_THER_TRIM |*/
+		/*	HAL_RF_PABIAS_TRIM |*/
+		/*	HAL_RF_TSSI_TRIM |*/
+		/*	HAL_RF_XTAL_TRACK |*/
+		/*	HAL_RF_TX_SHAPE |*/
+		/*	HAL_RF_TPE_CTRL |*/
+		/*	HAL_RF_RXDCK_TRACK |*/
+			HAL_RF_WATCHDOG |
+			0;
+		break;
+#endif
+#ifdef RF_8852D_SUPPORT
+	case RF_RTL8852D:
+		rf->hw_rf_ability |=
+			HAL_RF_TX_PWR_TRACK |
+			HAL_RF_IQK |
+			HAL_RF_LCK |
+			HAL_RF_DPK |
+			HAL_RF_DACK |
+			HAL_RF_TXGAPK |
+			HAL_RF_DPK_TRACK |
+			HAL_RF_RXDCK |
+			HAL_RF_THER_TRIM |
+			HAL_RF_PABIAS_TRIM |
+			HAL_RF_TSSI_TRIM |
+			HAL_RF_XTAL_TRACK |
+			HAL_RF_TX_SHAPE |
+			/*HAL_RF_TPE_CTRL |*/
+			HAL_RF_RXDCK_TRACK |
+			HAL_RF_WATCHDOG |
+			0;
+		break;
+#endif
+#ifdef RF_8832D_SUPPORT
+	case RF_RTL8832D:
+		rf->hw_rf_ability |=
+			HAL_RF_TX_PWR_TRACK |
+			HAL_RF_IQK |
+			HAL_RF_LCK |
+			HAL_RF_DPK |
+			HAL_RF_DACK |
+			HAL_RF_TXGAPK |
+			HAL_RF_DPK_TRACK |
+			HAL_RF_RXDCK |
+			HAL_RF_THER_TRIM |
+			HAL_RF_PABIAS_TRIM |
+			HAL_RF_TSSI_TRIM |
+			HAL_RF_XTAL_TRACK |
+			HAL_RF_TX_SHAPE |
+			/*HAL_RF_TPE_CTRL |*/
+			HAL_RF_RXDCK_TRACK |
+			HAL_RF_WATCHDOG |
+			0;
+		break;
+#endif
+#ifdef RF_8832BR_SUPPORT
+	case RF_RTL8832BR:
+		rf->hw_rf_ability =
+			HAL_RF_TX_PWR_TRACK |
+			HAL_RF_IQK |
+			HAL_RF_LCK |
+			HAL_RF_DPK |
+			HAL_RF_DACK |
+			HAL_RF_TXGAPK |
+			HAL_RF_DPK_TRACK |
+			HAL_RF_RXDCK |
+			HAL_RF_THER_TRIM |
+			HAL_RF_PABIAS_TRIM |
+			HAL_RF_TSSI_TRIM |
+			/*HAL_RF_XTAL_TRACK |*/
+			HAL_RF_TX_SHAPE |
+			/*HAL_RF_OP5K_TRACK |*/
+			/*HAL_RF_OP5K |*/
+			HAL_RF_WATCHDOG |
+			0;
+		break;
+#endif
+#ifdef RF_8192XB_SUPPORT
+	case RF_RTL8192XB:
+		rf->hw_rf_ability =
+			HAL_RF_TX_PWR_TRACK |
+			HAL_RF_IQK |
+			HAL_RF_LCK |
+			HAL_RF_DPK |
+			HAL_RF_DACK |
+			HAL_RF_TXGAPK |
+			HAL_RF_DPK_TRACK |
+			HAL_RF_RXDCK |
+			HAL_RF_THER_TRIM |
+			HAL_RF_PABIAS_TRIM |
+			HAL_RF_TSSI_TRIM |
+			/*HAL_RF_XTAL_TRACK |*/
+			HAL_RF_TX_SHAPE |
+			/*HAL_RF_OP5K_TRACK |*/
+			/*HAL_RF_OP5K |*/
+			HAL_RF_WATCHDOG |
+			0;
+		break;
+#endif
+#ifdef RF_8852BP_SUPPORT
+	case RF_RTL8852BP:
+		rf->hw_rf_ability |=
+			HAL_RF_TX_PWR_TRACK |
+			HAL_RF_IQK |
+			HAL_RF_LCK |
+			HAL_RF_DPK |
+			HAL_RF_DACK |
+			HAL_RF_TXGAPK |
+			HAL_RF_DPK_TRACK |
+			HAL_RF_RXDCK |
+			/*HAL_RF_RXGAINK |*/
+			HAL_RF_THER_TRIM |
+			HAL_RF_PABIAS_TRIM |
+			HAL_RF_TSSI_TRIM |
+			HAL_RF_XTAL_TRACK |
+			HAL_RF_TX_SHAPE |
+			HAL_RF_RXDCK_TRACK |
+			HAL_RF_WATCHDOG |
+			0;
+		break;
+#endif
+#ifdef RF_8730A_SUPPORT
+	case RF_RTL8730A:
+		rf->hw_rf_ability |=
+			/*HAL_RF_TX_PWR_TRACK |*/
+			/*HAL_RF_IQK |*/
+			/*HAL_RF_LCK |*/
+			/*HAL_RF_DPK |*/
+			/*HAL_RF_DACK |*/
+			/*HAL_RF_TXGAPK |*/
+			/*HAL_RF_DPK_TRACK |*/
+			/*HAL_RF_RXDCK |*/
+			/*HAL_RF_RXGAINK |*/
+			/*HAL_RF_THER_TRIM |*/
+			/*HAL_RF_PABIAS_TRIM |*/
+			/*HAL_RF_TSSI_TRIM |*/
+			/*HAL_RF_XTAL_TRACK |*/
+			/*HAL_RF_TX_SHAPE |*/
+			0;
+			break;
+#endif
+
+#ifdef RF_8851B_SUPPORT
+	case RF_RTL8851B:
+		rf->hw_rf_ability |=
+			HAL_RF_TX_PWR_TRACK |
+			HAL_RF_IQK |
+			HAL_RF_LCK |
+			HAL_RF_DPK |
+			HAL_RF_DACK |
+			HAL_RF_TXGAPK |
+			HAL_RF_DPK_TRACK |
+			HAL_RF_RXDCK |
+			/*HAL_RF_RXGAINK |*/
+			HAL_RF_THER_TRIM |
+			HAL_RF_PABIAS_TRIM |
+			HAL_RF_TSSI_TRIM |
+			HAL_RF_XTAL_TRACK |
+			HAL_RF_TX_SHAPE |
+			HAL_RF_WATCHDOG |
+			HAL_RF_TAS |
+			0;
+		break;
+#endif
+
+	default:
+		rf->hw_rf_ability =
+			/*HAL_RF_TX_PWR_TRACK |*/
+			/*HAL_RF_IQK |*/
+			/*HAL_RF_LCK |*/
+			/*HAL_RF_DPK |*/
+			/*HAL_RF_DACK |*/
+			/*HAL_RF_TXGAPK |*/
+			/*HAL_RF_DPK_TRACK |*/
+			0;
+		break;
+	}
+}
+
+void halrf_set_rfability(struct rf_info *rf)
+{
+
+	halrf_rfability_init(rf);
+	rf->hal_com->dev_hw_cap.rfk_cap = rf->hw_rf_ability;
+
+	RF_DBG(rf, DBG_RF_INIT,
+	       "IC = ((0x%x)), mp=%d,  hw_rf_ability = ((0x%x))\n",
+	       rf->ic_type, rf->phl_com->drv_mode, rf->hw_rf_ability);
+}
+
+void halrf_set_final_rfability(struct rf_info *rf)
+{
+	rf->support_ability =
+		rf->phl_com->dev_cap.rfk_cap & rf->hw_rf_ability;
+
+	RF_DBG(rf, DBG_RF_INIT,
+	       "IC = ((0x%x)), mp=%d,  RF_Supportability Init = ((0x%x))\n",
+	       rf->ic_type, rf->phl_com->drv_mode, rf->support_ability);
+}
+
+void halrf_rfe_init(struct rf_info *rf)
+{
+	u8 rfe_type = rf->phl_com->dev_cap.rfe_type;
+
+	switch (rf->ic_type) {
+#ifdef RF_8852A_SUPPORT
+	case RF_RTL8852A:
+		/*2G FEM check*/
+		if (rfe_type == 11 || rfe_type == 12 || rfe_type == 17 ||
+		    rfe_type == 18 || rfe_type == 51 || rfe_type == 52 ||
+		    rfe_type == 53 || rfe_type == 54) {
+			rf->fem.epa_2g = 1;
+			rf->fem.elna_2g = 1;
+		}
+		/*5G FEM check*/
+		if (rfe_type == 9 || rfe_type == 10 || rfe_type == 11 ||
+		    rfe_type == 12 || rfe_type == 15 || rfe_type == 16 ||
+		    rfe_type == 17 || rfe_type == 18 || rfe_type == 37 || 
+		    rfe_type == 38 || rfe_type == 51 || rfe_type == 52 ||
+		    rfe_type == 53 || rfe_type == 54) {
+			rf->fem.epa_5g = 1;
+			rf->fem.elna_5g = 1;
+		}
+		/*6G FEM check*/
+		if (rfe_type == 13 || rfe_type == 14 || rfe_type == 15 ||
+		    rfe_type == 16 || rfe_type == 17 || rfe_type == 18 ||
+		    rfe_type == 37 || rfe_type == 38 || rfe_type == 51 ||
+		    rfe_type == 52 || rfe_type == 53 ||
+		    rfe_type == 54) {
+			rf->fem.epa_6g = 1;
+			rf->fem.elna_6g = 1;
+		}
+		break;
+#endif
+
+#ifdef RF_8852C_SUPPORT
+	case RF_RTL8852C:
+		/*2G FEM check*/
+		if (rfe_type > 50) {
+			rf->fem.epa_2g = 1;
+			rf->fem.elna_2g = 1;
+		}
+		/*5G FEM check*/
+		if (rfe_type == 21 || rfe_type == 22 || rfe_type > 50) {
+			rf->fem.epa_5g = 1;
+			rf->fem.elna_5g = 1;
+		}
+		/*6G FEM check*/
+		if (rfe_type > 50) {
+			rf->fem.epa_6g = 1;
+			rf->fem.elna_6g = 1;
+		}
+		break;
+#endif
+	default:
+		break;
+	}
+}
+
+void halrf_rfe_type_gpio_setting(struct rf_info *rf)
+{
+	u32 band = rf->hal_com->band[HW_PHY_0].cur_chandef.band;
+
+	RF_DBG(rf, DBG_RF_INIT, "======>%s\n", __func__);
+
+	halrf_set_gpio(rf, HW_PHY_0, (u8)band);
+}
+
+enum rtw_hal_status halrf_dm_init(void *rf_void)
+{
+	struct rf_info *rf = (struct rf_info *)rf_void;
+	enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS;
+	u32 data_to_fw[1] = {0};
+	u16 len = (u16) (sizeof(data_to_fw) / sizeof(u32))*4;
+
+	if (!rf) {
+//		RF_DBG(rf, DBG_RF_INIT, "[%s] *rf = NULL", __func__);
+		RF_WARNING("[%s] *rf = NULL\n", __func__);
+		return RTW_HAL_STATUS_FAILURE;
+	}
+
+	halrf_rfe_type_gpio_setting(rf);
+	/*Set Power table ref power*/
+	halrf_set_ref_power_to_struct(rf, HW_PHY_0);
+
+	halrf_cmd_parser_init(rf);
+	halrf_set_final_rfability(rf);
+	halrf_rfe_init(rf);
+	halrf_config_nctl_reg(rf);
+	halrf_rfk_self_init(rf);
+	halrf_si_reset(rf);
+	halrf_aack_trigger(rf, HW_PHY_0);
+	halrf_lck_trigger(rf);
+	halrf_rck_trigger(rf, HW_PHY_0);
+	//halrf_gapk_save_tx_gain_8852a(rf);
+	halrf_dack_trigger(rf, false);
+
+	/*RX DCK move to halrf_chl_rfk_trigger RFK_TYPE_PLATFORM_INIT*/
+	//halrf_rx_dck_trigger(rf, HW_PHY_0, true);
+
+	/*RX Gain K Get efuse*/
+	/*halrf_get_efuse_rx_gain_k(rf, HW_PHY_0);*/
+
+	/*Thermal Trim, PA Bias k, TSSI Trim get efuse and set reg*/
+	halrf_get_efuse_trim(rf, HW_PHY_0);
+
+	/*TSSI Init*/
+	halrf_tssi_get_efuse_ex(rf, HW_PHY_0);
+	/*halrf_tssi_get_efuse_ex(rf, HW_PHY_1);*/
+
+	halrf_fcs_init(rf);
+	/*Set MAC 0xd220[1]=0  r_txagc_BT_en=0 by Bryant*/
+	if (phl_is_mp_mode(rf->phl_com)) {
+		/*halrf_wl_tx_power_control(rf, 0xffffffff);*/
+		halrf_wlan_tx_power_control(rf, HW_PHY_0, ALL_TIME_CTRL,
+			0x0, false);
+		halrf_wlan_tx_power_control(rf, HW_PHY_0, GNT_TIME_CTRL,
+			0x0, false);
+	}
+
+	data_to_fw[0] = rf->phl_com->dev_cap.rfe_type;
+	halrf_fill_h2c_cmd(rf, len, FWCMD_H2C_RF_INIT_CFG, 0xA, H2CB_TYPE_DATA, (u32 *)data_to_fw); // h2c cmd
+
+	return hal_status;
+}
+
+enum rtw_hal_status halrf_init(struct rtw_phl_com_t *phl_com,
+			struct rtw_hal_com_t *hal_com, void **rf_out)
+{
+	struct rf_info *rf = NULL;
+
+	rf = hal_mem_alloc(hal_com, sizeof(struct rf_info));
+
+	if (!rf)
+		return RTW_HAL_STATUS_RF_INIT_FAILURE;
+
+	*rf_out = rf;
+
+	rf->phl_com = phl_com;/*shared memory for all components*/
+	rf->hal_com = hal_com;/*shared memory for phl and hal*/
+
+	/*[Drv Dbg Info]*/
+	rf->dbg_component = 0;
+	rf->cmn_dbg_msg_period = 2;
+	rf->cmn_dbg_msg_cnt = 0;
+	halrf_dbg_setting_init(rf);
+	
+	#if 0 //move to halrf_ic_cfg_init
+	halrf_cmn_info_self_init(rf);
+	/*init. HW cap*/
+	halrf_set_rfability(rf);
+	#endif
+	halrf_mutex_init(rf, &rf->rf_lock);
+	return RTW_HAL_STATUS_SUCCESS;
+}
+
+void halrf_deinit(struct rtw_phl_com_t *phl_com,
+			struct rtw_hal_com_t *hal_com, void *rf)
+{
+	struct rf_info *halrf = (struct rf_info *)rf;
+
+#ifndef RF_8730A_SUPPORT
+	/*stop FSM of RF or free memory*/
+	PHL_INFO("[PHL] %s - halrf(%p)\n", __func__, halrf);
+#endif
+	if(halrf)
+		halrf_mutex_deinit(halrf, &halrf->rf_lock);
+
+	if(halrf) {	
+		hal_mem_free(hal_com, halrf, sizeof(struct rf_info));
+	}
+}
+
+enum rtw_hal_status halrf_ic_cfg_init(void *rf_void)
+{
+	struct rf_info *rf = (struct rf_info *)rf_void;
+	
+	RF_TRACE("halrf_ic_cfg_init aid = 0x%x !!\n",rf->hal_com->aid );
+
+	halrf_cmn_info_self_init(rf);
+	/*init. HW cap*/
+	halrf_set_rfability(rf);
+
+	return RTW_HAL_STATUS_SUCCESS;
+}			

3rd/devourer/hal/halrf/g6/vendor/halrf_init.h

@@ -0,0 +1,32 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2019 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef _HALRF_INIT_H_
+#define _HALRF_INIT_H_
+#include "../../hal_headers_le.h"
+
+
+ /*@--------------------------[Define] ---------------------------------------*/
+
+ /*@--------------------------[Enum]------------------------------------------*/
+ 
+ /*@--------------------------[Structure]-------------------------------------*/
+ 
+ /*@--------------------------[Prptotype]-------------------------------------*/
+struct rf_info;
+void halrf_cmn_info_self_init(struct rf_info *rf);
+void halrf_rfability_init_mp(struct rf_info *rf);
+void halrf_rfability_init(struct rf_info *rf);
+void halrf_set_rfability(struct rf_info *rf);
+#endif

3rd/devourer/hal/halrf/g6/vendor/halrf_init_ex.h

@@ -0,0 +1,38 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2019 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef _HALRF_INIT_EX_H_
+#define _HALRF_INIT_EX_H_
+
+ /*@--------------------------[Define] ---------------------------------------*/
+
+ /*@--------------------------[Enum]------------------------------------------*/
+ 
+ /*@--------------------------[Structure]-------------------------------------*/
+ 
+ /*@--------------------------[Prptotype]-------------------------------------*/
+#if 0
+struct rf_info;
+void halrf_cmn_info_self_init(struct rf_info *rf);
+void halrf_rfability_init_mp(struct rf_info *rf);
+void halrf_rfability_init(struct rf_info *rf);
+void halrf_set_rfability(struct rf_info *rf);
+
+enum rtw_hal_status  halrf_init(struct rtw_phl_com_t *phl_com,
+			 struct rtw_hal_com_t *hal_com, void **rf_out);
+void halrf_deinit(struct rtw_phl_com_t *phl_com,
+			 struct rtw_hal_com_t *hal_com, void *rf);
+#endif
+
+#endif

3rd/devourer/hal/halrf/g6/vendor/halrf_interface.c

@@ -0,0 +1,441 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2020  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+#include "halrf_precomp.h"
+
+u32 halrf_get_sys_time(struct rf_info *rf)
+{
+	return 0;
+}
+
+u32 halrf_cal_bit_shift(u32 bit_mask)
+{
+	u32 i;
+
+	for (i = 0; i <= 31; i++) {
+		if ((bit_mask >> i) & BIT0)
+			break;
+	}
+	return i;
+}
+
+void halrf_wmac(struct rf_info *rf, u32 addr, u32 mask, u32 val)
+{
+	u32 ori_val, bit_shift;
+#if defined(HALRF_CONFIG_FW_DBCC_OFLD_SUPPORT) || defined(HALRF_CONFIG_FW_IO_OFLD_SUPPORT)
+	struct rtw_mac_cmd cmd = {0};
+	//u32 fw_ofld = rf->phl_com->dev_cap.fw_cap.offload_cap & BIT(0);
+	bool fw_ofld = rf->phl_com->dev_cap.io_ofld;
+	u32 rtn;
+
+#ifdef HALRF_CONFIG_FW_DBCC_OFLD_SUPPORT
+	fw_ofld = 1;
+#endif
+
+
+
+	if (fw_ofld == true && rf->fw_ofld_enable == true) {
+		rf->fw_ofld_start = true;
+		RF_DBG(rf, DBG_RF_FW,
+			"[FW_Ofld] MAC   addr=0x%08x   val=0x%08x\n",
+			addr, val);
+
+		cmd.src = RTW_MAC_MAC_CMD_OFLD;
+		cmd.type = RTW_MAC_WRITE_OFLD;
+		cmd.lc = 0;
+		cmd.offset = (u16)addr;
+		cmd.value = val;
+		cmd.mask = mask;
+
+		rtn = halrf_mac_add_cmd_ofld(rf, &cmd);
+		if (rtn) {
+			RF_WARNING("======>%s return fail error code = %d !!!\n",
+				__func__, rtn);
+		}
+		rf->fw_w_count++;
+	}
+	else
+#endif
+	{
+		if (mask != MASKDWORD) {
+			ori_val = halrf_rmac32(rf, addr);
+			bit_shift = halrf_cal_bit_shift(mask);
+			val = ((ori_val) & (~mask)) |( ((val << bit_shift)) & mask);
+		}
+		halrf_wmac32(rf, addr, val);
+	}
+	rf->w_count++;
+}
+
+u32 halrf_rmac32(struct rf_info *rf, u32 addr)
+{
+	u32 reg_val = 0;
+	
+#if defined(HALRF_CONFIG_FW_DBCC_OFLD_SUPPORT) || defined(HALRF_CONFIG_FW_IO_OFLD_SUPPORT)
+	if (rf->fw_ofld_start == true)
+		halrf_write_fwofld_end(rf);
+#endif
+	rf->r_count++;
+	reg_val = hal_read32((rf)->hal_com, addr);
+	return reg_val;
+}
+void halrf_wreg(struct rf_info *rf, u32 addr, u32 mask, u32 val)
+{
+	u32 ori_val, bit_shift;
+#if defined(HALRF_CONFIG_FW_DBCC_OFLD_SUPPORT) || defined(HALRF_CONFIG_FW_IO_OFLD_SUPPORT)
+	struct rtw_mac_cmd cmd = {0};
+//	u32 fw_ofld = rf->phl_com->dev_cap.io_ofld; //rf->phl_com->dev_cap.fw_cap.offload_cap & BIT(0);
+	bool fw_ofld = rf->phl_com->dev_cap.io_ofld;
+	u32 rtn;
+#endif
+
+#ifdef HALRF_CONFIG_FW_DBCC_OFLD_SUPPORT
+	fw_ofld = 1;
+#endif
+//	u32 page_temp;
+//	u32 offset_temp;	
+//	u32 temp = 0;
+
+//	page_temp = addr & 0xff00;
+//	offset_temp = addr & 0xff;
+
+//	if ((page_temp != 0x4c00) && (page_temp != 0x4d00)) {
+//		if (offset_temp <= 0x9c)
+//			temp = halrf_r32(rf, offset_temp | 0x4c00);
+//	}
+#if defined(HALRF_CONFIG_FW_DBCC_OFLD_SUPPORT) || defined(HALRF_CONFIG_FW_IO_OFLD_SUPPORT)
+	if (fw_ofld == true && rf->fw_ofld_enable == true) {
+		rf->fw_ofld_start = true;
+		RF_DBG(rf, DBG_RF_FW,
+			"[FW_Ofld] BB   addr=0x%08x   mask=0x%08x   val=0x%08x\n",
+			addr, mask, val);
+
+		cmd.src = RTW_MAC_BB_CMD_OFLD;
+		cmd.type = RTW_MAC_WRITE_OFLD;
+		cmd.lc = 0;
+		cmd.offset = (u16)addr;
+		cmd.value = val;
+		cmd.mask = mask;
+
+		rtn = halrf_mac_add_cmd_ofld(rf, &cmd);
+		if (rtn) {
+			RF_WARNING("======>%s return fail error code = %d !!!\n",
+				__func__, rtn);
+		}
+
+		rf->fw_w_count++;
+	}
+	else
+#endif
+	{
+		if (mask != MASKDWORD) {
+			ori_val = halrf_r32(rf, addr);
+			bit_shift = halrf_cal_bit_shift(mask);
+			val = ((ori_val) & (~mask)) |( ((val << bit_shift)) & mask);
+		}
+		halrf_w32(rf, addr, val);
+	}
+	rf->w_count++;
+//	if ((page_temp != 0x4c00) && (page_temp != 0x4d00)) {
+//		if (offset_temp <= 0x9c)
+//			halrf_w32(rf, offset_temp | 0x4c00, temp);
+//	}
+}
+
+u32 halrf_rreg(struct rf_info *rf, u32 addr, u32 mask)
+{
+	u32 reg_val = 0, ori_val, bit_shift;
+
+#if defined(HALRF_CONFIG_FW_DBCC_OFLD_SUPPORT) || defined(HALRF_CONFIG_FW_IO_OFLD_SUPPORT)
+	if (rf->fw_ofld_start == true)
+		halrf_write_fwofld_trigger(rf);
+
+#endif
+	ori_val = halrf_r32(rf, addr);
+	bit_shift = halrf_cal_bit_shift(mask);
+	reg_val = (ori_val & mask) >> bit_shift;
+	rf->r_count++;
+	return reg_val;
+}
+
+u32 halrf_rrf(struct rf_info *rf, enum rf_path path, u32 addr, u32 mask)
+{
+	static u32 operate2 = 0;
+	u32 val = 0;
+	
+	if (_os_atomic_inc_return(rf->hal_com->drv_priv, (void*)&operate2) > 1) {
+		RF_WARNING("RF read race %x %x %x!!!!!!!!!!!!!!", path, addr, mask);
+	}
+
+#if defined(HALRF_CONFIG_FW_DBCC_OFLD_SUPPORT) || defined(HALRF_CONFIG_FW_IO_OFLD_SUPPORT)
+	if (rf->fw_ofld_start == true)
+		halrf_write_fwofld_trigger(rf);
+#endif
+
+	val = rtw_hal_read_rf_reg((rf)->hal_com, path, addr, mask);
+	_os_atomic_dec(rf->hal_com->drv_priv, (void*)&operate2);
+	rf->r_count++;
+	return val;
+}
+
+void halrf_wrf(struct rf_info *rf, enum rf_path path, u32 addr, u32 mask, u32 val)
+{
+	static u32 operate2 = 0;
+	
+#if defined(HALRF_CONFIG_FW_DBCC_OFLD_SUPPORT) || defined(HALRF_CONFIG_FW_IO_OFLD_SUPPORT)
+	struct rtw_mac_cmd cmd = {0};
+//	u32 fw_ofld = rf->phl_com->dev_cap.fw_cap.offload_cap & BIT(0);
+	bool fw_ofld = rf->phl_com->dev_cap.io_ofld;
+	u32 rtn;
+	u32 direct_addr, offset_write_rf[2] = {0xe000, 0xf000};
+
+#ifdef HALRF_CONFIG_FW_DBCC_OFLD_SUPPORT
+	fw_ofld = 1;
+#endif
+
+	if (_os_atomic_inc_return(rf->hal_com->drv_priv, (void*)&operate2) > 1) {
+		RF_WARNING("RF write race %x %x %x %x!!!!!!!!!!!!!!", path, addr, mask, val);
+	}
+
+
+	if (fw_ofld == true && rf->fw_ofld_enable == true) {
+		rf->fw_ofld_start = true;
+		RF_DBG(rf, DBG_RF_FW,
+			"[FW_Ofld] RF   addr=0x%08x   mask=0x%08x   val=0x%08x   path=%d\n",
+			addr, mask, val, path);
+
+		if (addr & BIT(16)) {	/*RF D-die*/
+			/*==== Calculate offset ====*/
+			addr &= 0xff;
+			direct_addr = offset_write_rf[path] + (addr << 2);
+
+			cmd.src = RTW_MAC_BB_CMD_OFLD;
+			cmd.type = RTW_MAC_WRITE_OFLD;
+			cmd.lc = 0;
+			cmd.offset = (u16)direct_addr;
+			cmd.value = val;
+			cmd.mask = mask;
+		} else {
+			cmd.src = RTW_MAC_RF_CMD_OFLD;
+			cmd.type = RTW_MAC_WRITE_OFLD;
+			cmd.lc = 0;
+			cmd.rf_path = path;
+			cmd.offset = (u16)addr;
+			cmd.value = val;
+			cmd.mask = mask;
+		}
+
+		RF_DBG(rf, DBG_RF_FW,
+			"[FW_Ofld] cmd.src=0x%x   addr=0x%x\n", cmd.src, addr);
+
+		rtn = halrf_mac_add_cmd_ofld(rf, &cmd);
+		if (rtn) {
+			RF_WARNING("======>%s return fail error code = %d !!!\n",
+				__func__, rtn);
+		}
+
+		rf->fw_w_count++;
+	} else
+#endif
+		rtw_hal_write_rf_reg((rf)->hal_com, path, addr, mask, val);
+
+	_os_atomic_dec(rf->hal_com->drv_priv, (void*)&operate2);
+	rf->w_count++;
+}
+
+bool halrf_polling_bb(struct rf_info *rf, u32 addr, u32 mask, u32 val, u32 count)
+{
+	bool result = true;
+#if defined(HALRF_CONFIG_FW_DBCC_OFLD_SUPPORT) || defined(HALRF_CONFIG_FW_IO_OFLD_SUPPORT)
+	struct rtw_mac_cmd cmd = {0};
+//	u32 fw_ofld = rf->phl_com->dev_cap.fw_cap.offload_cap & BIT(0);
+	bool fw_ofld = rf->phl_com->dev_cap.io_ofld;
+	u32 rtn;
+
+#ifdef HALRF_CONFIG_FW_DBCC_OFLD_SUPPORT
+	fw_ofld = 1;
+#endif
+
+	if (fw_ofld == true && rf->fw_ofld_enable == true) {
+		rf->fw_ofld_start = true;
+		RF_DBG(rf, DBG_RF_FW,
+			"[FW_Ofld] Polling BB addr=0x%08x   mask=0x%08x   val=0x%08x\n",
+			addr, mask, val);
+
+		cmd.src = RTW_MAC_BB_CMD_OFLD;
+		cmd.type = RTW_MAC_COMPARE_OFLD;
+		cmd.lc = 0;
+		cmd.offset = (u16)addr;
+		cmd.value = val;
+		cmd.mask = mask;
+
+		rtn = halrf_mac_add_cmd_ofld(rf, &cmd);
+		if (rtn) {
+			RF_WARNING("======>%s return fail error code = %d !!!\n",
+				__func__, rtn);
+		}
+		if (rtn == 0)
+			result = true;
+		else
+			result = false;
+	}
+	else
+#endif
+	{
+		u32 c = 0;
+		while (halrf_rreg(rf, addr, mask) != val) {
+			c++;
+			halrf_delay_us(rf, 1);
+			if (c > count) {
+				result = false;
+				break;
+			}
+		}
+	}
+
+	return result;
+}
+
+bool halrf_polling_rf(struct rf_info *rf, u32 path, u32 addr, u32 mask, u32 val, u32 count)
+{
+	bool result = true;
+#if defined(HALRF_CONFIG_FW_DBCC_OFLD_SUPPORT) || defined(HALRF_CONFIG_FW_IO_OFLD_SUPPORT)
+	struct rtw_mac_cmd cmd = {0};
+//	u32 fw_ofld = rf->phl_com->dev_cap.fw_cap.offload_cap & BIT(0);
+	bool fw_ofld = rf->phl_com->dev_cap.io_ofld;
+
+	u32 rtn;
+
+#ifdef HALRF_CONFIG_FW_DBCC_OFLD_SUPPORT
+	fw_ofld = 1;
+#endif
+
+	if (fw_ofld == true && rf->fw_ofld_enable == true) {
+		rf->fw_ofld_start = true;
+		RF_DBG(rf, DBG_RF_FW,
+			"[FW_Ofld] Polling RF path=%d   addr=0x%08x   mask=0x%08x   val=0x%08x\n",
+			path, addr, mask, val);
+
+		if (addr & BIT(16))
+			cmd.src = RTW_MAC_RF_DDIE_CMD_OFLD;
+		else
+			cmd.src = RTW_MAC_RF_CMD_OFLD;
+
+
+		cmd.type = RTW_MAC_COMPARE_OFLD;
+		cmd.lc = 0;
+		cmd.rf_path = path;
+		cmd.offset = (u16)addr;
+		cmd.value = val;
+		cmd.mask = mask;
+
+		rtn = halrf_mac_add_cmd_ofld(rf, &cmd);
+		if (rtn) {
+			RF_WARNING("======>%s return fail error code = %d !!!\n",
+				__func__, rtn);
+		}
+		if (rtn == 0)
+			result = true;
+		else
+			result = false;
+	}
+	else
+#endif
+	{
+		u32 c = 0;
+		while (halrf_rrf(rf, path, addr, mask) != val) {
+			c++;
+			halrf_delay_us(rf, 1);
+			if (c > count) {
+				result = false;
+				break;
+			}
+		}
+	}
+
+	return result;
+}
+
+
+void halrf_delay_us(struct rf_info *rf, u32 count)
+{
+#if defined(HALRF_CONFIG_FW_DBCC_OFLD_SUPPORT) || defined(HALRF_CONFIG_FW_IO_OFLD_SUPPORT)
+	struct rtw_mac_cmd cmd = {0};
+//	u32 fw_ofld = rf->phl_com->dev_cap.fw_cap.offload_cap & BIT(0);
+	bool fw_ofld = rf->phl_com->dev_cap.io_ofld;
+	u32 rtn;
+
+#ifdef HALRF_CONFIG_FW_DBCC_OFLD_SUPPORT
+	fw_ofld = 1;
+#endif
+
+	if (fw_ofld == true && rf->fw_ofld_enable == true) {
+		rf->fw_ofld_start= true;
+		RF_DBG(rf, DBG_RF_FW,
+			"[FW_Ofld] ======>%s count=%d\n",
+			__func__, count);
+
+		cmd.type = RTW_MAC_DELAY_OFLD;
+		cmd.lc = 0;
+		cmd.value = count;
+
+		rtn = halrf_mac_add_cmd_ofld(rf, &cmd);
+		if (rtn) {
+			RF_WARNING("======>%s return fail error code = %d !!!\n",
+				__func__, rtn);
+		}
+
+		rf->fw_delay_us_count = rf->fw_delay_us_count + count;
+	}
+	else
+#endif
+	{
+		u32 i;
+
+		for (i = 0; i < count; i++)
+			halrf_os_delay_us(rf, 1);
+	}
+}
+
+void halrf_fill_h2c_cmd(struct rf_info *rf, u16 cmdlen, u8 cmdid,
+			u8 classid, u32 cmdtype, u32 *pval)
+{
+	u32 rt_val = 0;
+	struct rtw_g6_h2c_hdr hdr = {0};
+	struct rtw_hal_com_t *hal_com = NULL;
+
+	hdr.h2c_class = classid;
+	hdr.h2c_func = cmdid;
+	hdr.type = cmdtype;
+	hdr.content_len = cmdlen;
+	hal_com = rf->hal_com;
+	RF_DBG(rf, DBG_RF_IQK, "[IQK]======>%s   H2C: %x %x %x\n",
+		__func__, classid, cmdid, cmdlen);
+	rt_val =  rtw_hal_mac_send_h2c(hal_com, &hdr, pval);
+	if (rt_val != 0) {
+		RF_WARNING("Error H2C CLASS=%d, ID=%d\n", classid, cmdid);
+		RF_DBG(rf, DBG_RF_IQK, "Error H2C CLASS=%d, ID=%d\n", classid, cmdid);
+	}
+}
+

3rd/devourer/hal/halrf/g6/vendor/halrf_interface.h

@@ -0,0 +1,240 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2020  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+#ifndef __HALRF_INTERFACE_H__
+#define __HALRF_INTERFACE_H__
+
+//#ifdef CONFIG_FW_IO_OFLD_SUPPORT
+#ifdef CONFIG_PHL_IO_OFLD
+#define HALRF_CONFIG_FW_IO_OFLD_SUPPORT
+#endif
+
+#ifdef CONFIG_FW_DBCC_OFLD_SUPPORT
+#define HALRF_CONFIG_FW_DBCC_OFLD_SUPPORT
+#endif
+
+#ifdef CONFIG_HAL_THERMAL_PROTECT
+#define HALRF_THERMAL_PROTECT_SUPPORT
+#endif
+
+#ifdef PHL_PLATFORM_WINDOWS
+#if (TAS_SUPPORT == 1)
+#define HALRF_TAS_SUPPORT
+#endif
+#endif
+
+#define CF_PHL_BB_CTRL_RX_CCA
+
+#define HALRF_PSD_SUPPORT
+
+#if defined(RF_8832BR_SUPPORT) || defined(RF_8192XB_SUPPORT)
+	#define HALRF_OP5K_SUPPORT
+#endif
+
+/* Load pwr_lmt/pwr_by_rate by rfe_type */
+/* BIT0: unknown */
+/* BIT1:RFE_TYPE1, BIT2:RFE_TYPE2 ~ BIT6:RFE_TYPE6*/
+/* 0xFFFFFFFF: all of rfe_type */
+#if !defined(CONFIG_RFE_TYPE1_31) && !defined(CONFIG_RFE_TYPE32_63) && \
+    !defined(CONFIG_RFE_TYPE64_95)
+#define HALRF_RFE_TYPE1_SUPPORT
+#define HALRF_RFE_TYPE2_SUPPORT
+#define HALRF_RFE_TYPE3_SUPPORT
+#define HALRF_RFE_TYPE4_SUPPORT
+#define HALRF_RFE_TYPE5_SUPPORT
+#define HALRF_RFE_TYPE6_SUPPORT
+#define HALRF_RFE_TYPE22_SUPPORT
+#endif
+
+#if defined(CONFIG_RFE_TYPE1_31)
+/* BIT1 ~ BIT31: RFE_TYPE1 ~ RFE_TYPE31 */
+
+#if (CONFIG_RFE_TYPE1_31 & BIT1)
+	#define HALRF_RFE_TYPE1_SUPPORT
+#endif
+#if (CONFIG_RFE_TYPE1_31 & BIT2)
+	#define HALRF_RFE_TYPE2_SUPPORT
+#endif
+#if (CONFIG_RFE_TYPE1_31 & BIT3)
+	#define HALRF_RFE_TYPE3_SUPPORT
+#endif
+#if (CONFIG_RFE_TYPE1_31 & BIT4)
+	#define HALRF_RFE_TYPE4_SUPPORT
+#endif
+#if (CONFIG_RFE_TYPE1_31 & BIT5)
+	#define HALRF_RFE_TYPE5_SUPPORT
+#endif
+#if (CONFIG_RFE_TYPE1_31 & BIT6)
+	#define HALRF_RFE_TYPE6_SUPPORT
+#endif
+#if (CONFIG_RFE_TYPE1_31 & BIT22)
+	#define HALRF_RFE_TYPE22_SUPPORT
+#endif
+#endif /* CONFIG_RFE_TYPE1_31 */
+
+#if defined(CONFIG_RFE_TYPE32_63)
+/* BIT32 ~ BIT63: RFE_TYPE32 ~ RFE_TYPE63 */
+#endif /* CONFIG_RFE_TYPE32_63 */
+#if defined(CONFIG_RFE_TYPE64_95)
+/* BIT64 ~ BIT95: RFE_TYPE64 ~ RFE_TYPE95 */
+#endif /* CONFIG_RFE_TYPE64_95 */
+
+/*@--------------------------[Define] ---------------------------------------*/
+/*[IO Reg]*/
+#define RF_OFST 0x10000
+#define halrf_btc_ntfy(rf, idx, type, process) rtw_hal_btc_wl_rfk_ntfy((rf)->hal_com, idx, type, process)
+#define halrf_r32(rf, addr) hal_read32((rf)->hal_com, (addr | RF_OFST))
+#define halrf_r16(rf, addr) hal_read16((rf)->hal_com, (addr | RF_OFST))
+#define halrf_r8(rf, addr) hal_read8((rf)->hal_com, (addr | RF_OFST))
+#define halrf_w32(rf, addr, val) hal_write32((rf)->hal_com, (addr | RF_OFST), val)
+#define halrf_w16(rf, addr, val) hal_write16((rf)->hal_com, (addr | RF_OFST), val)
+#define halrf_w8(rf, addr, val) hal_write8((rf)->hal_com, (addr | RF_OFST), val)
+//#define halrf_rrf(rf, path, addr, mask) rtw_hal_read_rf_reg((rf)->hal_com, path, addr, mask)
+/*#define halrf_wrf(rf, path, addr, mask, val) rtw_hal_write_rf_reg((rf)->hal_com, path, addr, mask, val)*/
+/*#define halrf_wmac32(rf, addr, val) hal_write32((rf)->hal_com, addr, val)*/
+//#define halrf_rmac32(rf, addr) hal_read32((rf)->hal_com, addr)
+#define halrf_wmac32(rf, addr, val) hal_write32((rf)->hal_com, addr, val)
+#define halrf_read_mem(rf, addr, cnt, pmem) hal_read_mem((rf)->hal_com, addr, cnt, pmem)
+
+/*[TX]*/
+#define halrf_tx_pause(rf, band_idx, tx_pause, rson) rtw_hal_tx_pause((rf)->hal_com, band_idx, tx_pause, rson)
+#define halrf_tx_mode_switch(rf, phy_idx, mode) rtw_hal_bb_tx_mode_switch((rf)->hal_com, phy_idx, mode)
+#define halrf_query_regulation_info(rf, info) rtw_hal_query_regulation((rf)->phl_com->phl_priv, info)
+#define halrf_hal_bb_backup_info(rf, phy_idx) rtw_hal_bb_backup_info((rf)->hal_com, phy_idx)
+#define halrf_hal_bb_restore_info(rf, phy_idx) rtw_hal_bb_restore_info((rf)->hal_com, phy_idx)
+
+/*[Delay]*/
+#define halrf_delay_ms(rf, ms) _os_delay_ms(rf->hal_com->drv_priv, ms)
+#define halrf_os_delay_us(rf, us) _os_delay_us(rf->hal_com->drv_priv, us)
+
+/*[Memory Access]*/
+#define halrf_mem_set(rf, buf, value, size) _os_mem_set(rf->hal_com->drv_priv, (void *)buf, value, size)
+#define halrf_mem_cpy(rf, dest, src, size) _os_mem_cpy(rf->hal_com->drv_priv, (void *)dest, (void *)src, size)
+#define halrf_mem_cmp(rf, dest, src, size) _os_mem_cmp(rf->hal_com->drv_priv, (void *)dest, (void *)src, size)
+#define halrf_mem_alloc(rf, buf_sz) hal_mem_alloc(rf->hal_com, buf_sz)
+#define halrf_mem_free(rf, buf, buf_sz) hal_mem_free(rf->hal_com, (void *)buf, buf_sz)
+
+
+/*[Timer]*/
+#define halrf_init_timer(rf, timer, call_back_func, context, sz_id) _os_init_timer(rf->hal_com->drv_priv, timer, call_back_func, context, sz_id)
+#define halrf_set_timer(rf, timer, ms_delay) _os_set_timer(rf->hal_com->drv_priv, timer, ms_delay)
+#define halrf_cancel_timer(rf, timer) _os_cancel_timer(rf->hal_com->drv_priv, timer)
+#define halrf_release_timer(rf, timer) _os_release_timer(rf->hal_com->drv_priv, timer)
+
+/*efuse*/
+#ifndef RTW_FLASH_98D
+#define halrf_efuse_get_info(rf, info_type, value, size) rtw_hal_efuse_get_info((rf)->hal_com, info_type, (void *)value, size)
+#else
+#define halrf_efuse_get_info(rf, info_type, value, size) rtw_hal_flash_get_info((rf)->hal_com, info_type, (void *)value, size)
+#endif /*RTW_FLASH_98D*/
+#define halrf_phy_efuse_get_info(rf, addr, size, value) rtw_hal_mac_read_phy_efuse((rf)->hal_com, addr, size, value)
+
+/*GPIO*/
+/*#ifndef RF_8852B_SUPPORT*/
+#define halrf_gpio_setting_all(rf, rfe_idx) rtw_hal_bb_gpio_setting_all((rf)->hal_com, rfe_idx)
+#define halrf_gpio_setting(rf, gpio_idx, path, inv, src) rtw_hal_bb_gpio_setting((rf)->hal_com, gpio_idx, path, inv, src)
+#define halrf_set_gpio_func(rf, func, gpio_cfg) rtw_hal_mac_set_gpio_func((rf)->hal_com, func, gpio_cfg)
+/*#endif*/
+
+/*Set power by rate, power limit, power */
+#define halrf_mac_write_pwr_limit_rua_reg(rf, band) rtw_hal_mac_write_pwr_limit_rua_reg((rf)->hal_com, band)
+#define halrf_mac_write_pwr_limit_reg(rf, band) rtw_hal_mac_write_pwr_limit_reg((rf)->hal_com, band)
+#define halrf_mac_write_pwr_by_rate_reg(rf, band) rtw_hal_mac_write_pwr_by_rate_reg((rf)->hal_com, band)
+#define halrf_bb_set_tx_pow_ref(rf, phy_idx) rtw_hal_bb_set_tx_pow_ref((rf)->hal_com, phy_idx)
+#define halrf_mac_write_pwr_ofst_mode(rf, phy_idx) rtw_hal_mac_write_pwr_ofst_mode((rf)->hal_com, phy_idx)
+#define halrf_mac_write_pwr_ofst_bw(rf, phy_idx) rtw_hal_mac_write_pwr_ofst_bw((rf)->hal_com, phy_idx)
+#define halrf_mac_write_pwr_limit_en(rf, phy_idx) rtw_hal_mac_write_pwr_limit_en((rf)->hal_com, phy_idx)
+#define halrf_bb_set_pow_patten_sharp(rf, channel, is_cck, sharp_id, phy_idx) rtw_hal_bb_set_pow_patten_sharp((rf)->hal_com, channel, is_cck, sharp_id, phy_idx)
+
+#if defined(HALRF_CONFIG_FW_DBCC_OFLD_SUPPORT) || defined(HALRF_CONFIG_FW_IO_OFLD_SUPPORT)
+/*FW offload*/
+#define halrf_mac_add_cmd_ofld(rf, cmd) rtw_hal_mac_add_cmd_ofld((rf)->hal_com, cmd)
+#endif
+
+/*BB related*/
+#define halrf_bb_ctrl_rx_cca(rf, cca_en, phy_idx) rtw_hal_bb_ctrl_rx_cca((rf)->hal_com, cca_en, phy_idx)
+#define halrf_bb_ctrl_cck_en(rf, cck_en, phy_idx) rtw_hal_bb_ctrl_cck_en((rf)->hal_com, cck_en, phy_idx)
+#define halrf_bb_query_cck_en(rf, phy_idx) rtw_hal_bb_query_cck_en((rf)->hal_com, phy_idx)
+#define halrf_bb_adc_cfg(rf, bw, path, phy_idx) rtw_hal_bb_adc_cfg((rf)->hal_com, bw, path, phy_idx)
+#define halrf_bb_bb_reset_cmn(rf, en, phy_idx) rtw_hal_bb_bb_reset_cmn((rf)->hal_com, en, phy_idx)
+
+#define halrf_mutex_init(rf, mutex) hal_mutex_init((rf)->hal_com, mutex)
+#define halrf_mutex_deinit(rf, mutex) hal_mutex_deinit((rf)->hal_com, mutex)
+#define halrf_mutex_lock(rf, mutex) hal_mutex_lock((rf)->hal_com, mutex)
+#define halrf_mutex_unlock(rf, mutex) hal_mutex_unlock((rf)->hal_com, mutex)
+
+/*Share Xtal*/
+#define harlf_mac_set_xsi(rf, offset, val) rtw_hal_mac_set_xsi((rf)->hal_com, offset, val)
+#define harlf_mac_get_xsi(rf, offset, val) rtw_hal_mac_get_xsi((rf)->hal_com, offset, val)
+
+/*SER control*/
+#define halrf_mac_ctrl_ser(rf, rsn, en) rtw_hal_mac_ctrl_ser((rf)->hal_com, rsn, en)
+
+#ifdef CONFIG_PHL_DFS
+/*BB DFS*/
+#define halrf_is_radar_detect_enabled(rf, phy_idx) rtw_hal_is_radar_detect_enabled((rf)->hal_com, phy_idx)
+#define halrf_bb_dfs_rpt_cfg(rf, phy_idx, dfs_en) rtw_hal_bb_dfs_rpt_cfg((rf)->hal_com, phy_idx, dfs_en)
+#endif
+
+#ifdef CONFIG_PHL_DIAGNOSE
+#define halrf_dz_event(rf, type, level, version, buf, len) rtw_hal_rf_diagnostic_event((rf)->hal_com, type, level, version, buf, len)
+#else
+#define halrf_dz_event(rf, type, level, version, buf, len)
+#endif
+
+/*@--------------------------[Enum]------------------------------------------*/
+
+
+/*@--------------------------[Structure]-------------------------------------*/
+
+/*@--------------------------[Prptotype]-------------------------------------*/
+struct bb_info;
+
+u32 halrf_cal_bit_shift(u32 bit_mask);
+
+u32 halrf_get_sys_time(struct rf_info *rf);
+
+void halrf_wmac(struct rf_info *rf, u32 addr, u32 mask, u32 val);
+
+void halrf_wreg(struct rf_info *rf, u32 addr, u32 bit_mask, u32 val);
+
+bool halrf_polling_bb(struct rf_info *rf, u32 addr, u32 mask, u32 val, u32 count);
+
+bool halrf_polling_rf(struct rf_info *rf, u32 path, u32 addr, u32 mask, u32 val, u32 count);
+
+u32 halrf_rreg(struct rf_info *rf, u32 addr, u32 bit_mask);
+
+void halrf_wrf(struct rf_info *rf, enum rf_path path, u32 addr, u32 mask, u32 val);
+
+u32 halrf_rrf(struct rf_info *rf, enum rf_path path, u32 addr, u32 mask);
+
+void halrf_fill_h2c_cmd(struct rf_info *rf, u16 cmdlen, u8 cmdid,
+			u8 classid, u32 cmdtype, u32 *pval);
+
+void halrf_fw_log_tas(struct rf_info *rf, u16 len, u8 *c2h);
+
+void halrf_delay_us(struct rf_info *rf, u32 count);
+
+u32 halrf_rmac32(struct rf_info *rf, u32 addr);
+#endif

3rd/devourer/hal/halrf/g6/vendor/halrf_iqk.h

@@ -0,0 +1,138 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2019 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef _HALRF_IQK_H_
+#define _HALRF_IQK_H_
+
+/*@--------------------------Define Parameters-------------------------------*/
+#define TXIQK 0
+#define RXIQK 1
+#define RXIQK1 2
+#define RXIQK2 3
+#define NBTXK 4
+#define NBRXK 5
+//#define NUM 2
+
+#define ID_TXAGC 0x0
+#define ID_FLoK_coarse 0x1
+#define ID_FLoK_fine 0x2
+#define ID_TXK 0x3
+#define ID_RXAGC 0x4
+#define ID_RXK 0x5
+#define ID_NBTXK 0x6
+#define ID_NBRXK 0x7
+#define ID_FLOK_vbuffer 0x8
+#define ID_A_FLoK_coarse 0x9
+#define ID_G_FLoK_coarse 0xa
+#define ID_A_FLoK_fine 0xb
+#define ID_G_FLoK_fine 0xc
+#define ID_TX_PAD_GainGapK 0xe
+#define ID_TX_PA_GainGapK 0xf
+#define ID_IQK_Restore 0x10
+
+/*@-----------------------End Define Parameters-----------------------*/
+
+struct halrf_iqk_info {
+	bool lok_cor_fail[2][NUM]; /*channel/path */
+	bool lok_fin_fail[2][NUM]; /*channel/path */
+	bool iqk_tx_fail[2][NUM]; /*channel/path */
+	bool iqk_rx_fail[2][NUM]; /*channel/path */
+	u32 iqk_cnt;
+	u32 iqk_fail_cnt;
+	bool segment_iqk;
+	bool is_iqk_enable;
+	bool is_iqk_init;
+	bool is_reload;
+	u32 iqk_channel[2];
+	u8 iqk_band[NUM];
+	u8 iqk_ch[NUM];
+	u8 iqk_bw[NUM];
+	u8 kcount;
+	u8 iqk_times;
+	u8 rxiqk_step;
+	u8 iqk_step;
+	u8 version;
+	u32 lok_idac[2][NUM];
+	u32 lok_vbuf[2][NUM];
+	u32 iqc_gain;
+	u32 rftxgain[NUM];
+	u32 rfrxgain[NUM];
+	u32 nb_txcfir[NUM];
+	u32 nb_rxcfir[NUM];
+	u32 rximr[NUM];
+	u32 syn1to2;
+	u32 bp_txkresult[2];
+	u32 bp_rxkresult[2];
+	u32 bp_lokresult[2];
+	u32 bp_iqkenable[2];
+	u32 reload_cnt;
+	bool is_wb_txiqk[2];
+	bool is_wb_rxiqk[2];
+	bool is_nbiqk;
+	bool iqk_fft_en;
+	bool iqk_xym_en;
+	bool iqk_sram_en;
+	bool iqk_cfir_en;
+	u8 ther_avg[2][8];	/*path*/
+	u8 ther_avg_idx;
+	u8 thermal[2];
+	bool thermal_rek_en;
+	u8 iqk_mcc_ch[2][NUM];
+	u8 iqk_table_idx[NUM];
+	bool is_fw_iqk;
+	u32	time;
+	u32 lok_0x58[2];
+	u32 lok_0x5c[2];
+	u32 lok_0x7c[2];	
+};
+
+enum halrf_iqk_dz{
+	DZ_IQK_ALIMTK_TIMEOUT1	= BIT(0),
+	DZ_IQK_ALIMTK_TIMEOUT2	= BIT(1),
+	DZ_LOK_ALIMTK	= BIT(2),	
+	DZ_TXIQK_ALIMTK	= BIT(3),	
+	DZ_RXIQK_ALIMTK = BIT(4),	
+	DZ_TXXYM_ALIMTK = BIT(5),
+	DZ_RXXYM_ALIMTK = BIT(6),
+	DZ_RXAGC_ALIMTK = BIT(7),
+};
+
+
+void halrf_iqk_init(struct rf_info *rf);
+void halrf_iqk(struct rf_info *rf, enum phl_phy_idx phy_idx, bool force);
+u32 halrf_get_iqk_ver(struct rf_info *rf);
+void halrf_iqk_toneleakage(void *rf_void, u8 path);
+void halrf_nbiqk_enable(void *rf_void, bool iqk_nbiqk_en);
+void halrf_iqk_tx_bypass(void *rf_void, u8 path);
+void halrf_iqk_rx_bypass(void *rf_void, u8 path);
+void halrf_iqk_lok_bypass(void *rf_void, u8 path);
+void halrf_iqk_xym_enable(void *rf_void, bool iqk_xym_en);
+void halrf_iqk_fft_enable(void *rf_void, bool iqk_fft_en);
+void halrf_iqk_cfir_enable(void *rf_void, bool iqk_cfir_en);
+void halrf_iqk_sram_enable(void *rf_void, bool iqk_sram_en);
+void halrf_iqk_reload(void *rf_void, u8 path);
+void halrf_iqk_dbcc(void *rf_void, u8 path);
+#ifdef HALRF_MCC_DBCC
+u8 halrf_iqk_get_mcc_ch0(void *rf_void);
+u8 halrf_iqk_get_mcc_ch1(void *rf_void);
+#endif
+void halrf_enable_fw_iqk(void *rf_void, bool is_fw_iqk);
+u8 halrf_iqk_get_rxevm(void *rf_void);
+u32 halrf_iqk_get_rximr(void *rf_void, u8 path, u32 idx);
+bool halrf_check_fwiqk_done(struct rf_info *rf);
+
+
+
+
+#endif

3rd/devourer/hal/halrf/g6/vendor/halrf_kfree.h

@@ -0,0 +1,50 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2019 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef _HALRF_KFREE_H_
+#define _HALRF_KFREE_H_
+
+#if 0
+#define RX_GAIN_K_PATH_MAX 2
+#define RX_GAIN_K_OFFSET_MAX 5
+#define RX_GAIN_K_HIDE_OFFSET_MAX 4
+#endif
+
+enum BITMASK {
+	LOW_MASK = 0,
+	HIGH_MASK = 1
+};
+
+struct halrf_kfree_info{
+	u8 efuse_content[100];
+	s8 thermal_trim[MAX_RF_PATH];
+	bool thermal_trim_protect[MAX_RF_PATH];
+
+#if 0
+	bool efuse_chenk;
+	bool hide_efuse_chenk;
+	s8 rx_gain_offset[RX_GAIN_K_PATH_MAX][RX_GAIN_K_OFFSET_MAX];
+	s8 rx_gain_cs[RX_GAIN_K_PATH_MAX][RX_GAIN_K_HIDE_OFFSET_MAX];
+	s8 rx_gain_cg[RX_GAIN_K_PATH_MAX][RX_GAIN_K_HIDE_OFFSET_MAX];
+
+	s8 rx_lna_err_2g[RX_GAIN_K_PATH_MAX][7];
+	s8 rx_lna_err_5g[RX_GAIN_K_PATH_MAX][7];
+
+	s8 rx_frontend_loss[RX_GAIN_K_PATH_MAX];
+	s8 rx_rpl_bias_comp[RX_GAIN_K_PATH_MAX];
+	s8 rx_rssi_bias_comp[RX_GAIN_K_PATH_MAX];
+#endif
+};
+
+#endif	/*_HALRF_SET_PWR_TABLE_H_*/

3rd/devourer/hal/halrf/g6/vendor/halrf_outsrc_def.h

@@ -0,0 +1,192 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2020  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+#ifndef __HALRF_OUTSRC_DEF_H__
+#define __HALRF_OUTSRC_DEF_H__
+
+struct rf_info;
+
+struct halrf_fem_info {
+	u8 elna_2g;		/*@with 2G eLNA  NO/Yes = 0/1*/
+	u8 elna_5g;		/*@with 5G eLNA  NO/Yes = 0/1*/
+	u8 elna_6g;		/*@with 6G eLNA  NO/Yes = 0/1*/
+	u8 epa_2g;		/*@with 2G ePA    NO/Yes = 0/1*/
+	u8 epa_5g;		/*@with 5G ePA    NO/Yes = 0/1*/
+	u8 epa_6g;		/*@with 6G ePA    NO/Yes = 0/1*/
+};
+
+enum halrf_rfk_err_type {
+	HALRF_RFK_ERR_IQK = BIT(0),
+	HALRF_RFK_ERR_DPK = BIT(1),
+	HALRF_RFK_ERR_DACK = BIT(2),
+	HALRF_RFK_ERR_RXDCK = BIT(3),
+	HALRF_RFK_ERR_TXGAPK = BIT(4),
+	HALRF_RFK_ERR_TSSI = BIT(5),
+};
+
+enum halrf_notify_type {
+	HALRF_NOTIFY_UNDEF = 0,
+	HALRF_NOTIFY_RFK_ERR = 1,
+	HALRF_NOTIFY_MAX = 0xFF
+};
+
+/* err code version follow framework */
+struct halrf_err_code_v1 {
+	u32 iqk;
+	u32 dpk;
+	u32 dack;
+	u32 rxdck;
+	u32 txgapk;
+	u32 tssi;
+};
+
+/* IQK Report */
+struct halrf_ex_iqk_rpt_v1 {
+	u32 iqk_dz_lok[2][4]; /* path/value */
+	u32 iqk_dz_tx_xym[2][4]; /* path/value */
+	u32 iqk_dz_rx_xym[2][4]; /* path/value */
+	u32 iqk_dz_rx_rxbb[2][4]; /* path/value */
+	u32 iqk_dz_s0_rxsram[4][1280]; /* group/value */
+	u32 iqk_dz_s1_rxsram[4][1280]; /* group/value */
+};
+
+/* DPK Report */
+struct halrf_ex_dpk_rpt_v1 {
+	u32 dpk_rxsram[4][512];
+	u32 dpk_pas[4][32];
+};
+
+/* RT Report */
+struct halrf_ex_rt_rpt_v2 {
+	u32 ch_info[10][2][3]; //last10 /cv
+	u32 tssi_code[10][2]; //tssi/path
+	u32 drv_lck_fail_count;
+	u32 fw_lck_fail_count;
+};
+
+struct halrf_ex_rt_rpt_v1 {
+	u32 ch_info[10][2][2]; //last10 /cv
+	u8 tssi_code[10][2]; //tssi/path
+	u32 drv_lck_fail_count;
+	u32 fw_lck_fail_count;
+};
+
+/* TXGAPK Report */
+struct halrf_ex_txgapk_rpt_v1 {
+	u32 txgapk_dz_max_nctl_cnt; 
+	s32 txgapk_dz_track_d[2][17];
+	s32 txgapk_dz_power_d[2][17];
+};
+
+
+/*
+ * Note: when change happen on err code or sub report(iqk/dpk/rt/...),
+ *       add struct halrf_outsrc_rpt_vxxx
+ *       and set HALRF_OUTSRC_FRAMEWORK_VER/HALRF_XXX_RPT to corresponding version
+ */
+#define HALRF_OUTSRC_FRAMEWORK_VER 2
+typedef struct halrf_outsrc_rpt_v2 HALRF_OUTSRC_RPT;
+#define HALRF_OUTSRC_IQK_RPT_VER 1
+typedef struct halrf_ex_iqk_rpt_v1 HALRF_IQK_RPT;
+#define HALRF_OUTSRC_DPK_RPT_VER 1
+typedef struct halrf_ex_dpk_rpt_v1 HALRF_DPK_RPT;
+#define HALRF_OUTSRC_RT_RPT_VER 2
+typedef struct halrf_ex_rt_rpt_v2 HALRF_RT_RPT;
+#define HALRF_OUTSRC_TXGAPK_RPT_VER 1
+typedef struct halrf_ex_txgapk_rpt_v1 HALRF_TXGAPK_RPT;
+
+/* OUTSRC Report */
+struct halrf_outsrc_rpt_v2 { /*** changelog: update rt_rpt to v2 ***/
+	struct halrf_err_code_v1 err; /* err code version follow framework */
+	u8 iqk_rpt_ver;
+	struct halrf_ex_iqk_rpt_v1 iqk_rpt;
+	u8 dpk_rpt_ver;
+	struct halrf_ex_dpk_rpt_v1 dpk_rpt;
+	u8 rt_rpt_ver;
+	struct halrf_ex_rt_rpt_v2 rt_rpt;
+	u8 txgapk_rpt_ver;
+	struct halrf_ex_txgapk_rpt_v1 txgapk_rpt;
+};
+
+struct halrf_outsrc_rpt_v1 {
+	struct halrf_err_code_v1 err; /* err code version follow framework */
+	u8 iqk_rpt_ver;
+	struct halrf_ex_iqk_rpt_v1 iqk_rpt;
+	u8 dpk_rpt_ver;
+	struct halrf_ex_dpk_rpt_v1 dpk_rpt;
+	u8 rt_rpt_ver;
+	struct halrf_ex_rt_rpt_v1 rt_rpt;
+	u8 txgapk_rpt_ver;
+	struct halrf_ex_txgapk_rpt_v1 txgapk_rpt;
+};
+
+struct halrf_rt_rpt {
+	u32 ch_info[10][2][3]; //last10 /cv
+	u32 tssi_code[10][2]; //tssi/path
+	u32 drv_lck_fail_count;
+	u32 fw_lck_fail_count;
+};
+
+struct halrf_rfk_dz_rpt {
+	u32 iqk_dz_code;
+	u32 dpk_dz_code;
+	u32 dpk_rxsram[4][512];
+	u32 dpk_pas[4][32];
+	u32 dack_dz_code;
+	u32 rxdck_dz_code;
+	u32 txgapk_dz_code;
+	u32 tssi_dz_code;
+//IQK
+	u32 iqk_dz_lok[2][4]; //path/value
+	u32 iqk_dz_tx_xym[2][4];//path/value
+	u32 iqk_dz_rx_xym[2][4];//path/value
+	u32 iqk_dz_rx_rxbb[2][4];//path/value
+	u32 iqk_dz_s0_rxsram[4][1280]; //group/value
+	u32 iqk_dz_s1_rxsram[4][1280]; //group/value
+
+//TXGAPK
+	u32 txgapk_dz_max_nctl_cnt; 
+	s32 txgapk_dz_track_d[2][17];
+	s32 txgapk_dz_power_d[2][17];
+};
+
+
+struct halrf_ex_dz_info {
+	struct halrf_rt_rpt rf_rt_rpt;
+	struct halrf_rfk_dz_rpt rfk_dz_rpt;
+};
+
+
+struct halrf_fem_info halrf_ex_efem_info(struct rf_info *rf);
+
+struct halrf_ex_dz_info halrf_ex_rfdz_info(struct rf_info *rf);
+
+enum rtw_hal_status halrf_query_rfdz_err_code(void *rf_void, u32 *err_code);
+
+enum rtw_hal_status halrf_query_rf_diag_buf_len(u32 *len);
+enum rtw_hal_status halrf_query_rf_diag_buf(void *rf_void, u8 *ver, u8 *buf, u32 buf_len);
+
+enum rtw_hal_status halrf_query_rfdz_info(void *rf_void, u8 *rt_rpt_buf, u32 rt_buf_len, u8 *rfk_rpt_buf, u32 rfk_buf_len);
+#endif
+

3rd/devourer/hal/halrf/g6/vendor/halrf_pmac.c

@@ -0,0 +1,180 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2019 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+ 
+#include "halrf_precomp.h"
+
+void halrf_set_pseudo_cw(struct rf_info *rf, enum rf_path path,
+			u16 txagc_cw, bool en)
+{
+	u32 cw_addr[2] = {0x7c10, 0x7d10};
+
+	if (path >= halrf_max_path_num(rf))
+		return;
+
+	halrf_wreg(rf, cw_addr[path], 0x000001FF, txagc_cw & 0x1ff);
+	halrf_wreg(rf, cw_addr[path], BIT(9), en);
+
+	if (en)
+		RF_DBG(rf, DBG_RF_RFK,
+		       "[RFK] Set S%d Pseudo_CW RF:0x%x, BB:%d(x0.125)\n",
+		       path, (txagc_cw & 0x1f8) >> 3, txagc_cw & 0x7);
+	else
+		RF_DBG(rf, DBG_RF_RFK,
+		       "[RFK] Set S%d Pseudo_CW off!!\n", path);
+}
+
+void halrf_set_plcp_usr_info(struct rf_info *rf, struct halbb_plcp_info *plcp,
+				struct rf_pmac_tx_info *tx_info)
+{
+	plcp->usr[0].mcs = tx_info->mcs;
+	plcp->usr[0].mpdu_len = 0; /*def*/
+	plcp->usr[0].n_mpdu = 0;   /*def*/
+	plcp->usr[0].fec = 0;
+	plcp->usr[0].dcm = 0;
+	plcp->usr[0].aid = 0;
+	plcp->usr[0].scrambler_seed = 100;   /*rand(1~255)*/
+	plcp->usr[0].random_init_seed = 100; /*rand(1~255)*/
+	plcp->usr[0].apep = tx_info->length;
+	plcp->usr[0].ru_alloc = 0;
+	plcp->usr[0].nss = tx_info->nss;
+	plcp->usr[0].txbf = 0; /*def*/
+	plcp->usr[0].pwr_boost_db = 0;
+
+	RF_DBG(rf, DBG_RF_RFK,
+	       "[RFK] Set PLCP usr (mcs:%d, length:%d, nss:%d)\n",
+	       tx_info->mcs, tx_info->length, tx_info->nss);
+}
+
+void halrf_set_plcp_para_info(struct rf_info *rf, struct halbb_plcp_info *plcp,
+				struct rf_pmac_tx_info *tx_info)
+{
+	plcp->dbw = tx_info->bw; /*0:BW20, 1:BW40, 2:BW80, 3:BW160/BW80+80*/
+	plcp->source_gen_mode = 3; /*def*/
+	plcp->locked_clk = 1; /*def*/
+	plcp->dyn_bw = 0; /*def*/
+	plcp->ndp_en = 0; /*def*/
+	plcp->long_preamble_en = tx_info->long_preamble_en;
+	plcp->stbc = 0;
+	plcp->gi = tx_info->gi;
+	plcp->tb_l_len = 0;
+	plcp->tb_ru_tot_sts_max = 0;
+	plcp->vht_txop_not_allowed = 0;
+	plcp->tb_disam = 0;
+	plcp->doppler = 0; /*def*/
+	plcp->he_ltf_type = 0;
+	plcp->ht_l_len = 0; /*def*/
+	plcp->preamble_puncture = 0; /*def*/
+	plcp->he_mcs_sigb = 0;
+	plcp->he_dcm_sigb = 0;
+	plcp->he_sigb_compress_en = 1; /*def*/
+	plcp->max_tx_time_0p4us = 0;
+	plcp->ul_flag = 0; /*def*/
+	plcp->tb_ldpc_extra = 0;
+	plcp->bss_color = 0;
+	plcp->sr = 0; /*def*/
+	plcp->beamchange_en = 1; /*def*/
+	plcp->he_er_u106ru_en = 0;
+	plcp->ul_srp1 = 0; /*def*/
+	plcp->ul_srp2 = 0; /*def*/
+	plcp->ul_srp3 = 0; /*def*/
+	plcp->ul_srp4 = 0; /*def*/
+	plcp->mode = 0;
+	plcp->group_id = 0;
+	plcp->ppdu_type = tx_info->ppdu;
+	plcp->txop = 127; /*def*/
+	plcp->tb_strt_sts = 0;
+	plcp->tb_pre_fec_padding_factor = 0;
+	plcp->cbw = 0;
+	plcp->txsc = 0;
+	plcp->tb_mumimo_mode_en = 0;
+	plcp->nominal_t_pe = 2; /*def*/
+	plcp->ness = 0; /*def*/
+	plcp->n_user = 1;
+	plcp->tb_rsvd = 0; /*def*/
+
+	/*halrf_mem_cpy(rf, plcp->usr, rf->usr, 4*sizeof(struct usr_plcp_gen_in));*/
+
+	RF_DBG(rf, DBG_RF_RFK,
+	       "[RFK] Set PLCP para (BW:%d, long_preamble:%d, GI:%d, PPDU:%d)\n",
+	       tx_info->bw, tx_info->long_preamble_en, tx_info->gi ,tx_info->ppdu);
+}
+
+void halrf_set_pmac_plcp_gen(struct rf_info *rf, enum phl_phy_idx phy_idx,
+			struct rf_pmac_tx_info *tx_info)
+{
+	struct halbb_plcp_info plcp = {0};
+	u8 sts = 0;
+
+	halrf_set_plcp_usr_info(rf, &plcp, tx_info);
+
+	halrf_set_plcp_para_info(rf, &plcp, tx_info);
+
+	rtw_hal_bb_set_plcp_tx((rf)->hal_com, (void*)&plcp, (void*)&plcp.usr, phy_idx, &sts);
+}
+
+void halrf_set_pmac_tx(struct rf_info *rf, enum phl_phy_idx phy_idx,
+			enum rf_path path, struct rf_pmac_tx_info *tx,
+			u8 enable, bool by_cw)
+{
+	if (enable) {
+		RF_DBG(rf, DBG_RF_RFK,
+			"[RFK] Set S%d PMAC Tx (PHY%d)\n", path, phy_idx);
+
+		halrf_set_pmac_plcp_gen(rf, phy_idx, tx);
+
+		if (path < halrf_max_path_num(rf)) {
+			rtw_hal_bb_cfg_tx_path((rf)->hal_com, path, phy_idx);
+			rtw_hal_bb_cfg_rx_path((rf)->hal_com, path, phy_idx);
+		}
+
+		if (by_cw)
+			halrf_set_pseudo_cw(rf, path, tx->txagc_cw, true);
+		else
+			rtw_hal_bb_set_power((rf)->hal_com, tx->dbm, phy_idx);
+	} else
+		RF_DBG(rf, DBG_RF_RFK, "[RFK] Disable PMAC Tx!!\n");
+
+	rtw_hal_bb_set_pmac_packet_tx((rf)->hal_com, enable, tx->is_cck, tx->cnt,
+				 tx->period, tx->time, false, phy_idx);
+}
+
+#if 0
+void halrf_set_pmac_tx(struct rf_info *rf, enum phl_phy_idx phy_idx,
+			enum rf_path path, enum packet_format_t ppdu_type, u8 case_id,
+			s16 dbm, u8 enable, u8 is_cck, u16 cnt ,u16 time, u16 period)
+{
+#if 1
+	if (enable) {
+		RF_DBG(rf, DBG_RF_RFK,
+		       "[RFK] Set PMAC Tx (PHY%d, S%d, PPDU:%d, case:%d)\n",
+		       phy_idx, path, ppdu_type, case_id);
+		RF_DBG(rf, DBG_RF_RFK,
+	 	       "[RFK] Set PMAC Tx (%ddBm, Cnt:%d, time:%d, period:%d)\n",
+		       dbm, cnt, time, period);
+
+		//halrf_set_pmac_pattern(rf, ppdu_type, case_id, phy_idx);
+		halrf_set_pmac_plcp_gen(rf, 7, 0, 1, 0, 0, 1, ppdu_type, phy_idx);
+		halrf_cfg_tx_path(rf, path);
+		//halrf_set_pmac_power(rf, dbm, phy_idx);
+		halrf_set_pseudo_cw(rf, path, 0x1d0, true);
+	} else
+		RF_DBG(rf, DBG_RF_RFK, "[RFK] Disable PMAC Tx!!\n");
+
+	halrf_set_pmac_packet_tx(rf, enable, is_cck, cnt, period, time, phy_idx);
+#endif
+}
+#endif
+

3rd/devourer/hal/halrf/g6/vendor/halrf_pmac.h

@@ -0,0 +1,55 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2019 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef _HALRF_PMAC_H_
+#define _HALRF_PMAC_H_
+/*@--------------------------[Define] ---------------------------------------*/
+
+/*@--------------------------[Enum]------------------------------------------*/
+
+/*@--------------------------[Structure]-------------------------------------*/
+struct rf_pmac_tx_info {
+	enum packet_format_t ppdu;
+	u8 mcs;
+	u8 bw;
+	u8 nss;
+	u8 long_preamble_en;
+	u8 gi;
+	u16 case_id;
+	s16 dbm;
+	u16 txagc_cw;
+	u8 is_cck;
+	u16 cnt;
+	u16 time;
+	u16 period;
+	u16 length;
+};
+
+/*@--------------------------[Prptotype]-------------------------------------*/
+void halrf_set_pmac_cw(struct rf_info *rf, enum rf_path path, u16 txagc_cw, bool en);
+
+void halrf_set_pmac_tx(struct rf_info *rf, enum phl_phy_idx phy_idx,
+			enum rf_path path, struct rf_pmac_tx_info *tx,
+			u8 enable, bool by_cw);
+
+void halrf_set_pseudo_cw(struct rf_info *rf, enum rf_path path,
+			u16 txagc_cw, bool en);
+
+#if 0
+void halrf_set_pmac_tx(struct rf_info *rf, enum phl_phy_idx phy_idx,
+						enum rf_path path, u8 ppdu_type, u8 case_id, s16 dbm,
+						u8 enable, u8 is_cck, u16 cnt ,u16 time, u16 period);
+#endif
+
+#endif

3rd/devourer/hal/halrf/g6/vendor/halrf_precomp.h

@@ -0,0 +1,426 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2020  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+#ifndef __HALRF_PRECOMP_H__
+#define __HALRF_PRECOMP_H__
+
+/*---[Define in upper layer] ----------------------------------------------------------*/
+#include "../../hal_headers_le.h"
+/*@--------------------------[Define] ---------------------------------------*/
+
+#ifdef CONFIG_RTL8852A
+    #define RF_8852A_SUPPORT
+#endif
+
+#ifdef CONFIG_RTL8852B
+    #define RF_8852B_SUPPORT
+#endif
+
+#ifdef CONFIG_RTL8852BT
+    #define RF_8852BT_SUPPORT
+#endif
+
+#ifdef CONFIG_RTL8852BPT
+    #define RF_8852BPT_SUPPORT
+#endif
+
+#ifdef CONFIG_RTL8852C
+	#define RF_8852C_SUPPORT
+#endif
+
+#ifdef CONFIG_RTL8842A
+	#define RF_8852C_SUPPORT
+	#define RF_8842A_SUPPORT
+#endif
+
+
+#ifdef CONFIG_RTL8852D
+//	#ifdef PHL_PLATFORM_AP
+//    #define RF_8832D_SUPPORT
+//	#else
+	#define RF_8852D_SUPPORT
+	#define RF_8832D_SUPPORT
+//	#endif
+#endif
+
+#ifdef CONFIG_RTL8832BR
+    #define RF_8832BR_SUPPORT
+#endif
+
+#ifdef CONFIG_RTL8192XB
+    #define RF_8192XB_SUPPORT
+#endif
+
+#ifdef CONFIG_RTL8852BP
+    #define RF_8852BP_SUPPORT
+#endif
+
+#ifdef CONFIG_RTL8851B
+    #define RF_8851B_SUPPORT
+#endif
+
+#ifdef CONFIG_RTL8832CRVU
+    #define RF_8832CRVU_SUPPORT
+#endif
+
+#ifdef CONFIG_RTL8832BRVT
+    #define RF_8832BRVT_SUPPORT
+#endif
+
+#define	MASKBYTE0		0xff
+#define	MASKBYTE1		0xff00
+#define	MASKBYTE2		0xff0000
+#define	MASKBYTE3		0xff000000
+#define	MASKHWORD		0xffff0000
+#define	MASKLWORD		0x0000ffff
+#define	MASKDWORD		0xffffffff
+#define	MASKRF		0xfffff
+#define	MASKRFMODE		0xf0000
+#define	MASKRFRXBB		0x003e0
+#define	MASKTXPWR		0x0003f
+#define	INVALID_RF_DATA 0xffffffff
+
+
+/*---[Define Only] ----------------------------------------------------------*/
+//#include "../../hal_headers_le.h"
+#include "halrf_ic_hw_info.h"
+#include "halrf_ic_sw_info.h"
+
+#ifdef CONFIG_RTL8730A
+    #define RF_8730A_SUPPORT
+#endif
+
+/*---[Include structure & prototype] ----------------------------------------*/
+
+#include "halrf_outsrc_def.h"
+#include "halrf_hw_cfg.h"
+#include "halrf_hw_cfg_ex.h"
+#include "halrf_interface.h"
+#include "halrf_dbg_cmd.h"
+#include "halrf_dbg.h"
+#include "halrf_txgapk.h"
+#include "halrf_pwr_track.h"
+#include "halrf_iqk.h"
+#include "halrf_dpk.h"
+#include "halrf_dack.h"
+#include "halrf_pmac.h"
+//#include "halrf_dbg_cmd.h"
+#include "halrf_dbg_cmd_ex.h"
+#include "halrf_init.h"
+#include "halrf_init_ex.h"
+#include "halrf_pwr_table.h"
+#include "halrf_api.h"
+#include "halrf_psd.h"
+#include "halrf_kfree.h"
+#include "halrf_hwimg.h"
+#include "halrf_tas.h"
+#ifdef RF_8852A_SUPPORT
+#include "halrf_8852a/halrf_dack_8852a.h"
+#include "halrf_8852a/halrf_hwimg_8852a.h"
+#include "halrf_8852a/halrf_kfree_8852a.h"
+#endif
+
+#ifdef RF_8852B_SUPPORT
+#include "halrf_8852b/halrf_dack_8852b.h"
+#include "halrf_8852b/halrf_hwimg_8852b.h"
+#include "halrf_8852b/halrf_kfree_8852b.h"
+#endif
+
+#ifdef RF_8852BT_SUPPORT
+#include "halrf_8852bt/halrf_dack_8852bt.h"
+#include "halrf_8852bt/halrf_hwimg_8852bt.h"
+#include "halrf_8852bt/halrf_kfree_8852bt.h"
+#endif
+
+#ifdef RF_8852BPT_SUPPORT
+#include "halrf_8852bpt/halrf_dack_8852bpt.h"
+#include "halrf_8852bpt/halrf_hwimg_8852bpt.h"
+#include "halrf_8852bpt/halrf_kfree_8852bpt.h"
+#endif
+
+#ifdef RF_8852C_SUPPORT
+#include "halrf_8852c/halrf_dack_8852c.h"
+#include "halrf_8852c/halrf_hwimg_8852c.h"
+#include "halrf_8852c/halrf_kfree_8852c.h"
+#endif
+
+#ifdef RF_8842A_SUPPORT
+#include "halrf_8842a/halrf_dack_8842a.h"
+#include "halrf_8842a/halrf_hwimg_8842a.h"
+#include "halrf_8842a/halrf_kfree_8842a.h"
+#endif
+
+#ifdef RF_8852D_SUPPORT
+#include "halrf_8852d/halrf_dack_8852d.h"
+#include "halrf_8852d/halrf_hwimg_8852d.h"
+#include "halrf_8852d/halrf_kfree_8852d.h"
+#endif
+
+#ifdef RF_8832D_SUPPORT
+#include "halrf_8832d/halrf_dack_8832d.h"
+#include "halrf_8832d/halrf_hwimg_8832d.h"
+#include "halrf_8832d/halrf_kfree_8832d.h"
+#endif
+
+#ifdef RF_8832BR_SUPPORT
+#include "halrf_8832br/halrf_dack_8832br.h"
+#include "halrf_8832br/halrf_hwimg_8832br.h"
+#include "halrf_8832br/halrf_kfree_8832br.h"
+#endif
+
+#ifdef RF_8192XB_SUPPORT
+#include "halrf_8192xb/halrf_dack_8192xb.h"
+#include "halrf_8192xb/halrf_hwimg_8192xb.h"
+#include "halrf_8192xb/halrf_kfree_8192xb.h"
+#endif
+
+#ifdef RF_8852BP_SUPPORT
+#include "halrf_8852bp/halrf_dack_8852bp.h"
+#include "halrf_8852bp/halrf_hwimg_8852bp.h"
+#include "halrf_8852bp/halrf_kfree_8852bp.h"
+#endif
+
+#ifdef RF_8730A_SUPPORT
+#include "halrf_8730a/halrf_dack_8730a.h"
+#include "halrf_8730a/halrf_hwimg_8730a.h"
+#include "halrf_8730a/halrf_kfree_8730a.h"
+#endif
+
+#ifdef RF_8851B_SUPPORT
+#include "halrf_8851b/halrf_dack_8851b.h"
+#include "halrf_8851b/halrf_hwimg_8851b.h"
+#include "halrf_8851b/halrf_kfree_8851b.h"
+#endif
+
+#include "halrf.h"
+#include "halrf_ex.h"
+
+#ifdef RF_8852A_SUPPORT
+	#include "halrf_8852a/halrf_efuse_8852a.h"
+	#include "halrf_8852a/halrf_reg_cfg_8852a.h"
+	#include "halrf_8852a/halrf_8852a.h"
+	#include "halrf_8852a/halrf_8852a_api.h"
+	#include "halrf_8852a/halrf_8852a_api_ex.h"
+	#include "halrf_8852a/halrf_iqk_8852a.h"
+	#include "halrf_8852a/halrf_dpk_8852a.h"
+	#include "halrf_8852a/halrf_txgapk_8852a.h"
+	#include "halrf_8852a/halrf_version_rtl8852a.h"
+	#include "halrf_8852a/halrf_set_pwr_table_8852a.h"
+	#include "halrf_8852a/halrf_tssi_8852a.h"
+	#include "halrf_8852a/halrf_psd_8852a.h"
+	#include "halrf_8852a/halrf_ops_rtl8852a.h"
+#endif
+
+#ifdef RF_8852B_SUPPORT
+	#include "halrf_8852b/halrf_efuse_8852b.h"
+	#include "halrf_8852b/halrf_reg_cfg_8852b.h"
+	#include "halrf_8852b/halrf_8852b.h"
+	#include "halrf_8852b/halrf_8852b_api.h"
+	#include "halrf_8852b/halrf_8852b_api_ex.h"
+	#include "halrf_8852b/halrf_iqk_8852b.h"
+	#include "halrf_8852b/halrf_dpk_8852b.h"
+	#include "halrf_8852b/halrf_txgapk_8852b.h"
+	#include "halrf_8852b/halrf_version_rtl8852b.h"
+	#include "halrf_8852b/halrf_set_pwr_table_8852b.h"
+	#include "halrf_8852b/halrf_tssi_8852b.h"
+	#include "halrf_8852b/halrf_psd_8852b.h"
+	#include "halrf_8852b/halrf_ops_rtl8852b.h"
+#endif
+
+#ifdef RF_8852BT_SUPPORT
+	#include "halrf_8852bt/halrf_efuse_8852bt.h"
+	#include "halrf_8852bt/halrf_reg_cfg_8852bt.h"
+	#include "halrf_8852bt/halrf_8852bt.h"
+	#include "halrf_8852bt/halrf_8852bt_api.h"
+	#include "halrf_8852bt/halrf_8852bt_api_ex.h"
+	#include "halrf_8852bt/halrf_iqk_8852bt.h"
+	#include "halrf_8852bt/halrf_dpk_8852bt.h"
+	#include "halrf_8852bt/halrf_txgapk_8852bt.h"
+	#include "halrf_8852bt/halrf_version_rtl8852bt.h"
+	#include "halrf_8852bt/halrf_set_pwr_table_8852bt.h"
+	#include "halrf_8852bt/halrf_tssi_8852bt.h"
+	#include "halrf_8852bt/halrf_psd_8852bt.h"
+	#include "halrf_8852bt/halrf_ops_rtl8852bt.h"
+#endif
+
+#ifdef RF_8852BPT_SUPPORT
+	#include "halrf_8852bpt/halrf_efuse_8852bpt.h"
+	#include "halrf_8852bpt/halrf_reg_cfg_8852bpt.h"
+	#include "halrf_8852bpt/halrf_8852bpt.h"
+	#include "halrf_8852bpt/halrf_8852bpt_api.h"
+	#include "halrf_8852bpt/halrf_8852bpt_api_ex.h"
+	#include "halrf_8852bpt/halrf_iqk_8852bpt.h"
+	#include "halrf_8852bpt/halrf_dpk_8852bpt.h"
+	#include "halrf_8852bpt/halrf_txgapk_8852bpt.h"
+	#include "halrf_8852bpt/halrf_version_rtl8852bpt.h"
+	#include "halrf_8852bpt/halrf_set_pwr_table_8852bpt.h"
+	#include "halrf_8852bpt/halrf_tssi_8852bpt.h"
+	#include "halrf_8852bpt/halrf_psd_8852bpt.h"
+	#include "halrf_8852bpt/halrf_ops_rtl8852bpt.h"
+#endif
+
+#ifdef RF_8852C_SUPPORT
+	#include "halrf_8852c/halrf_efuse_8852c.h"
+	#include "halrf_8852c/halrf_reg_cfg_8852c.h"
+	#include "halrf_8852c/halrf_8852c.h"
+	#include "halrf_8852c/halrf_8852c_api.h"
+//	#include "halrf_8852c/halrf_8852c_api_ex.h"
+	#include "halrf_8852c/halrf_iqk_8852c.h"
+	#include "halrf_8852c/halrf_dpk_8852c.h"
+	#include "halrf_8852c/halrf_txgapk_8852c.h"
+	#include "halrf_8852c/halrf_version_rtl8852c.h"
+	#include "halrf_8852c/halrf_set_pwr_table_8852c.h"
+	#include "halrf_8852c/halrf_tssi_8852c.h"
+	#include "halrf_8852c/halrf_psd_8852c.h"
+	#include "halrf_8852c/halrf_ops_rtl8852c.h"
+#endif
+
+#ifdef RF_8842A_SUPPORT
+	#include "halrf_8842a/halrf_efuse_8842a.h"
+	#include "halrf_8842a/halrf_reg_cfg_8842a.h"
+	#include "halrf_8842a/halrf_8842a.h"
+	#include "halrf_8842a/halrf_8842a_api.h"
+//	#include "halrf_8842a/halrf_8842a_api_ex.h"
+	#include "halrf_8842a/halrf_iqk_8842a.h"
+	#include "halrf_8842a/halrf_dpk_8842a.h"
+	#include "halrf_8842a/halrf_txgapk_8842a.h"
+	#include "halrf_8842a/halrf_version_rtl8842a.h"
+	#include "halrf_8842a/halrf_set_pwr_table_8842a.h"
+	#include "halrf_8842a/halrf_tssi_8842a.h"
+	#include "halrf_8842a/halrf_psd_8842a.h"
+	#include "halrf_8842a/halrf_ops_rtl8842a.h"
+#endif
+
+#ifdef RF_8852D_SUPPORT
+	#include "halrf_8852d/halrf_efuse_8852d.h"
+	#include "halrf_8852d/halrf_reg_cfg_8852d.h"
+	#include "halrf_8852d/halrf_8852d.h"
+	#include "halrf_8852d/halrf_8852d_api.h"
+//	#include "halrf_8852d/halrf_8852d_api_ex.h"
+	#include "halrf_8852d/halrf_iqk_8852d.h"
+	#include "halrf_8852d/halrf_dpk_8852d.h"
+	#include "halrf_8852d/halrf_txgapk_8852d.h"
+	#include "halrf_8852d/halrf_version_rtl8852d.h"
+	#include "halrf_8852d/halrf_set_pwr_table_8852d.h"
+	#include "halrf_8852d/halrf_tssi_8852d.h"
+	#include "halrf_8852d/halrf_psd_8852d.h"
+	#include "halrf_8852d/halrf_ops_rtl8852d.h"
+#endif
+
+#ifdef RF_8832D_SUPPORT
+	#include "halrf_8832d/halrf_efuse_8832d.h"
+	#include "halrf_8832d/halrf_reg_cfg_8832d.h"
+	#include "halrf_8832d/halrf_8832d.h"
+	#include "halrf_8832d/halrf_8832d_api.h"
+//	#include "halrf_8832d/halrf_8832d_api_ex.h"
+	#include "halrf_8832d/halrf_iqk_8832d.h"
+	#include "halrf_8832d/halrf_dpk_8832d.h"
+	#include "halrf_8832d/halrf_txgapk_8832d.h"
+	#include "halrf_8832d/halrf_version_rtl8832d.h"
+	#include "halrf_8832d/halrf_set_pwr_table_8832d.h"
+	#include "halrf_8832d/halrf_tssi_8832d.h"
+	#include "halrf_8832d/halrf_psd_8832d.h"
+	#include "halrf_8832d/halrf_ops_rtl8832d.h"
+#endif
+
+
+#ifdef RF_8832BR_SUPPORT
+	#include "halrf_8832br/halrf_efuse_8832br.h"
+	#include "halrf_8832br/halrf_reg_cfg_8832br.h"
+	#include "halrf_8832br/halrf_8832br.h"
+	#include "halrf_8832br/halrf_8832br_api.h"
+//	#include "halrf_8832br/halrf_8832br_api_ex.h"
+	#include "halrf_8832br/halrf_iqk_8832br.h"
+	#include "halrf_8832br/halrf_dpk_8832br.h"
+	#include "halrf_8832br/halrf_txgapk_8832br.h"
+	#include "halrf_8832br/halrf_version_rtl8832br.h"
+	#include "halrf_8832br/halrf_set_pwr_table_8832br.h"
+	#include "halrf_8832br/halrf_tssi_8832br.h"
+	#include "halrf_8832br/halrf_psd_8832br.h"
+	#include "halrf_8832br/halrf_ops_rtl8832br.h"
+#endif
+
+#ifdef RF_8192XB_SUPPORT
+	#include "halrf_8192xb/halrf_efuse_8192xb.h"
+	#include "halrf_8192xb/halrf_reg_cfg_8192xb.h"
+	#include "halrf_8192xb/halrf_8192xb.h"
+	#include "halrf_8192xb/halrf_8192xb_api.h"
+//	#include "halrf_8192xb/halrf_8192xb_api_ex.h"
+	#include "halrf_8192xb/halrf_iqk_8192xb.h"
+	#include "halrf_8192xb/halrf_dpk_8192xb.h"
+	#include "halrf_8192xb/halrf_txgapk_8192xb.h"
+	#include "halrf_8192xb/halrf_version_rtl8192xb.h"
+	#include "halrf_8192xb/halrf_set_pwr_table_8192xb.h"
+	#include "halrf_8192xb/halrf_tssi_8192xb.h"
+	#include "halrf_8192xb/halrf_psd_8192xb.h"
+	#include "halrf_8192xb/halrf_ops_rtl8192xb.h"
+#endif
+
+#ifdef RF_8852BP_SUPPORT
+	#include "halrf_8852bp/halrf_efuse_8852bp.h"
+	#include "halrf_8852bp/halrf_reg_cfg_8852bp.h"
+	#include "halrf_8852bp/halrf_8852bp.h"
+	#include "halrf_8852bp/halrf_8852bp_api.h"
+//	#include "halrf_8852bp/halrf_8852bp_api_ex.h"
+	#include "halrf_8852bp/halrf_iqk_8852bp.h"
+	#include "halrf_8852bp/halrf_dpk_8852bp.h"
+	#include "halrf_8852bp/halrf_txgapk_8852bp.h"
+	#include "halrf_8852bp/halrf_version_rtl8852bp.h"
+	#include "halrf_8852bp/halrf_set_pwr_table_8852bp.h"
+	#include "halrf_8852bp/halrf_tssi_8852bp.h"
+	#include "halrf_8852bp/halrf_psd_8852bp.h"
+	#include "halrf_8852bp/halrf_ops_rtl8852bp.h"
+#endif
+#ifdef RF_8730A_SUPPORT
+	#include "halrf_8730a/halrf_efuse_8730a.h"
+	#include "halrf_8730a/halrf_reg_cfg_8730a.h"
+	#include "halrf_8730a/halrf_8730a.h"
+	#include "halrf_8730a/halrf_8730a_api.h"
+//	#include "halrf_8730a/halrf_8730a_api_ex.h"
+	#include "halrf_8730a/halrf_iqk_8730a.h"
+	#include "halrf_8730a/halrf_dpk_8730a.h"
+//	#include "halrf_8730a/halrf_txgapk_8730a.h"
+	#include "halrf_8730a/halrf_version_rtl8730a.h"
+	#include "halrf_8730a/halrf_set_pwr_table_8730a.h"
+	#include "halrf_8730a/halrf_tssi_8730a.h"
+	#include "halrf_8730a/halrf_psd_8730a.h"
+#endif
+
+#ifdef RF_8851B_SUPPORT
+	#include "halrf_8851b/halrf_efuse_8851b.h"
+	#include "halrf_8851b/halrf_reg_cfg_8851b.h"
+	#include "halrf_8851b/halrf_8851b.h"
+	#include "halrf_8851b/halrf_8851b_api.h"
+	#include "halrf_8851b/halrf_8851b_api_ex.h"
+	#include "halrf_8851b/halrf_iqk_8851b.h"
+	#include "halrf_8851b/halrf_dpk_8851b.h"
+	#include "halrf_8851b/halrf_txgapk_8851b.h"
+	#include "halrf_8851b/halrf_version_rtl8851b.h"
+	#include "halrf_8851b/halrf_set_pwr_table_8851b.h"
+	#include "halrf_8851b/halrf_tssi_8851b.h"
+	#include "halrf_8851b/halrf_psd_8851b.h"
+	#include "halrf_8851b/halrf_ops_rtl8851b.h"
+#endif
+
+#endif

3rd/devourer/hal/halrf/g6/vendor/halrf_psd.h

@@ -0,0 +1,43 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2019 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef _HALRF_PSD_H_
+#define _HALRF_PSD_H_
+
+#ifdef HALRF_PSD_SUPPORT
+
+/*@--------------------------Define Parameters-------------------------------*/
+#define PSD_RF_PATH_MAX 4
+#define PSD_RF_REG_NUM 10
+#define PSD_RF_DATA_NUM 400
+
+/*@-----------------------End Define Parameters-----------------------*/
+struct halrf_psd_data {
+	u8 path;
+	u8 iq_path;
+	u32 avg;
+	u32 fft;
+	u32 point;
+	u32 start_point;
+	u32 stop_point;
+	u32 average;
+	u32 buf_size;
+	u32 psd_data[PSD_RF_DATA_NUM];
+	u8 psd_result_running;
+	u32 psd_reg_backup[100];
+	u32 rf_bkup[PSD_RF_PATH_MAX][PSD_RF_REG_NUM];
+};
+
+#endif	/*HALRF_PSD_SUPPORT*/
+#endif	/*_HALRF_PSD_H_*/

3rd/devourer/hal/halrf/g6/vendor/halrf_pwr_table.h

@@ -0,0 +1,559 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2019 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef _HALRF_PWR_TABLE_H_
+#define _HALRF_PWR_TABLE_H_
+
+/*@--------------------------Define Parameters-------------------------------*/
+#define TX_TABLE_TO_TX_PWR 4
+
+#define TX_PWR_BY_RATE_NUM_RF 4
+
+#define PW_LMT_MAX_2G_BANDWITH_NUM 2
+#define PW_LMT_MAX_CHANNEL_NUMBER_2G 14
+#define PW_LMT_MAX_CHANNEL_NUMBER_5G 53
+#define PW_LMT_MAX_CHANNEL_NUMBER_6G 120
+
+#define TX_PWR_BY_RATE_NUM_MAC 44
+#define TX_PWR_LIMIT_NUM_MAC 80
+#define TX_PWR_LIMIT_RU_NUM_MAC 30
+
+#define RADIO_TO_FW_PAGE_SIZE 6
+#define RADIO_TO_FW_DATA_SIZE 500
+
+#define HALRF_TPE_TORRANCE_ANTGAIN 13	/* 6.5 dBm, unit: 0.5 dBm (multiply by 2). 1.5dB torrace for each sample, antenna gain 5dBi */
+#define HALRF_TPE_2TX_COMBINE 6	/* 2TX combine 3dB, unit: 0.5 dBm (multiply by 2).*/
+#define HALRF_TPE_TSSI_LOW_PWR_TORRACE 4	/* TSSI low power 0dBm torrace, 2 dBm, unit: 0.5 dBm (multiply by 2). */
+
+#ifndef PW_LMT_MAX_REGULATION_EXT_NUM
+#define PW_LMT_MAX_REGULATION_EXT_NUM 5
+#endif
+
+#ifndef PW_LMT_MAX_6G_REGULATION_EXT_NUM
+#define PW_LMT_MAX_6G_REGULATION_EXT_NUM 10
+#endif
+
+/*@-----------------------End Define Parameters-----------------------*/
+/*power by rate*/
+enum halrf_pw_by_rate_para_type {
+	PW_BYRATE_PARA_NSS1,
+	PW_BYRATE_PARA_NSS2,
+	PW_BYRATE_PARA_OFFS = 0xF
+};
+
+enum halrf_pw_by_rate_rate_type {
+	PW_BYRATE_RATE_11M_1M = 0,
+	PW_BYRATE_RATE_18M_6M = 1,
+	PW_BYRATE_RATE_54M_24M = 2,
+	PW_BYRATE_RATE_MCS3_0 = 3,
+	PW_BYRATE_RATE_MCS7_4 = 4,
+	PW_BYRATE_RATE_MCS11_8 = 5,
+	PW_BYRATE_RATE_DCM4_0 = 6,
+	PW_BYRATE_RATE_AllRate2_1 = 7,  /* CCK, OFDM, HT, VHT */
+	PW_BYRATE_RATE_AllRate2_2 = 8,  /* HE_HEDCM */
+	PW_BYRATE_RATE_AllRate5_1 = 9,  /* OFDM, HT, VHT, HE_HEDCM */
+	PW_BYRATE_RATE_AllRate6_1 = 10,  /* OFDM, HT, VHT, HE_HEDCM */
+	PW_BYRATE_RATE_NULL = 0xF
+};
+
+/*power limit*/
+struct halrf_tx_pw_lmt {
+	u8 band;
+	u8 bw;
+	u8 ntx;
+	u8 rs;
+	u8 bf;
+	u8 reg;
+	u8 ch;
+	s8 val;
+	u8 tx_shap_idx;
+};
+
+struct halrf_tx_pw_lmt_ru {
+	u8			band;
+	u8			bw;
+	u8			ntx;
+	u8			rs;
+	u8			reg;
+	u8			ch;
+	s8			val;
+	u8 tx_shap_idx;
+};
+
+enum halrf_tx_pw_lmt_ru_bandwidth_type {
+	PW_LMT_RU_BW_RU26 = 0,
+	PW_LMT_RU_BW_RU52,
+	PW_LMT_RU_BW_RU106,
+	PW_LMT_RU_BW_NULL
+};
+
+enum halrf_pw_lmt_regulation_type {
+	PW_LMT_REGU_NULL	= 0, /* declare this to 0xFF after limit array remove usage of PW_LMT_REGU_NULL */
+	PW_LMT_REGU_NA		= 1, /* declare this to 0xFE after limit array remove usage of PW_LMT_REGU_NA */
+	PW_LMT_REGU_WW13 = 2,
+	PW_LMT_REGU_INTERSECT = 3,
+	PW_LMT_REGU_EXT_PWR = 4,
+	/* place share index item above */
+	PW_LMT_REGU_ETSI = 5,
+	PW_LMT_REGU_FCC = 6,
+	PW_LMT_REGU_MKK = 7,
+	PW_LMT_REGU_IC = 8,
+	PW_LMT_REGU_KCC = 9,
+	PW_LMT_REGU_ACMA = 10,
+	PW_LMT_REGU_NCC = 11,
+	PW_LMT_REGU_MEXICO = 12,
+	PW_LMT_REGU_CHILE = 13,
+	PW_LMT_REGU_UKRAINE = 14,
+	PW_LMT_REGU_CNOLD = 15,
+	PW_LMT_REGU_QATAR = 16,
+	PW_LMT_REGU_UK = 17,
+	PW_LMT_REGU_CN = 18,
+	PW_LMT_REGU_THAILAND = 19,
+	PW_LMT_REGU_ETSI_DA = 20,
+	/* place predefined ones above */
+	PW_LMT_REGU_PREDEF_NUM,
+	PW_LMT_MAX_REGULATION_NUM = PW_LMT_REGU_PREDEF_NUM + PW_LMT_MAX_REGULATION_EXT_NUM
+};
+
+
+enum halrf_pw_lmt_regulation_type_6g {
+	PW_LMT_REGU_6G_NULL		= 0, /* declare this to 0xFF after limit array remove usage of PW_LMT_REGU_NULL */
+	PW_LMT_REGU_6G_NA		= 1, /* declare this to 0xFE after limit array remove usage of PW_LMT_REGU_NA */
+	PW_LMT_REGU_6G_WW13 = 2,
+	PW_LMT_REGU_6G_INTERSECT = 3,
+	PW_LMT_REGU_6G_EXT_PWR = 4,
+	/* place share index item above */
+	PW_LMT_REGU_6G_ETSI_LPI = 5,
+	PW_LMT_REGU_6G_ETSI_STD = 6,
+	PW_LMT_REGU_6G_ETSI_VLP = 7,
+	PW_LMT_REGU_6G_FCC_LPI = 8,
+	PW_LMT_REGU_6G_FCC_STD = 9,
+	PW_LMT_REGU_6G_FCC_VLP = 10,
+	PW_LMT_REGU_6G_MKK_LPI = 11,
+	PW_LMT_REGU_6G_MKK_STD = 12,
+	PW_LMT_REGU_6G_MKK_VLP = 13,
+	PW_LMT_REGU_6G_IC_LPI = 14,
+	PW_LMT_REGU_6G_IC_STD = 15,
+	PW_LMT_REGU_6G_IC_VLP = 16,
+	PW_LMT_REGU_6G_KCC_LPI = 17,
+	PW_LMT_REGU_6G_KCC_STD = 18,
+	PW_LMT_REGU_6G_KCC_VLP = 19,
+	PW_LMT_REGU_6G_ACMA_LPI = 20,
+	PW_LMT_REGU_6G_ACMA_STD = 21,
+	PW_LMT_REGU_6G_ACMA_VLP = 22,
+	PW_LMT_REGU_6G_NCC_LPI = 23,
+	PW_LMT_REGU_6G_NCC_STD = 24,
+	PW_LMT_REGU_6G_NCC_VLP = 25,
+	PW_LMT_REGU_6G_MEXICO_LPI = 26,
+	PW_LMT_REGU_6G_MEXICO_STD = 27,
+	PW_LMT_REGU_6G_MEXICO_VLP = 28,
+	PW_LMT_REGU_6G_CHILE_LPI = 29,
+	PW_LMT_REGU_6G_CHILE_STD = 30,
+	PW_LMT_REGU_6G_CHILE_VLP = 31,
+	PW_LMT_REGU_6G_UKRAINE_LPI = 32,
+	PW_LMT_REGU_6G_UKRAINE_STD = 33,
+	PW_LMT_REGU_6G_UKRAINE_VLP = 34,
+	PW_LMT_REGU_6G_CNOLD_LPI = 35,
+	PW_LMT_REGU_6G_CNOLD_STD = 36,
+	PW_LMT_REGU_6G_CNOLD_VLP = 37,
+	PW_LMT_REGU_6G_QATAR_LPI = 38,
+	PW_LMT_REGU_6G_QATAR_STD = 39,
+	PW_LMT_REGU_6G_QATAR_VLP = 40,
+	PW_LMT_REGU_6G_UK_LPI = 41,
+	PW_LMT_REGU_6G_UK_STD = 42,
+	PW_LMT_REGU_6G_UK_VLP = 43,
+	PW_LMT_REGU_6G_CN_LPI = 44,
+	PW_LMT_REGU_6G_CN_STD = 45,
+	PW_LMT_REGU_6G_CN_VLP = 46,
+	PW_LMT_REGU_6G_THAILAND_LPI = 47,
+	PW_LMT_REGU_6G_THAILAND_STD = 48,
+	PW_LMT_REGU_6G_THAILAND_VLP = 49,
+	PW_LMT_REGU_6G_ETSI_LPI_DA = 50,
+	PW_LMT_REGU_6G_ETSI_STD_DA = 51,
+	PW_LMT_REGU_6G_ETSI_VLP_DA = 52,
+
+	/* place predefined ones above */
+	PW_LMT_REGU_6G_PREDEF_NUM,
+	PW_LMT_MAX_6G_REGULATION_NUM = PW_LMT_REGU_6G_PREDEF_NUM + PW_LMT_MAX_6G_REGULATION_EXT_NUM
+};
+
+#define PW_LMT_MAX_PER_BAND_REGU_NUM ((u8)PW_LMT_MAX_REGULATION_NUM > (u8)PW_LMT_MAX_6G_REGULATION_NUM ? PW_LMT_MAX_REGULATION_NUM : PW_LMT_MAX_6G_REGULATION_NUM)
+
+enum halrf_tx_shape_modu_type {
+	TX_SHAPE_CCK,
+	TX_SHAPE_OFDM,
+	TX_SHAPE_MAX
+};
+
+enum halrf_pw_lmt_band_type {
+	PW_LMT_BAND_2_4G = 0,
+	PW_LMT_BAND_5G = 1,
+	PW_LMT_BAND_6G = 2,
+	PW_LMT_MAX_BAND = 3
+};
+
+enum halrf_pw_lmt_bandwidth_type {
+	PW_LMT_BW_20M = 0,
+	PW_LMT_BW_40M = 1,
+	PW_LMT_BW_80M = 2,
+	PW_LMT_BW_160M = 3,
+	PW_LMT_MAX_BANDWIDTH_NUM = 4
+};
+
+enum halrf_pw_lmt_ratesection_type {
+	PW_LMT_RS_CCK = 0,
+	PW_LMT_RS_OFDM = 1,
+	PW_LMT_RS_HT = 2,
+	PW_LMT_RS_VHT = 3,
+	PW_LMT_RS_HE = 4,
+	PW_LMT_MAX_RS_NUM = 5
+};
+
+enum halrf_pw_lmt_rfpath_type {
+	PW_LMT_PH_1T = 0,
+	PW_LMT_PH_2T = 1,
+	PW_LMT_PH_3T = 2,
+	PW_LMT_PH_4T = 3,
+	PW_LMT_MAX_PH_NUM = 4
+};
+
+enum halrf_pw_lmt_beamforming_type {
+	PW_LMT_NONBF = 0,
+	PW_LMT_BF = 1,
+	PW_LMT_MAX_BF_NUM = 2
+};
+
+enum halrf_data_rate {
+	HALRF_DATA_RATE_CCK1 = 0,
+	HALRF_DATA_RATE_CCK2 = 0x1,
+	HALRF_DATA_RATE_CCK5_5,
+	HALRF_DATA_RATE_CCK11,
+	HALRF_DATA_RATE_OFDM6,
+	HALRF_DATA_RATE_OFDM9,
+	HALRF_DATA_RATE_OFDM12,
+	HALRF_DATA_RATE_OFDM18,
+	HALRF_DATA_RATE_OFDM24,
+	HALRF_DATA_RATE_OFDM36,
+	HALRF_DATA_RATE_OFDM48 = 10,
+	HALRF_DATA_RATE_OFDM54,
+	HALRF_DATA_RATE_MCS0,
+	HALRF_DATA_RATE_MCS1,
+	HALRF_DATA_RATE_MCS2,
+	HALRF_DATA_RATE_MCS3,
+	HALRF_DATA_RATE_MCS4,
+	HALRF_DATA_RATE_MCS5,
+	HALRF_DATA_RATE_MCS6,
+	HALRF_DATA_RATE_MCS7,
+	HALRF_DATA_RATE_MCS8 = 20,
+	HALRF_DATA_RATE_MCS9,
+	HALRF_DATA_RATE_MCS10,
+	HALRF_DATA_RATE_MCS11,
+	HALRF_DATA_RATE_MCS12,
+	HALRF_DATA_RATE_MCS13,
+	HALRF_DATA_RATE_MCS14,
+	HALRF_DATA_RATE_MCS15,
+	HALRF_DATA_RATE_MCS16,
+	HALRF_DATA_RATE_MCS17,
+	HALRF_DATA_RATE_MCS18 = 30,
+	HALRF_DATA_RATE_MCS19,
+	HALRF_DATA_RATE_MCS20,
+	HALRF_DATA_RATE_MCS21,
+	HALRF_DATA_RATE_MCS22,
+	HALRF_DATA_RATE_MCS23,
+	HALRF_DATA_RATE_MCS24,
+	HALRF_DATA_RATE_MCS25,
+	HALRF_DATA_RATE_MCS26,
+	HALRF_DATA_RATE_MCS27,
+	HALRF_DATA_RATE_MCS28 = 40,
+	HALRF_DATA_RATE_MCS29,
+	HALRF_DATA_RATE_MCS30,
+	HALRF_DATA_RATE_MCS31,
+	HALRF_DATA_RATE_VHT_NSS1_MCS0,
+	HALRF_DATA_RATE_VHT_NSS1_MCS1,
+	HALRF_DATA_RATE_VHT_NSS1_MCS2,
+	HALRF_DATA_RATE_VHT_NSS1_MCS3,
+	HALRF_DATA_RATE_VHT_NSS1_MCS4,
+	HALRF_DATA_RATE_VHT_NSS1_MCS5,
+	HALRF_DATA_RATE_VHT_NSS1_MCS6 = 50,
+	HALRF_DATA_RATE_VHT_NSS1_MCS7,
+	HALRF_DATA_RATE_VHT_NSS1_MCS8,
+	HALRF_DATA_RATE_VHT_NSS1_MCS9,
+	HALRF_DATA_RATE_VHT_NSS2_MCS0,
+	HALRF_DATA_RATE_VHT_NSS2_MCS1,
+	HALRF_DATA_RATE_VHT_NSS2_MCS2,
+	HALRF_DATA_RATE_VHT_NSS2_MCS3,
+	HALRF_DATA_RATE_VHT_NSS2_MCS4,
+	HALRF_DATA_RATE_VHT_NSS2_MCS5,
+	HALRF_DATA_RATE_VHT_NSS2_MCS6 = 60,
+	HALRF_DATA_RATE_VHT_NSS2_MCS7,
+	HALRF_DATA_RATE_VHT_NSS2_MCS8,
+	HALRF_DATA_RATE_VHT_NSS2_MCS9,
+	HALRF_DATA_RATE_VHT_NSS3_MCS0,
+	HALRF_DATA_RATE_VHT_NSS3_MCS1,
+	HALRF_DATA_RATE_VHT_NSS3_MCS2,
+	HALRF_DATA_RATE_VHT_NSS3_MCS3,
+	HALRF_DATA_RATE_VHT_NSS3_MCS4,
+	HALRF_DATA_RATE_VHT_NSS3_MCS5,
+	HALRF_DATA_RATE_VHT_NSS3_MCS6 = 70,
+	HALRF_DATA_RATE_VHT_NSS3_MCS7,
+	HALRF_DATA_RATE_VHT_NSS3_MCS8,
+	HALRF_DATA_RATE_VHT_NSS3_MCS9,
+	HALRF_DATA_RATE_VHT_NSS4_MCS0,
+	HALRF_DATA_RATE_VHT_NSS4_MCS1,
+	HALRF_DATA_RATE_VHT_NSS4_MCS2,
+	HALRF_DATA_RATE_VHT_NSS4_MCS3,
+	HALRF_DATA_RATE_VHT_NSS4_MCS4,
+	HALRF_DATA_RATE_VHT_NSS4_MCS5,
+	HALRF_DATA_RATE_VHT_NSS4_MCS6 = 80,
+	HALRF_DATA_RATE_VHT_NSS4_MCS7,
+	HALRF_DATA_RATE_VHT_NSS4_MCS8,
+	HALRF_DATA_RATE_VHT_NSS4_MCS9,
+	HALRF_DATA_RATE_HE_NSS1_MCS0,
+	HALRF_DATA_RATE_HE_NSS1_MCS1,
+	HALRF_DATA_RATE_HE_NSS1_MCS2,
+	HALRF_DATA_RATE_HE_NSS1_MCS3,
+	HALRF_DATA_RATE_HE_NSS1_MCS4,
+	HALRF_DATA_RATE_HE_NSS1_MCS5,
+	HALRF_DATA_RATE_HE_NSS1_MCS6 = 90,
+	HALRF_DATA_RATE_HE_NSS1_MCS7,
+	HALRF_DATA_RATE_HE_NSS1_MCS8,
+	HALRF_DATA_RATE_HE_NSS1_MCS9,
+	HALRF_DATA_RATE_HE_NSS1_MCS10,
+	HALRF_DATA_RATE_HE_NSS1_MCS11,
+	HALRF_DATA_RATE_HE_NSS2_MCS0,
+	HALRF_DATA_RATE_HE_NSS2_MCS1,
+	HALRF_DATA_RATE_HE_NSS2_MCS2,
+	HALRF_DATA_RATE_HE_NSS2_MCS3,
+	HALRF_DATA_RATE_HE_NSS2_MCS4 = 100,
+	HALRF_DATA_RATE_HE_NSS2_MCS5,
+	HALRF_DATA_RATE_HE_NSS2_MCS6,
+	HALRF_DATA_RATE_HE_NSS2_MCS7,
+	HALRF_DATA_RATE_HE_NSS2_MCS8,
+	HALRF_DATA_RATE_HE_NSS2_MCS9,
+	HALRF_DATA_RATE_HE_NSS2_MCS10,
+	HALRF_DATA_RATE_HE_NSS2_MCS11,
+	HALRF_DATA_RATE_HE_NSS3_MCS0,
+	HALRF_DATA_RATE_HE_NSS3_MCS1,
+	HALRF_DATA_RATE_HE_NSS3_MCS2 = 110,
+	HALRF_DATA_RATE_HE_NSS3_MCS3,
+	HALRF_DATA_RATE_HE_NSS3_MCS4,
+	HALRF_DATA_RATE_HE_NSS3_MCS5,
+	HALRF_DATA_RATE_HE_NSS3_MCS6,
+	HALRF_DATA_RATE_HE_NSS3_MCS7,
+	HALRF_DATA_RATE_HE_NSS3_MCS8,
+	HALRF_DATA_RATE_HE_NSS3_MCS9,
+	HALRF_DATA_RATE_HE_NSS3_MCS10,
+	HALRF_DATA_RATE_HE_NSS3_MCS11,
+	HALRF_DATA_RATE_HE_NSS4_MCS0 = 120,
+	HALRF_DATA_RATE_HE_NSS4_MCS1,
+	HALRF_DATA_RATE_HE_NSS4_MCS2,
+	HALRF_DATA_RATE_HE_NSS4_MCS3,
+	HALRF_DATA_RATE_HE_NSS4_MCS4,
+	HALRF_DATA_RATE_HE_NSS4_MCS5,
+	HALRF_DATA_RATE_HE_NSS4_MCS6,
+	HALRF_DATA_RATE_HE_NSS4_MCS7,
+	HALRF_DATA_RATE_HE_NSS4_MCS8,
+	HALRF_DATA_RATE_HE_NSS4_MCS9,
+	HALRF_DATA_RATE_HE_NSS4_MCS10 = 130,
+	HALRF_DATA_RATE_HE_NSS4_MCS11,
+	HALRF_DATA_RATE_HEDCM_NSS1_MCS0,
+	HALRF_DATA_RATE_HEDCM_NSS1_MCS1,
+	HALRF_DATA_RATE_HEDCM_NSS1_MCS3,
+	HALRF_DATA_RATE_HEDCM_NSS1_MCS4,
+	HALRF_DATA_RATE_HEDCM_NSS2_MCS0,
+	HALRF_DATA_RATE_HEDCM_NSS2_MCS1,
+	HALRF_DATA_RATE_HEDCM_NSS2_MCS3,
+	HALRF_DATA_RATE_HEDCM_NSS2_MCS4,
+	HALRF_DATA_RATE_HEDCM_OFFSET = 140,
+	HALRF_DATA_RATE_VHT_OFFSET,
+	HALRF_DATA_RATE_HT_OFFSET,
+	HALRF_DATA_RATE_OFDM_OFFSET,
+	HALRF_DATA_RATE_CCK_OFFSET,
+	HALRF_DATA_RATE_MAX
+};
+
+enum halrf_pw_lmt_6g_type {
+	PW_LMT_6G_LOW = 0,
+	PW_LMT_6G_STD = 1,
+	PW_LMT_6G_VLOW = 2,
+	PW_LMT_6G_MAX
+};
+
+enum halrf_pw_lmt_tbl_ru {
+	PW_LMT_TBL_NONE_RU = 0,
+	PW_LMT_TBL_RU = 1,
+	PW_LMT_TBL_RU_MAX
+};
+
+enum halrf_pw_lmt_tbl_band {
+	PW_LMT_TBL = 0,
+	PW_LMT_TBL_6G = 1,
+	PW_LMT_TBL_BAND_MAX
+};
+
+struct halrf_pwr_info {
+	/*Power by Rate and Power Limit Switch*/
+	u8 pwr_table_switch_efuse;
+	u8 pwr_by_rate_switch;
+	u8 pwr_limit_switch;
+
+//	bool regulation[PW_LMT_MAX_BAND][PW_LMT_MAX_PER_BAND_REGU_NUM];
+	bool regulation[PW_LMT_MAX_BAND][PW_LMT_MAX_PER_BAND_REGU_NUM];
+	u8 tx_shap_idx[PW_LMT_MAX_BAND][TX_SHAPE_MAX][PW_LMT_MAX_PER_BAND_REGU_NUM];
+	u8 tx_shap_idx_ru[PW_LMT_MAX_BAND][TX_SHAPE_MAX][PW_LMT_MAX_PER_BAND_REGU_NUM];
+	s8 tx_pwr_by_rate[PW_LMT_MAX_BAND][HALRF_DATA_RATE_MAX];
+
+	s8 tx_pwr_limit_2g[PW_LMT_MAX_REGULATION_NUM][PW_LMT_MAX_2G_BANDWITH_NUM]
+			[PW_LMT_MAX_RS_NUM][PW_LMT_MAX_BF_NUM][PW_LMT_MAX_CHANNEL_NUMBER_2G][MAX_HALRF_PATH];
+
+	s8 tx_pwr_limit_5g[PW_LMT_MAX_REGULATION_NUM][PW_LMT_MAX_BANDWIDTH_NUM]
+			[PW_LMT_MAX_RS_NUM][PW_LMT_MAX_BF_NUM][PW_LMT_MAX_CHANNEL_NUMBER_5G][MAX_HALRF_PATH];
+
+	s8 tx_pwr_limit_6g[PW_LMT_MAX_6G_REGULATION_NUM][PW_LMT_MAX_BANDWIDTH_NUM]
+			[PW_LMT_MAX_RS_NUM][PW_LMT_MAX_BF_NUM][PW_LMT_MAX_CHANNEL_NUMBER_6G][MAX_HALRF_PATH];
+
+	s8 tx_pwr_limit_ru_2g[PW_LMT_MAX_REGULATION_NUM][PW_LMT_RU_BW_NULL]
+			[PW_LMT_MAX_RS_NUM][PW_LMT_MAX_CHANNEL_NUMBER_2G][MAX_HALRF_PATH];
+
+	s8 tx_pwr_limit_ru_5g[PW_LMT_MAX_REGULATION_NUM][PW_LMT_RU_BW_NULL]
+			[PW_LMT_MAX_RS_NUM][PW_LMT_MAX_CHANNEL_NUMBER_5G][MAX_HALRF_PATH];
+
+	s8 tx_pwr_limit_ru_6g[PW_LMT_MAX_6G_REGULATION_NUM][PW_LMT_RU_BW_NULL]
+			[PW_LMT_MAX_RS_NUM][PW_LMT_MAX_CHANNEL_NUMBER_6G][MAX_HALRF_PATH];
+
+	s8 tx_pwr_by_rate_mac[HW_PHY_MAX][TX_PWR_BY_RATE_NUM_MAC];
+
+	s8 tx_pwr_limit_mac[HW_PHY_MAX][TX_PWR_LIMIT_NUM_MAC];
+
+	s8 tx_pwr_limit_ru_mac[HW_PHY_MAX][TX_PWR_LIMIT_RU_NUM_MAC];
+	s16 tx_pwr_limit_ru26_mac[HW_PHY_MAX];
+	s16 tx_pwr_limit_ru52_mac[HW_PHY_MAX];
+	s16 tx_pwr_limit_ru106_mac[HW_PHY_MAX];
+	bool coex_pwr_ctl_enable;
+	bool dpk_pwr_ctl_enable;
+	s32 coex_pwr;
+	s32 dpk_pwr;
+	u8 mp_regulation;
+	u8 regulation_idx;
+	u8 regulation_str[10];
+	bool fix_power[MAX_HALRF_PATH];
+	s8 fix_power_dbm[MAX_HALRF_PATH];
+	bool set_tx_ptrn_shap_en;
+	u8 set_tx_ptrn_shap_idx[PW_LMT_MAX_BAND][TX_SHAPE_MAX];
+	u16 extra_regd_idx;
+	u16 extra_regd_idx_6g;
+	u8 power_constraint[HW_PHY_MAX];
+	s8 dpk_mcc_power;
+	s8 tx_rate_power_control[HW_PHY_MAX];
+	s8 max_tx_rate_power[HW_PHY_MAX];
+	bool max_tx_rate_power_en;
+	s8 pwr_by_rate_bw_oft[PW_LMT_MAX_BAND];
+	bool pwr_by_rate_bw_oft_en;
+	/*Force Regulation*/
+	bool regulation_force_en;
+	u8 reg_2g;
+	u8 reg_5g;
+	u8 reg_6g;
+	u8 reg_array_2g[PW_LMT_MAX_REGULATION_NUM];
+	u8 reg_array_5g[PW_LMT_MAX_REGULATION_NUM];
+	u8 reg_array_6g[PW_LMT_MAX_6G_REGULATION_NUM];
+	u8 reg_2g_len;
+	u8 reg_5g_len;
+	u8 reg_6g_len;
+	s8 ext_pwr[MAX_HALRF_PATH];
+	s8 ext_pwr_diff[MAX_HALRF_PATH];
+	s8 ext_pwr_org[MAX_HALRF_PATH];
+	u8 power_limit_6g_type;
+	s8 ext_pwr_diff_2g[MAX_HALRF_PATH];	/*PathA, PathB compare power and take the smaller difference*/
+	s8 ext_pwr_diff_5g[MAX_HALRF_PATH][RTK_DAG_5G_SUB_BAND_CNT];
+	s8 ext_pwr_diff_6g[MAX_HALRF_PATH][RTK_DAG_6G_SUB_BAND_CNT];
+	bool ant_gain_en;
+	u8 ant_gain_reload_table_reg;
+	u8 ant_gain_reg_2g[PW_LMT_MAX_REGULATION_NUM];
+	u8 ant_gain_reg_5g[PW_LMT_MAX_REGULATION_NUM];
+	u8 ant_gain_reg_6g[PW_LMT_MAX_6G_REGULATION_NUM];
+	s8 ant_gain_2g_oft[PW_LMT_MAX_REGULATION_NUM][MAX_HALRF_PATH];	/*Antenna gain compensation. EX: Ant gain 5dBi in lab, but customer use 2dBi ant*/
+	s8 ant_gain_5g_oft[PW_LMT_MAX_REGULATION_NUM][MAX_HALRF_PATH][RTK_DAG_5G_SUB_BAND_CNT];
+	s8 ant_gain_6g_oft[PW_LMT_MAX_6G_REGULATION_NUM][MAX_HALRF_PATH][RTK_DAG_6G_SUB_BAND_CNT];
+	s8 toal_pwr_diff_2g[PW_LMT_MAX_REGULATION_NUM][MAX_HALRF_PATH];	/*PathA, PathB compare power and take the smaller difference + Antenna gain compensation. Offset to power limit*/
+	s8 toal_pwr_diff_5g[PW_LMT_MAX_REGULATION_NUM][MAX_HALRF_PATH][RTK_DAG_5G_SUB_BAND_CNT];
+	s8 toal_pwr_diff_6g[PW_LMT_MAX_6G_REGULATION_NUM][MAX_HALRF_PATH][RTK_DAG_6G_SUB_BAND_CNT];
+	u8 ant_type;
+	s32 tpe_max_tx_pwr[HW_PHY_MAX][MAX_TPE_ELE_CNT][MAX_TPE_TX_PWR_CNT];
+	bool pwr_by_rate_form_folder;
+	bool pwr_lmt_form_folder;
+	bool pwr_lmt_6g_form_folder;
+	bool pwr_lmt_ru_form_folder;
+	bool pwr_lmt_ru_6g_form_folder;
+	bool pwr_trk_tbl_form_folder;
+	bool regulation_test_en;	/*for debug test, set regulation enable*/
+	u8 regulation_test_idx;		/*for debug test, set regulation: FCC, CE, iC....*/
+};
+
+#define TX_NUM 2		/*1TX, 2TX*/
+#define BW20M_2G_5G_CH_NUM 42	/*2G CCK + 5G OFDM ch list*/
+
+struct halrf_fw_scan_pwr_info {
+	u8 fw_scan_pwr_enable;
+	u32 cck_11m_1m;
+	u32 ofdm_2g_18m_6m;
+	u32 ofdm_5g_18m_6m;
+	s8 pwr_lmt[TX_NUM][BW20M_2G_5G_CH_NUM];
+};
+
+extern const char * const _pw_lmt_regu_type_str[PW_LMT_MAX_REGULATION_NUM];
+#define pw_lmt_regu_type_str(lmt) ((lmt) < PW_LMT_MAX_REGULATION_NUM ? _pw_lmt_regu_type_str[(lmt)] : NULL)
+
+extern const char * const _pw_lmt_regu_type_str_6g[PW_LMT_MAX_6G_REGULATION_NUM];
+#define pw_lmt_regu_type_str_6g(lmt) ((lmt) < PW_LMT_MAX_6G_REGULATION_NUM ? _pw_lmt_regu_type_str_6g[(lmt)] : NULL)
+
+const char *pw_lmt_regu_type_of_band_str(u8 band, u8 lmt);
+
+void halrf_power_by_rate_store_to_array(struct rf_info *rf,
+			u32 band, u32 tx_num, u32 rate_id, u32 data);
+void halrf_power_limit_store_to_array(struct rf_info *rf,
+			u8 regulation, u8 band, u8 bandwidth, u8 rate,
+			u8 tx_num, u8 beamforming, u8 chnl, s8 val);
+void halrf_power_limit_ntx_cpy(struct rf_info *rf, u8 tx_num_dst, u8 tx_num_src);
+void halrf_power_limit_set_worldwide(struct rf_info *rf);
+void halrf_power_limit_ru_store_to_array(struct rf_info *rf,
+			u8 band, u8 bandwidth, u8 tx_num, u8 rate,
+			u8 regulation, u8 chnl, s8 val);
+void halrf_power_limit_ru_ntx_cpy(struct rf_info *rf, u8 tx_num_dst, u8 tx_num_src);
+void halrf_power_limit_ru_set_worldwide(struct rf_info *rf);
+
+#ifndef RF_8730A_SUPPORT
+const char *halrf_get_pw_lmt_regu_type_str_extra(struct rf_info *rf, u8 band);
+void halrf_get_power_limit_extra(struct rf_info *rf);
+#endif
+
+void halrf_modify_pwr_table_bitmask(struct rf_info *rf,
+	enum phl_phy_idx phy, enum phl_pwr_table pwr_table);
+
+s8 halrf_get_pwr_control(struct rf_info *rf, enum phl_phy_idx phy);
+
+s8 halrf_get_tx_rate_pwr_control(struct rf_info *rf, enum phl_phy_idx phy);
+
+bool halrf_pwr_is_minus(struct rf_info *rf, u32 reg_tmp);
+
+s32 halrf_show_pwr_table(struct rf_info *rf, u32 reg_tmp);
+
+void halrf_set_scan_power_table_to_fw_no_6g(struct rf_info *rf);
+
+void halrf_get_path_power_diff(struct rf_info *rf, enum phl_phy_idx phy);
+
+void halrf_get_ant_gain_ofst_and_calc_total_ofst(struct rf_info *rf,
+	enum phl_phy_idx phy, struct rtw_phl_regu_dyn_ant_gain *regu);
+
+#endif

3rd/devourer/hal/halrf/g6/vendor/halrf_pwr_track.h

@@ -0,0 +1,266 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2019 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef _HALRF_PWR_TRACK_H_
+#define _HALRF_PWR_TRACK_H_
+
+/*@--------------------------Define Parameters-------------------------------*/
+#define AVG_THERMAL_NUM 8
+#define MAX_RF_PATH 4
+#define DELTA_SWINGIDX_SIZE 30
+#define BAND_NUM 4
+#define BAND_NUM_6G 4
+#define DELTA_SWINTSSI_SIZE 61
+#define TSSI_EFUSE_NUM 32
+#define TSSI_BW_DIFF_EFUSE_NUM 14
+#define TSSI_HIDE_EFUSE_NUM 8
+#define TSSI_HIDE_EFUSE_NUM_6G 8
+#define AVG_THERMAL_NUM_TSSI 2
+#define MAX_CH_NUM 67
+#define TSSI_ALIMK_VAULE_NUM 8
+
+#define MAX_HALRF_PATH 2
+
+#define TSSI_EXTRA_GROUP_BIT (BIT(31))
+#define TSSI_EXTRA_GROUP(idx) (TSSI_EXTRA_GROUP_BIT | (idx))
+#define IS_TSSI_EXTRA_GROUP(group) ((group) & TSSI_EXTRA_GROUP_BIT)
+#define TSSI_EXTRA_GET_GROUP_IDX1(group) ((group) & ~TSSI_EXTRA_GROUP_BIT)
+#define TSSI_EXTRA_GET_GROUP_IDX2(group) (TSSI_EXTRA_GET_GROUP_IDX1(group) + 1)
+
+/*@---------------------------End Define Parameters---------------------------*/
+
+
+u8 halrf_get_limit_ch_idx_to_ch_idx(struct rf_info *rf, u8 band, u8 channel);
+
+enum halrf_tssi_rate_type {
+	EFUSE_TSSI_CCK = 0,
+	EFUSE_TSSI_MCS,
+	EFUSE_TSSI_6G,
+	EFUSE_TSSI_RATE_MAX
+};
+
+enum halrf_tssi_type{
+	TSSI_OFF = 0,
+	TSSI_ON,
+	TSSI_CAL
+};
+
+enum halrf_tssi_slope_type{
+	TSSI_SLOPE_DEFAULT = 0,
+	TSSI_SLOPE_ON,
+	TSSI_SLOPE_OFF
+};
+
+enum halrf_tssi_alimk_band{
+	TSSI_ALIMK_2G = 0,
+	TSSI_ALIMK_5GL,
+	TSSI_ALIMK_5GM,
+	TSSI_ALIMK_5GH,
+	TSSI_ALIMK_MAX
+};
+
+enum halrf_tssi_dz {
+	DZ_TSSI_ALIMTK_TIMEOUT	= BIT(0),
+};
+
+struct halrf_pwr_track_info {
+	/* u8 is_txpowertracking; */
+	u8	tx_powercount;
+	bool    is_txpowertracking_init;
+	bool    is_txpowertracking;
+	u8  	txpowertrack_control; /* for mp mode, turn off txpwrtracking as default */
+	u8	tm_trigger;
+	u8  	internal_pa_5g[2];	/* pathA / pathB */
+
+	u8  	thermal_meter[2];    /* thermal_meter, index 0 for RFIC0, and 1 for RFIC1 */
+	u8	thermal_value;
+	u8	thermal_value_path[MAX_RF_PATH];
+	u8	thermal_value_lck;
+	u8	thermal_value_iqk;
+	s8  	thermal_value_delta; /* delta of thermal_value and efuse thermal */
+	u8	thermal_value_avg[AVG_THERMAL_NUM];
+	u8	thermal_value_avg_path[MAX_RF_PATH][AVG_THERMAL_NUM];
+	u8	thermal_value_avg_index;
+	u8	thermal_value_avg_index_path[MAX_RF_PATH];
+	s8	power_index_offset_path[MAX_RF_PATH];
+
+	u8	thermal_value_rx_gain;
+	u8	thermal_value_crystal;
+	u8	thermal_value_dpk_store;
+	u8	thermal_value_dpk_track;
+	bool	txpowertracking_in_progress;
+
+	bool	is_reloadtxpowerindex;
+	u8	is_rf_pi_enable;
+	u32 	txpowertracking_callback_cnt; /* cosa add for debug */
+
+	u8	is_cck_in_ch14;
+	u8	CCK_index;
+	u8	OFDM_index[MAX_RF_PATH];
+	s8	power_index_offset;
+	s8	delta_power_index;
+	s8	delta_power_index_path[MAX_RF_PATH];
+	s8	delta_power_index_last;
+	s8	delta_power_index_last_path[MAX_RF_PATH];
+	bool is_tx_power_changed;
+
+	/*struct iqk_matrix_regs_setting iqk_matrix_reg_setting[IQK_MATRIX_SETTINGS_NUM];*/
+	u8	delta_lck;
+	s8  delta_swing_table_idx_2g_cck_a_p[DELTA_SWINGIDX_SIZE];
+	s8  delta_swing_table_idx_2g_cck_a_n[DELTA_SWINGIDX_SIZE];
+	s8  delta_swing_table_idx_2g_cck_b_p[DELTA_SWINGIDX_SIZE];
+	s8  delta_swing_table_idx_2g_cck_b_n[DELTA_SWINGIDX_SIZE];
+	s8  delta_swing_table_idx_2g_cck_c_p[DELTA_SWINGIDX_SIZE];
+	s8  delta_swing_table_idx_2g_cck_c_n[DELTA_SWINGIDX_SIZE];
+	s8  delta_swing_table_idx_2g_cck_d_p[DELTA_SWINGIDX_SIZE];
+	s8  delta_swing_table_idx_2g_cck_d_n[DELTA_SWINGIDX_SIZE];
+	s8  delta_swing_table_idx_2ga_p[DELTA_SWINGIDX_SIZE];
+	s8  delta_swing_table_idx_2ga_n[DELTA_SWINGIDX_SIZE];
+	s8  delta_swing_table_idx_2gb_p[DELTA_SWINGIDX_SIZE];
+	s8  delta_swing_table_idx_2gb_n[DELTA_SWINGIDX_SIZE];
+	s8  delta_swing_table_idx_2gc_p[DELTA_SWINGIDX_SIZE];
+	s8  delta_swing_table_idx_2gc_n[DELTA_SWINGIDX_SIZE];
+	s8  delta_swing_table_idx_2gd_p[DELTA_SWINGIDX_SIZE];
+	s8  delta_swing_table_idx_2gd_n[DELTA_SWINGIDX_SIZE];
+	s8  delta_swing_table_idx_5ga_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
+	s8  delta_swing_table_idx_5ga_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
+	s8  delta_swing_table_idx_5gb_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
+	s8  delta_swing_table_idx_5gb_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
+	s8  delta_swing_table_idx_5gc_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
+	s8  delta_swing_table_idx_5gc_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
+	s8  delta_swing_table_idx_5gd_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
+	s8  delta_swing_table_idx_5gd_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
+	s8 delta_swing_table_idx_6ga_p[BAND_NUM_6G][DELTA_SWINGIDX_SIZE];
+	s8 delta_swing_table_idx_6ga_n[BAND_NUM_6G][DELTA_SWINGIDX_SIZE];
+	s8 delta_swing_table_idx_6gb_p[BAND_NUM_6G][DELTA_SWINGIDX_SIZE];
+	s8 delta_swing_table_idx_6gb_n[BAND_NUM_6G][DELTA_SWINGIDX_SIZE];
+	s8 delta_swing_table_idx_6gc_p[BAND_NUM_6G][DELTA_SWINGIDX_SIZE];
+	s8 delta_swing_table_idx_6gc_n[BAND_NUM_6G][DELTA_SWINGIDX_SIZE];
+	s8 delta_swing_table_idx_6gd_p[BAND_NUM_6G][DELTA_SWINGIDX_SIZE];
+	s8 delta_swing_table_idx_6gd_n[BAND_NUM_6G][DELTA_SWINGIDX_SIZE];
+	s8  delta_swing_tssi_table_2g_cck_a[DELTA_SWINTSSI_SIZE];
+	s8  delta_swing_tssi_table_2g_cck_b[DELTA_SWINTSSI_SIZE];
+	s8  delta_swing_tssi_table_2g_cck_c[DELTA_SWINTSSI_SIZE];
+	s8  delta_swing_tssi_table_2g_cck_d[DELTA_SWINTSSI_SIZE];
+	s8  delta_swing_tssi_table_2ga[DELTA_SWINTSSI_SIZE];
+	s8  delta_swing_tssi_table_2gb[DELTA_SWINTSSI_SIZE];
+	s8  delta_swing_tssi_table_2gc[DELTA_SWINTSSI_SIZE];
+	s8  delta_swing_tssi_table_2gd[DELTA_SWINTSSI_SIZE];
+	s8  delta_swing_tssi_table_5ga[BAND_NUM][DELTA_SWINTSSI_SIZE];
+	s8  delta_swing_tssi_table_5gb[BAND_NUM][DELTA_SWINTSSI_SIZE];
+	s8  delta_swing_tssi_table_5gc[BAND_NUM][DELTA_SWINTSSI_SIZE];
+	s8  delta_swing_tssi_table_5gd[BAND_NUM][DELTA_SWINTSSI_SIZE];
+	s8  delta_swing_table_xtal_p[DELTA_SWINGIDX_SIZE];
+	s8  delta_swing_table_xtal_n[DELTA_SWINGIDX_SIZE];
+	s8  delta_swing_table_idx_2ga_p_8188e[DELTA_SWINGIDX_SIZE];
+	s8  delta_swing_table_idx_2ga_n_8188e[DELTA_SWINGIDX_SIZE];
+
+	u8			bb_swing_idx_ofdm[MAX_RF_PATH];
+	u8			bb_swing_idx_ofdm_current;
+	u8			bb_swing_idx_ofdm_base;
+	u8			bb_swing_idx_ofdm_base_path[MAX_RF_PATH];
+	bool			bb_swing_flag_ofdm;
+	u8			bb_swing_idx_cck;
+	u8			bb_swing_idx_cck_current;
+	u8			bb_swing_idx_cck_base;
+	u8			default_ofdm_index;
+	u8			default_cck_index;
+	bool			bb_swing_flag_cck;
+
+	s8			absolute_ofdm_swing_idx[MAX_RF_PATH];
+	s8			remnant_ofdm_swing_idx[MAX_RF_PATH];
+	s8			absolute_cck_swing_idx[MAX_RF_PATH];
+	s8			remnant_cck_swing_idx;
+	s8			modify_tx_agc_value;       /*Remnat compensate value at tx_agc */
+	bool			modify_tx_agc_flag_path_a;
+	bool			modify_tx_agc_flag_path_b;
+	bool			modify_tx_agc_flag_path_c;
+	bool			modify_tx_agc_flag_path_d;
+	bool			modify_tx_agc_flag_path_a_cck;
+	bool			modify_tx_agc_flag_path_b_cck;
+
+	s8			kfree_offset[MAX_RF_PATH];
+	/*Add by Yuchen for Kfree Phydm*/
+	u8			reg_rf_kfree_enable;	/*for registry*/
+	u8			rf_kfree_enable;		/*for efuse enable check*/
+};
+
+struct halrf_tssi_info{
+	u8 thermal[MAX_HALRF_PATH];
+	u8 do_tssi_thermal[MAX_HALRF_PATH];
+	s32 tssi_de[MAX_HALRF_PATH];
+	u8 tssi_type[MAX_HALRF_PATH];
+	s8 tssi_efuse[MAX_HALRF_PATH][EFUSE_TSSI_RATE_MAX][TSSI_EFUSE_NUM];
+	s8 tssi_bw_diff_efuse[MAX_HALRF_PATH][EFUSE_TSSI_RATE_MAX][CHANNEL_WIDTH_MAX][TSSI_BW_DIFF_EFUSE_NUM];
+	s8 tssi_efuse_slope_gain_diff[MAX_HALRF_PATH][EFUSE_TSSI_RATE_MAX][TSSI_EFUSE_NUM];
+	s8 tssi_efuse_slope_cw_diff[MAX_HALRF_PATH][EFUSE_TSSI_RATE_MAX][TSSI_EFUSE_NUM];
+	bool tssi_slope_no_pg;
+	s8 tssi_trim[MAX_HALRF_PATH][TSSI_HIDE_EFUSE_NUM];
+	s8 tssi_trim_6g[MAX_HALRF_PATH][TSSI_HIDE_EFUSE_NUM_6G];
+	s32 tssi_xdbm;
+	s8 curr_tssi_cck_de[MAX_HALRF_PATH];
+	s8 curr_tssi_efuse_cck_de[MAX_HALRF_PATH];
+	s8 curr_tssi_ofdm_de[MAX_HALRF_PATH];
+	s8 curr_tssi_ofdm_de_20m[MAX_HALRF_PATH];
+	s8 curr_tssi_ofdm_de_80m[MAX_HALRF_PATH];
+	s8 curr_tssi_ofdm_de_160m[MAX_HALRF_PATH];
+	s8 curr_tssi_efuse_ofdm_de[MAX_HALRF_PATH];
+	s8 curr_tssi_ofdm_de_diff_20m[MAX_HALRF_PATH];
+	s8 curr_tssi_ofdm_de_diff_80m[MAX_HALRF_PATH];
+	s8 curr_tssi_ofdm_de_diff_160m[MAX_HALRF_PATH];
+	s8 curr_tssi_trim_de[MAX_HALRF_PATH];
+	s8 tssi_de_160m_adc_wa_20m;
+	s8 tssi_de_160m_adc_wa_40m;
+	s8 tssi_de_160m_adc_wa_80m;
+	s8 tssi_de_160m_adc_wa_160m;
+	bool do_tssi;
+	bool base_thermal_check[MAX_HALRF_PATH];
+	u32 base_thermal[MAX_HALRF_PATH];
+	u32 tssi_stop_power[MAX_HALRF_PATH];
+	bool tssi_tracking_check[MAX_HALRF_PATH];
+	u8 ther_avg[MAX_HALRF_PATH][AVG_THERMAL_NUM_TSSI]; /*path*/
+	u8 ther_avg_idx[MAX_HALRF_PATH];
+	u8 ther_avg_fifo_idx[MAX_HALRF_PATH];
+	u32 ther_avg_final[MAX_HALRF_PATH];
+	s8 extra_ofst[MAX_HALRF_PATH];
+	/*bool normal_tssi_tracking;*/
+	u8 normal_tssi_tracking_times;
+	u8 default_txagc_offset_check;
+	u8 default_txagc_offset_times;
+	u32 default_txagc_offset[MAX_HALRF_PATH];
+	s16 ref_pow_ofdm; /*-> HW: s(9,2)*/
+	s16 ref_pow_ofdm_offset;
+	u32 high_pwr_rst_cnt;
+	u8 cur_ch;
+	u8 cur_bw;
+	u32 backup_txagc_offset[MAX_HALRF_PATH][MAX_CH_NUM];
+	u8 backup_txagc_oft_ther[MAX_HALRF_PATH][MAX_CH_NUM];
+	bool check_backup_txagc[MAX_CH_NUM];
+	bool check_backup_aligmk[MAX_HALRF_PATH][MAX_CH_NUM];
+	u32 start_time, finish_time;
+	u32 alignment_value[MAX_HALRF_PATH][TSSI_ALIMK_MAX][TSSI_ALIMK_VAULE_NUM];
+	u32 alignment_backup_by_ch[MAX_HALRF_PATH][MAX_CH_NUM][TSSI_ALIMK_VAULE_NUM];
+	bool alignment_done[MAX_HALRF_PATH][TSSI_ALIMK_MAX];
+	u32 tssi_total_time;
+	u32 tssi_alimk_time;
+	u32 tssi_slope_time;
+	s32 slopek_cw_diff[MAX_HALRF_PATH];
+};
+
+struct halrf_xtal_info{
+	s8  delta_swing_xtal_table_idx_p[DELTA_SWINGIDX_SIZE];
+	s8  delta_swing_xtal_table_idx_n[DELTA_SWINGIDX_SIZE];
+};
+
+#endif

3rd/devourer/hal/halrf/g6/vendor/halrf_struct.h

@@ -0,0 +1,25 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2019 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef _HALRF_STRUCT_H_
+#define _HALRF_STRUCT_H_
+
+
+struct hal_rf_t {
+	struct rtw_phl_com_t *phl_com;
+	struct rtw_hal_com_t *hal_com;
+
+};
+
+#endif /*_HALRF_STRUCT_H_*/

3rd/devourer/hal/halrf/g6/vendor/halrf_tas.h

@@ -0,0 +1,156 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2019 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef _HALRF_TAS_H_
+#define _HALRF_TAS_H_
+
+#ifdef PHL_PLATFORM_WINDOWS
+#ifdef HALRF_TAS_SUPPORT
+
+#define TAS_VER 0x2
+
+#define HALRF_TAS_MV_AVG_WINDOW 180 /* watchdog period is 2s, target window is 360 sec, 360/2 = 180 */
+#define HALRF_TAS_MV_AVG_TX_RATIO_WINDOW 6 /* watchdog period is 2s, target window is 12 sec, 12/2 = 6 */
+#define HALRF_TAS_PAUSE_FCC_TIME 50 /* watchdog period is 2s, target window is 100 sec, 100/2 = 50, TAS pause 50 timees, reset TX AVG power */
+#define HALRF_TAS_PAUSE_IC_TIME HALRF_TAS_MV_AVG_WINDOW /* watchdog period is 2s, target window is 360 sec, 360/2 = 180, TAS pause 180 timees, reset TX AVG power */
+#define HALRF_TAS_WATCHDOG_TIME 2
+#define HALRF_TAS_DEF_PWR 80 /* 20 dBm, unit: 0.25 dBm (multiply by 4) */
+#define HALRF_TAS_DEF_RATIO 80 /* default tx ratio 80% */
+#define HALRF_TAS_DPR_ON_TH 24 /* 6 dBm, unit: 0.25 dBm (multiply by 4) */
+#define HALRF_TAS_DPR_OFF_TH 16 /* 4 dBm, unit: 0.25 dBm (multiply by 4) */
+#define HALRF_TAS_SAR_LMT_GAP 4 /* 1 dBm, unit: 0.25 dBm (multiply by 4) */
+#define HALRF_TAS_DPR_GAP 4 /* 1 dBm, unit: 0.25 dBm (multiply by 4) */
+#define HALRF_TAS_DELTA 8 /* 2 dBm, unit: 0.25 dBm (multiply by 4) */
+#define HALRF_TAS_UNDEF 0xFF
+#define HALRF_TAS_MAX_TH 0x7F
+ 
+enum halrf_tas_state {
+	HALRF_TAS_STATE_DPR_ON = 0,
+	HALRF_TAS_STATE_DPR_OFF = 1,
+	HALRF_TAS_STATE_STATIC_SAR = 2,
+};
+ 
+enum halrf_tas_p_idx {
+	HALRF_PATTERN_1 = 0,
+	HALRF_PATTERN_2 = 1,
+	HALRF_PATTERN_3 = 2,
+	HALRF_PATTERN_4 = 3,
+	HALRF_PATTERN_5 = 4,
+	HALRF_PATTERN_6 = 5,
+	HALRF_PATTERN_7 = 6,
+	HALRF_PATTERN_8 = 7,
+};
+
+enum halrf_tas_test_item {
+	HALRF_TAS_SET_PWR_BY_RATE_TO_DEFAULT = 0,
+	HALRF_TAS_SET_PWR_BY_RATE_N_DBM,
+	HALRF_TAS_SET_PWR_BY_RATE_HALF_SAR_LIMIT,
+	HALRF_TAS_SET_PWR_BY_RATE_SAR_LIMIT_ADD4,
+};
+
+struct halrf_tas_fw_info {
+    u32 tas_cur_idx;
+    s16 tas_txpwr_his[20];
+};
+ 
+struct halrf_tas_info {
+	u32 tas_mv_avg;
+	s16 txpwr_his[HALRF_TAS_MV_AVG_WINDOW];
+	s16 tx_ratio_his[HALRF_TAS_MV_AVG_TX_RATIO_WINDOW];
+	s16 last_txpwr;
+	double txpwr_r_his[HALRF_TAS_MV_AVG_WINDOW]; /* txpwr x ratio */
+	s16 cur_txpwr_avg;
+	u8 cur_tx_ratio_avg;
+	u8 cur_ratio;
+	u8 cur_state;
+	u8 last_state;
+	u8 cur_idx;
+	u8 cur_radio_idx;
+	u32 avg_pwr_start_idx;
+	u32 avg_pwr_end_idx;
+	s8 dpr_on_th;
+	s8 dpr_off_th;
+	u8 dpr_gap;
+	u8 tas_delta;
+	u8 tas_delta_show_cli;
+	s8 tas_off_delta_pwr;
+	u8 tas_delta_tmp;
+	s8 tas_off_delta_pwr_tmp;
+	u8 tas_en;
+	u8 tas_pause;
+	u32 tas_pause_time;
+	u8 tas_p_idx;
+	u8 tas_case_id;
+	struct rtw_phl_ext_pwr_lmt_info sar_lmt;
+	struct halrf_tas_fw_info tas_fw_info;
+	enum halrf_tas_test_item tas_test_item;
+	bool tx_ratio_limit_en;
+	bool tas_ext_pwr_lmt_en_tmp;
+	bool tas_ext_pwr_lmt_en_check;
+	u32 tas_pwr_over_sar_lmt;
+	bool tas_pwr_over_sar_lmt_check;
+	bool tas_pwr_by_rate_ctrl;
+	s32 tas_pwr_by_rate_ctrl_value;		/* unit: 0.25 dBm (multiply by 4) */
+	u8 last_channel;
+	u8 last_band;
+};
+
+void halrf_tas_get_th(struct rf_info *rf, s16 *dpr_on_th, s16 *dpr_off_th, s16 *sar_org_lmt);
+
+void halrf_tas_watchdog(struct rf_info *rf);
+
+void halrf_tas_powersaving_watchdog(struct rf_info *rf);
+
+void halrf_tas_enable(struct rf_info *rf, char input[][16], u32 *_used,
+				char *output, u32 *_out_len);
+void halrf_tas_case_id(struct rf_info *rf, char input[][16], u32 *_used,
+				char *output, u32 *_out_len);
+void halrf_tas_info_dump(struct rf_info *rf, char input[][16], u32 *_used,
+				char *output, u32 *_out_len);
+void halrf_tas_tx_ratio_lmt_en(struct rf_info *rf, char input[][16], u32 *_used,
+				char *output, u32 *_out_len);
+
+void halrf_tas_config(struct rf_info *rf, char input[][16], u32 *_used,
+				char *output, u32 *_out_len);
+
+void halrf_tas_set_power_by_rate_n_dbm(struct rf_info *rf, char input[][16], u32 *_used,
+					char *output, u32 *_out_len);
+
+void halrf_tas_set_power_by_rate_half_sar_limit(struct rf_info *rf, char input[][16], u32 *_used,
+						char *output, u32 *_out_len);
+
+void halrf_tas_set_power_by_rate_sar_limit_add_4db(struct rf_info *rf, char input[][16], u32 *_used,
+						char *output, u32 *_out_len);
+
+void halrf_tas_set_power_by_rate_to_default(struct rf_info *rf, char input[][16], u32 *_used,
+						char *output, u32 *_out_len);
+
+#define halrf_is_tas_en(rf) (rf->tas_info.tas_en & BIT0)
+#define halrf_get_tas_delta(rf) (rf->tas_info.tas_delta)
+
+
+#endif /*HALRF_TAS_SUPPORT*/
+#endif	/*PHL_PLATFORM_WINDOWS*/
+
+void halrf_tas_set_oft_to_zero_scan_start(struct rf_info *rf);
+
+void halrf_tas_set_oft_scan_end(struct rf_info *rf);
+
+void halrf_tas_update_dpr_th(struct rf_info *rf);
+
+s8 halrf_tas_get_test_item_power(struct rf_info *rf);
+
+void halrf_tas_pause(struct rf_info *rf, bool is_stop);
+
+#endif	/*_HALRF_TAS_H_*/

3rd/devourer/hal/halrf/g6/vendor/halrf_txgapk.h

@@ -0,0 +1,58 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2019 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef _HALRF_TXGAPK_H_
+#define _HALRF_TXGAPK_H_
+#include "halrf_headers.h"
+
+#define NUM		4
+
+enum txgapk_id {
+	TXGAPK_TRACK	= 0x00,
+	TXGAPK_PWR		= 0x01,
+	TXGAPK_IQKBK    = 0x02,
+	TXGAPK_TRK_W,
+    TXGAPK_PWR_W,
+    TANK_CAL,
+    TANK_W,
+};
+
+
+struct halrf_gapk_info {
+
+	bool is_gapk_init;
+	bool is_gapk_enable;
+//	u8 band[NUM];
+	u8 ch[NUM];
+//	u8 bw[NUM];	
+	s32 track_d[2][17];
+	s32 track_ta[2][17];
+	s32 power_d[2][17];
+	s32 power_ta[2][17];
+	u32 txgapk_time;
+
+	bool	is_txgapk_ok;
+//	u32		failcode;
+	u32     r0x8010[2]; /* before and after txgapk */
+	u32     txgapk_chk_cnt[2][3][2]; /* path */ /* track pwr iqkbk*/ /* 0xbff8 0x80fc*/
+
+	/* u8 txgapk_mcc_ch[2][NUM]; */
+	/* u8 txgapk_table_idx[NUM]; */
+	u8 txgapk_mcc_ch[2]; /* channel */
+	u8 txgapk_table_idx;
+
+	bool d_bnd_ok;
+};
+
+#endif

3rd/devourer/hal/halrf/g6/vendor/halrf_wpp.h

@@ -0,0 +1,53 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+#ifndef __HALRF_WPP_H__
+#define __HALRF_WPP_H__
+
+#define HALRF_WPP_CONTROL_GUIDS \
+	WPP_DEFINE_CONTROL_GUID( \
+		HalrfGuid, (C01A40AB,B69E,4CF6,BB09,4E0672EA2FC6), \
+		WPP_DEFINE_BIT(DBG_RF_TX_PWR_TRACK) \
+		WPP_DEFINE_BIT(DBG_RF_IQK) \
+		WPP_DEFINE_BIT(DBG_RF_LCK) \
+		WPP_DEFINE_BIT(DBG_RF_DPK) \
+		WPP_DEFINE_BIT(DBG_RF_TXGAPK) \
+		WPP_DEFINE_BIT(DBG_RF_DACK) \
+		WPP_DEFINE_BIT(DBG_RF_DPK_TRACK) \
+		WPP_DEFINE_BIT(DBG_RF_RXDCK) \
+		WPP_DEFINE_BIT(DBG_RF_RFK) \
+		WPP_DEFINE_BIT(DBG_RF_INIT) \
+		WPP_DEFINE_BIT(DBG_RF_POWER) \
+		WPP_DEFINE_BIT(DBG_RF_RXGAINK) \
+		WPP_DEFINE_BIT(DBG_RF_THER_TRIM) \
+		WPP_DEFINE_BIT(DBG_RF_PABIAS_TRIM) \
+		WPP_DEFINE_BIT(DBG_RF_TSSI_TRIM) \
+		WPP_DEFINE_BIT(DBG_RF_FW) \
+		WPP_DEFINE_BIT(DBG_RF_MP) \
+		WPP_DEFINE_BIT(DBG_RF_TMP) \
+		WPP_DEFINE_BIT(DBG_RF_PSD) \
+		WPP_DEFINE_BIT(DBG_RF_TAS) \
+		)
+
+#endif /* __HALRF_WPP_H__ */