misakiotoha/OpenIPC_RTL8812AU_Forword_cpp
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

first

Browse Source
This commit is contained in:
Misaki
2026-09-13 13:30:21 +08:00
commit a6bbd520cf
2744 changed files with 1598795 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files
3rd/devourer/hal/halbb/g6/kestrel_halbb_glue.c
+204
View File
@@ -0,0 +1,204 @@
/* C glue: owns a bb_info and drives the vendored halbb-G6 BB functions for
* both Kestrel chips. Compiled as C behind the shim (hal/halbb/
* hal_headers_le.h). See the header. */
#include "halbb_precomp.h" /* full bb_info + halbb types + BB functions */
#include "kestrel_halbb_glue.h"
struct kestrel_halbb_ctx {
struct bb_info bb;
struct rtw_hal_com_t hal;
struct rtw_phl_com_t phl;
struct bb_cmn_info cmn;
int env_mntr_ready; /* lazy halbb_env_mntr init done */
};
struct kestrel_halbb_ctx *kestrel_halbb_create(struct kestrel_halbb_bridge *br,
enum kestrel_chip chip,
unsigned char cut,
unsigned char rfe_type) {
struct kestrel_halbb_ctx *c =
(struct kestrel_halbb_ctx *)malloc(sizeof(struct kestrel_halbb_ctx));
if (!c)
return 0;
_os_mem_set(0, c, 0, sizeof(*c));
c->hal.drv_priv = br; /* -> kestrel_halbb_bridge (register plane) */
c->hal.cv = cut;
c->phl.dev_cap.rfe_type = rfe_type;
c->bb.hal_com = &c->hal;
c->bb.phl_com = &c->phl;
c->bb.bb_cmn_hooker = &c->cmn;
c->bb.bb_phy_idx = HW_PHY_0;
if (chip == KESTREL_CHIP_8852B) {
c->bb.ic_type = BB_RTL8852B;
c->bb.ic_sub_type = BB_IC_SUB_TYPE_8852B_8852B;
c->hal.chip_id = CHIP_WIFI6_8852B;
} else {
c->bb.ic_type = BB_RTL8852C;
c->bb.ic_sub_type = BB_IC_SUB_TYPE_8852C_8852C;
c->hal.chip_id = CHIP_WIFI6_8852C;
}
c->bb.rx_path = RF_PATH_AB;
/* Both supported dies are 2SS / 2 RF paths. The vendor derives these in
* halbb_cmn_info_self_init from ic_type; the minimal bring-up must set them
* itself — halbb_physts_parsing_init shifts a
* halbb_gen_mask_from_0(num_rf_path) into the physts IE04..07 bits, so a
* zero here silently disables the per-path IE pages (per-antenna SNR/EVM). */
c->bb.num_rf_path = 2;
c->bb.num_tx_path = 2;
c->bb.num_ss = 2;
c->bb.cr_type = BB_CLIENT; /* USB client CR bank; without it the env-monitor
* CR-init switch falls through and the NHM
* ready-bit address stays 0 (report never rdy) */
c->bb.bb0_cr_offset = 0; /* bridge adds the BB window (wIndex=1) */
/* halbb_init_cr_default guards on this flag; it asserts exactly the wiring
* done above (hal_com/phl_com/bb_cmn_hooker present). */
c->bb.bb_cmn_info_init_ready = true;
br->bb_info = &c->bb; /* halrf's cross-plane rtw_hal_bb_* calls (shim) */
return c;
}
/* Apply the built-in BB register table + load the gain table + the efuse RX
* gain offsets — the vendor's own loader flow (halbb_init_reg ->
* halbb_init_cr_default + halbb_init_gain_table + halbb_get_efuse_ofst_init),
* walking the vendored hwimg arrays with the vendor's check-positive engine.
* Returns nonzero on success. */
int kestrel_halbb_init_reg(struct kestrel_halbb_ctx *ctx) {
if (!ctx)
return 0;
return halbb_init_reg(&ctx->bb) ? 1 : 0;
}
void kestrel_halbb_rx_bringup(struct kestrel_halbb_ctx *ctx) {
if (!ctx)
return;
struct bb_info *bb = &ctx->bb;
/* The gain cache (bb_gain_i) is populated by kestrel_halbb_init_reg's
* halbb_init_gain_table; this entry owns the front-end routing + chains. */
/* LNAON / TRSW / PAPE RF-front-end routing (the both-bands deafness fix on
* the 8852C). Vendor core dispatcher — per-chip via ic_type. */
halbb_gpio_setting_init(bb);
/* Enable both RX chains (rx_path_en). Vendor core dispatcher; its 8852C
* case passes hal_com->dbcc_en (0 here) — same as the direct call did. */
halbb_ctrl_rx_path(bb, RF_PATH_AB, HW_PHY_0);
/* 8852C physts MEASUREMENT bring-up. Devourer's minimal halbb bring-up runs
* only halbb_init_reg (BB table) + this, skipping the vendor's
* halbb_dm_init_per_phy measurement inits. On the 8852B the physts engine
* fills reports anyway (its table covers it); on the 8852C the reports arrive
* EMPTY (is_valid=0) without these — halbb_ic_hw_setting_init_8852c sets the
* BB evm/measurement report-enable (0xa10[0]), and the physts CR map + IE
* bitmap must be programmed for the engine to snapshot RSSI/SNR/EVM. */
#ifdef BB_8852C_SUPPORT
if (bb->ic_type == BB_RTL8852C) {
halbb_ic_hw_setting_init_8852c(bb); /* 0xa10[0] evm/measurement rpt-en */
halbb_cr_cfg_physts_init(bb);
halbb_physts_parsing_init(bb);
}
#endif
}
void kestrel_halbb_set_gain(struct kestrel_halbb_ctx *ctx, unsigned char central_ch,
unsigned char band_type) {
if (!ctx)
return;
struct bb_info *bb = &ctx->bb;
if (bb->ic_type == BB_RTL8852B) {
#ifdef BB_8852B_SUPPORT
/* The 8852B loader applies both paths in one call (no efem arg). */
halbb_set_gain_error_8852b(bb, central_ch, (enum band_type)band_type);
#endif
} else {
#ifdef BB_8852C_SUPPORT
/* is_efem=false (compact USB dongle, no external LNA). Vendor skips 2.4G
* gain-error internally. */
halbb_set_gain_error_8852c(bb, central_ch, (enum band_type)band_type,
false, RF_PATH_A);
halbb_set_gain_error_8852c(bb, central_ch, (enum band_type)band_type,
false, RF_PATH_B);
#endif
}
}
void kestrel_halbb_ctrl_bw_ch(struct kestrel_halbb_ctx *ctx, unsigned char pri_ch,
unsigned char central_ch, unsigned char bw,
unsigned char band_type) {
if (!ctx)
return;
/* Vendor core dispatcher (halbb_api.c): its per-chip case forwards to
* halbb_ctrl_bw_ch_<chip> with these exact arguments (seg1 is 80+80-only,
* unused on both chips). */
halbb_ctrl_bw_ch(&ctx->bb, pri_ch, central_ch, /*central_ch_seg1=*/0,
(enum band_type)band_type, (enum channel_width)bw,
HW_PHY_0);
}
void kestrel_halbb_ctrl_tx_path(struct kestrel_halbb_ctx *ctx) {
/* 8852C-only: the 8852B routes TX antennas per-STA via the CMAC antenna
* model (TXWD/cctl), there is no path-com block to program. */
#ifdef BB_8852C_SUPPORT
if (ctx && ctx->bb.ic_type == BB_RTL8852C)
halbb_ctrl_tx_path_tmac_8852c(&ctx->bb, RF_PATH_A, false);
#else
(void)ctx;
#endif
}
/* One-shot active/frame-free NHM absolute noise floor. See the header. */
int kestrel_halbb_env_mntr_nhm(struct kestrel_halbb_ctx *ctx,
unsigned short mntr_time_ms,
signed char *nhm_pwr_dbm) {
struct bb_info *bb;
struct ccx_para_info para;
struct env_trig_rpt trig;
struct env_mntr_rpt rpt;
void *drv;
u16 mtime;
int i;
if (!ctx || !nhm_pwr_dbm)
return 0;
bb = &ctx->bb;
drv = bb->hal_com->drv_priv;
mtime = mntr_time_ms ? mntr_time_ms : 100;
/* Lazy env-monitor init: the RX bring-up flow (kestrel_halbb_init_reg) only
* runs halbb_init_reg, so the NHM CR addresses (incl. nhm_rdy) and the ccx/nhm
* state are still zero. Run the two vendor inits once before the first
* trigger. */
if (!ctx->env_mntr_ready) {
halbb_cr_cfg_env_mntr_init(bb);
halbb_env_mntr_init(bb);
ctx->env_mntr_ready = 1;
}
/* One-shot NHM in the vendor's IEEE-11k idle-noise mode. A zeroed para gives
* nhm_incld_cca=NHM_EXCLUDE_CCA + nav/rssi gating DISABLED (all enum 0). */
_os_mem_set(0, &para, 0, sizeof(para));
para.rac_lv = RAC_LV_4; /* debug priority: always wins the racing arbiter */
para.mntr_time = mtime; /* ms; drives ccx_period (must be nonzero) */
para.nhm_app = NHM_DBG_11K; /* 802.11k noise-floor thresholds */
if (!(halbb_env_mntr_trigger(bb, &para, &trig, HW_PHY_0) & NHM_SUCCESS))
return 0;
/* The measurement runs mntr_time in HW; wait the window, then poll the ready
* bit (halbb_env_mntr_result returns NHM_SUCCESS once nhm_rdy is set). */
_os_delay_ms(drv, mtime);
for (i = 0; i < 8; ++i) {
_os_mem_set(0, &rpt, 0, sizeof(rpt));
if ((halbb_env_mntr_result(bb, &rpt, HW_PHY_0) & NHM_SUCCESS) &&
rpt.nhm_pwr != ENV_MNTR_FAIL_BYTE) {
*nhm_pwr_dbm = (signed char)((int)rpt.nhm_pwr - 110); /* 110+x dBm */
return 1;
}
_os_delay_ms(drv, 3);
}
return 0;
}
void kestrel_halbb_destroy(struct kestrel_halbb_ctx *ctx) {
if (ctx)
free(ctx);
}
3rd/devourer/hal/halbb/g6/kestrel_halbb_glue.h
+83
View File
@@ -0,0 +1,83 @@
/* C/C++ boundary for the vendored halbb-G6 baseband plane (both Kestrel
* chips).
*
* The vendored halbb C (compiled behind hal/halbb/hal_headers_le.h) owns the
* full `struct bb_info` and the BB functions (gpio routing, RX-path enable,
* per-band gain-error, per-channel BB config). This header exposes an OPAQUE
* handle + a tiny API so devourer's C++ (RtlKestrelDevice/HalKestrel) can
* drive them WITHOUT including any halbb header — the C++ side only sees
* plain types + the register bridge. Chip dispatch is the vendor core's own
* runtime ic_type switch; the glue only selects the ic_type at create and
* forks the few entry points that have no generic dispatcher.
*
* Register/OS access is routed back to devourer through kestrel_halbb_bridge
* (shim/halbb_bridge.h): the caller fills its callbacks (BB window read/write,
* MAC pwr-reg read/write, delay, XTAL-SI) pointing at its RtlAdapter, then
* hands it in.
*/
#ifndef KESTREL_HALBB_GLUE_H
#define KESTREL_HALBB_GLUE_H
#include "shim/halbb_bridge.h"
#ifdef __cplusplus
extern "C" {
#endif
struct kestrel_halbb_ctx; /* opaque; owns a bb_info + hal_com/phl_com */
/* Allocate + populate a bb_info for `chip`, non-DBCC, HW_PHY_0, RX_PATH_AB.
* `br` must outlive the ctx (its callbacks are stored; br->bb_info is set to
* the live bb so the halrf plane's cross-plane calls resolve). `cut` = chip
* cut version, `rfe_type` = efuse RFE type (drives the gpio/gain RFE branch). */
struct kestrel_halbb_ctx *kestrel_halbb_create(struct kestrel_halbb_bridge *br,
enum kestrel_chip chip,
unsigned char cut,
unsigned char rfe_type);
void kestrel_halbb_destroy(struct kestrel_halbb_ctx *ctx);
/* Apply the built-in BB register table + gain table + efuse RX gain offsets
* via the vendor's own loader flow (halbb_init_reg). Returns nonzero on
* success. Run after the MAC's enable_bb_rf, before rx_bringup. */
int kestrel_halbb_init_reg(struct kestrel_halbb_ctx *ctx);
/* One-shot RX bring-up: the LNAON/TRSW/PAPE RF-front-end gpio routing
* (halbb_gpio_setting_init), then enable the RX chains (halbb_ctrl_rx_path).
* The gain cache is loaded by kestrel_halbb_init_reg. */
void kestrel_halbb_rx_bringup(struct kestrel_halbb_ctx *ctx);
/* Per-channel: apply the cached per-band LNA/TIA gain-error
* (halbb_set_gain_error_<chip>). band_type: 0 = 2.4G (vendor skips
* gain-error), 1 = 5G, 2 = 6G. */
void kestrel_halbb_set_gain(struct kestrel_halbb_ctx *ctx, unsigned char central_ch,
unsigned char band_type);
/* Full vendor per-channel BB config (halbb_ctrl_bw_ch -> per-chip backend):
* gain-error, hidden/normal efuse RX gain, band mode-sel, SCO comp, BW/RXBB/
* ADC, CCK en. bw is enum channel_width (20=0,40=1,80=2,160=3,5=6,10=7);
* band_type 0=2.4G,1=5G,2=6G. */
void kestrel_halbb_ctrl_bw_ch(struct kestrel_halbb_ctx *ctx, unsigned char pri_ch,
unsigned char central_ch, unsigned char bw,
unsigned char band_type);
/* T-MAC TX path-com routing (halbb_ctrl_tx_path_tmac_8852c): the 0xD800..
* 0xD820 path-com block (per-cut, via the MAC pwr-reg plane) + the 0x9a4 path
* enable + both-path TSSI reset. Connects the BB IFFT output to the TX chain.
* 8852C-only — the 8852B selects its TX antenna per-STA via the CMAC antenna
* model, so this is a no-op there. Single-PHY, RF_PATH_A. */
void kestrel_halbb_ctrl_tx_path(struct kestrel_halbb_ctx *ctx);
/* One-shot active/frame-free NHM absolute noise floor. Runs a manual IEEE-11k
* NHM measurement over `mntr_time_ms` (0 -> 100) and returns the
* idle in-band power as signed dBm (nhm_pwr - 110). Frame-free, BB-driven, no
* clock-stop -> no RX wedge. Lazily runs halbb_cr_cfg_env_mntr_init +
* halbb_env_mntr_init on first call (the RX bring-up path does not). Returns 1
* on a valid reading (fills *nhm_pwr_dbm), 0 on timeout/failure. */
int kestrel_halbb_env_mntr_nhm(struct kestrel_halbb_ctx *ctx,
unsigned short mntr_time_ms,
signed char *nhm_pwr_dbm);
#ifdef __cplusplus
}
#endif
#endif /* KESTREL_HALBB_GLUE_H */
3rd/devourer/hal/halbb/g6/kestrel_halbb_helpers.c
+231
View File
@@ -0,0 +1,231 @@
/* Disabled-path stubs for the vendored halbb-G6 8852C RX bring-up.
*
* With FW offload OFF (HALBB_FW_OFLD_SUPPORT=0, dev_cap.io_ofld=0) the register
* writers reference three fwofld entry points that would otherwise drag the
* whole cmd-offload/MAC surface in. check_fw_ofld returns false (so the direct
* register path is always taken); fw_delay/fw_set_reg are never reached at
* runtime. Providing them here avoids vendoring halbb_fwofld.c. Compiled as C
* behind the shim, same as the vendored .c. */
#include "halbb_precomp.h"
bool halbb_check_fw_ofld(struct bb_info *bb) { (void)bb; return false; }
bool halbb_fw_delay(struct bb_info *bb, u32 val) { (void)bb; (void)val; return false; }
bool halbb_fw_set_reg(struct bb_info *bb, u32 addr, u32 mask, u32 val, u8 lc) {
(void)bb; (void)addr; (void)mask; (void)val; (void)lc; return false;
}
bool halbb_fw_set_reg_cmn(struct bb_info *bb, u32 addr, u32 mask, u32 val,
enum phl_phy_idx phy_idx, u8 lst_cmd) {
(void)bb; (void)addr; (void)mask; (void)val; (void)phy_idx; (void)lst_cmd;
return false;
}
/* halbb_pmac_setting.c brackets set_tmac_tx/restore_info with this fwofld
* batching toggle — with io_ofld off it only flips bb_cmn_hooker state the
* direct register path never reads. */
void halbb_fwofld_bitmap_en(struct bb_info *bb, bool en, enum fw_ofld_type app) {
(void)bb; (void)en; (void)app;
}
/* The halbb_ctrl_bw_ch dispatcher's 8852B case branches on
* halbb_check_fw_ofld (false above), so this fwofld variant is never called —
* the symbol just has to link (halbb_8852b_fwofld_api.c is not vendored). */
bool halbb_fwofld_ctrl_bw_ch_8852b(struct bb_info *bb, u8 pri_ch, u8 central_ch,
enum channel_width bw, enum band_type band,
enum phl_phy_idx phy_idx) {
(void)bb; (void)pri_ch; (void)central_ch; (void)bw; (void)band; (void)phy_idx;
return false;
}
/* DV/PXP (design-verification platform) debug print toggle (halbb_dv_dbg.c,
* not vendored) — a log-gate only. */
void halbb_dv_pxp_print_en(struct bb_info *bb, bool en) {
(void)bb; (void)en;
}
/* TPU / TSSI-ctrl MAC CR init (halbb_pwr_ctrl.c, not vendored) — the vendor's
* TX-power-unit plane. Devourer's hand-ported fixed-dBm TXAGC owns the MAC
* power CRs (set_txpwr_dbm, applied at every set_channel), so the vendor
* init stays a no-op here; the pwr_ctrl TU would come in with a
* TSSI-referenced power model. */
void halbb_tpu_mac_cr_init(struct bb_info *bb, enum phl_phy_idx phy_idx) {
(void)bb; (void)phy_idx;
}
void halbb_tssi_ctrl_mac_cr_init(struct bb_info *bb, enum phl_phy_idx phy_idx) {
(void)bb; (void)phy_idx;
}
/* fwofld variants behind halbb_check_fw_ofld (false above) — link-only. */
bool halbb_fwcfg_bb_phy_8852b(struct bb_info *bb, u32 addr, u32 data,
enum phl_phy_idx phy_idx) {
(void)bb; (void)addr; (void)data; (void)phy_idx;
return false;
}
void halbb_fwofld_set_gain_cr_init_8852c(struct bb_info *bb) { (void)bb; }
/* Spur suppression (halbb_spur_suppress.c, not vendored): channel-specific NBI
* /CSI notch, not RX-hearing-critical — no-op (no spur notch). */
void halbb_csi_tone_idx(struct bb_info *bb, u8 central_ch, enum channel_width bw,
enum band_type band, enum phl_phy_idx phy_idx) {
(void)bb; (void)central_ch; (void)bw; (void)band; (void)phy_idx;
}
void halbb_nbi_tone_idx(struct bb_info *bb, u8 central_ch, u8 pri_ch,
enum channel_width bw, enum band_type band,
enum rf_path path) {
(void)bb; (void)central_ch; (void)pri_ch; (void)bw; (void)band; (void)path;
}
/* ---- Link-only stubs for the un-vendored halbb subsystems ----------------
*
* The verbatim vendor TUs reference entry points that live in halbb .c files
* we deliberately do NOT vendor. No runtime path reaches them (the callers
* are un-driven vendor entry points kept verbatim), and GNU --gc-sections
* dead-strips the references on Linux — but MSVC and MinGW ld resolve
* archive members before dead-stripping, so the symbols must exist at link.
* Signatures match the vendored header prototypes exactly (this TU includes
* them via halbb_precomp.h). */
/* BB debug port (halbb_dbg.c, not vendored): register-window arbitration for
* the vendor debug console + the fw dbg-print C2H decoder. */
u32 halbb_get_bb_dbg_port_idx(struct bb_info *bb) { (void)bb; return 0; }
void halbb_set_bb_dbg_port(struct bb_info *bb, u32 dbg_port) {
(void)bb; (void)dbg_port;
}
void halbb_set_bb_dbg_port_ip(struct bb_info *bb, enum bb_dbg_port_ip_t ip) {
(void)bb; (void)ip;
}
void halbb_release_bb_dbg_port(struct bb_info *bb) { (void)bb; }
bool halbb_bb_dbg_port_racing(struct bb_info *bb, u8 curr_dbg_priority) {
(void)bb; (void)curr_dbg_priority;
return false; /* port not granted */
}
u32 halbb_get_bb_dbg_port_val(struct bb_info *bb) { (void)bb; return 0; }
void halbb_cr_hook_fake_init(struct bb_info *bb, u32 *str_table, u32 len) {
(void)bb; (void)str_table; (void)len;
}
void halbb_cr_hook_init_dump(struct bb_info *bb, u32 *str_table, u32 len) {
(void)bb; (void)str_table; (void)len;
}
u32 halbb_c2h_fw_dbg(struct bb_info *bb, u16 len, u8 *c2h) {
(void)bb; (void)len; (void)c2h;
return 0;
}
/* MP / mass-production counters (halbb_mp_ex.c, not vendored). */
u32 halbb_mp_get_rx_crc_ok(struct bb_info *bb, enum phl_phy_idx phy_idx) {
(void)bb; (void)phy_idx;
return 0;
}
u32 halbb_mp_get_rx_crc_err(struct bb_info *bb, enum phl_phy_idx phy_idx) {
(void)bb; (void)phy_idx;
return 0;
}
void halbb_dbg_port_sel(struct bb_info *bb, u16 dbg_port_sel, u8 dbg_port_ip_sel,
bool dbg_port_ref_clk_en, bool dbg_port_en) {
(void)bb; (void)dbg_port_sel; (void)dbg_port_ip_sel;
(void)dbg_port_ref_clk_en; (void)dbg_port_en;
}
/* RA rate-adaptive reports (halbb_ra.c, not vendored): rate parsing helpers
* + the fw RA-report / TX-history / TX-status C2H decoders. */
bool halbb_is_cck_rate(struct bb_info *bb, u16 rate) {
(void)bb; (void)rate;
return false;
}
enum bb_mode_type halbb_get_rate_mode(struct bb_info *bb, u16 rate_idx) {
(void)bb; (void)rate_idx;
return BB_LEGACY_MODE;
}
void halbb_rate_idx_parsor(struct bb_info *bb, u16 rate_idx,
enum rtw_gi_ltf gi_ltf, struct bb_rate_info *ra_i) {
(void)bb; (void)rate_idx; (void)gi_ltf; (void)ra_i;
}
void halbb_print_rate_2_buff(struct bb_info *bb, u16 rate_idx,
enum rtw_gi_ltf gi_ltf, char *buf, u16 buf_size) {
(void)bb; (void)rate_idx; (void)gi_ltf;
if (buf && buf_size)
buf[0] = '\0';
}
u32 halbb_get_fw_ra_rpt(struct bb_info *bb, u16 len, u8 *c2h) {
(void)bb; (void)len; (void)c2h;
return 0;
}
void halbb_get_fw_c2h_tx_hist(struct bb_info *bb, u16 len, u8 *c2h) {
(void)bb; (void)len; (void)c2h;
}
u32 halbb_get_fw_ra_dbgrpt_wifi7(struct bb_info *bb, u16 len, u8 *c2h) {
(void)bb; (void)len; (void)c2h;
return 0;
}
u32 halbb_get_txsts_rpt(struct bb_info *bb, u16 len, u8 *c2h) {
(void)bb; (void)len; (void)c2h;
return 0;
}
/* FW statistics C2H (halbb_statistics.c fw half, not vendored). */
u32 halbb_get_fw_c2h_statistics(struct bb_info *bb_0, u16 len, u8 *c2h) {
(void)bb_0; (void)len; (void)c2h;
return 0;
}
/* Common per-frame report plane (halbb_cmn_rpt.c, not vendored). */
void halbb_cmn_rpt(struct bb_info *bb, struct physts_rxd *desc,
u32 physts_bitmap) {
(void)bb; (void)desc; (void)physts_bitmap;
}
u8 halbb_get_rssi_min(struct bb_info *bb) { (void)bb; return 0; }
/* Antenna / TX-path diversity (halbb_ant_div.c / halbb_path_div.c /
* halbb_rua_tbl.c, not vendored). */
void halbb_antdiv_phy_sts(struct bb_info *bb, u32 physts_bitmap,
struct physts_rxd *desc) {
(void)bb; (void)physts_bitmap; (void)desc;
}
void halbb_pathdiv_phy_sts(struct bb_info *bb, struct physts_rxd *desc) {
(void)bb; (void)desc;
}
void halbb_set_tx_path(struct bb_info *bb, u16 macid,
enum bb_path tx_path_sel_1ss) {
(void)bb; (void)macid; (void)tx_path_sel_1ss;
}
u32 halbb_trxpath_notif(struct bb_info *bb, enum rf_path tx_path,
enum rf_path rx_path) {
(void)bb; (void)tx_path; (void)rx_path;
return 0;
}
/* Dynamic 1R-CCA / DTR watchdog mechanisms (halbb_dyn_1r_cca.c /
* halbb_dyn_dtr.c, not vendored). */
void halbb_dyn_1r_cca(struct bb_info *bb) { (void)bb; }
void halbb_dyn_1r_cca_rst(struct bb_info *bb) { (void)bb; }
void halbb_dyn_dtr_watchdog(struct bb_info *bb) { (void)bb; }
/* Watchdog pause arbitration (halbb_init.c pause half, not vendored). */
u8 halbb_pause_func(struct bb_info *bb, enum habb_fun_t pause_func,
enum halbb_pause_type pause_type,
enum halbb_pause_lv_type lv,
u8 val_lehgth,
u32 *val_buf, enum phl_phy_idx phy_idx) {
(void)bb; (void)pause_func; (void)pause_type; (void)lv; (void)val_lehgth;
(void)val_buf; (void)phy_idx;
return 0;
}
/* TSSI band-edge config (halbb_pwr_ctrl.c, not vendored — same subsystem as
* the tpu/tssi cr-init no-ops above). */
void halbb_tssi_ctrl_set_bandedge_cfg(struct bb_info *bb,
enum phl_phy_idx phy_idx,
enum tssi_bandedge_cfg bandedge_cfg) {
(void)bb; (void)phy_idx; (void)bandedge_cfg;
}
/* BE (11BE / WiFi7) primary-sub-band helper referenced by halbb_env_mntr.c's
* EDCCA-opt path only in its 11BE branch - dead code on the AX Kestrel ICs
* (halbb_api_be.c is not vendored). A link-only stub, never called at runtime. */
u8 halbb_get_prim_sb(struct bb_info *bb, u8 central_ch, u8 pri_ch,
enum channel_width bw) {
(void)bb; (void)central_ch; (void)pri_ch; (void)bw;
return 0;
}
3rd/devourer/hal/halbb/g6/shim/hal_general_def.h
+492
View File
@@ -0,0 +1,492 @@
/******************************************************************************
*
* Copyright(c) 2019 - 2023 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HAL_GENERAL_DEF_H_
#define _HAL_GENERAL_DEF_H_
#define FL_COMP_VER BIT0
#define FL_COMP_INIT BIT1
#define FL_COMP_TASK BIT2
#define FL_COMP_CNS BIT3
#define FL_COMP_H2C BIT4
#define FL_COMP_C2H BIT5
#define FL_COMP_TX BIT6
#define FL_COMP_RX BIT7
#define FL_COMP_IPSEC BIT8
#define FL_COMP_TIMER BIT9
#define FL_COMP_DBGPKT BIT10
#define FL_COMP_PS BIT11
#define FL_COMP_BB BIT16
#define FL_COMP_TWT BIT17
#define FL_COMP_MCC BIT20
#define FL_COMP_NAN BIT26
#define FL_COMP_SCAN BIT28
#define RTW_MAC_TBTT_AGG_DEF 1
/* RXBUF should larger than RXBD, or it will cause RX RDU
the minimum number of RXBUF - RXBD is 32 */
#define RTW_RX_BUF_BD_MIN_DIFF 32
enum rtw_chip_id {
CHIP_WIFI6_8852A,
CHIP_WIFI6_8834A,
CHIP_WIFI6_8852B,
CHIP_WIFI6_8852C,
CHIP_WIFI6_8852D,
CHIP_WIFI6_8192XB,
CHIP_WIFI6_8832BR,
CHIP_WIFI6_8852BP,
CHIP_WIFI7_8922A,
CHIP_WIFI6_8851B,
CHIP_WIFI6_8852BT,
CHIP_WIFI6_8852BPT,
CHIP_WIFI6_8842A,
CHIP_WIFI6_MAX
};
enum rtw_efuse_info {
/* MAC Part */
EFUSE_INFO_MAC_ADDR,
EFUSE_INFO_MAC_PID,
EFUSE_INFO_MAC_DID,
EFUSE_INFO_MAC_VID,
EFUSE_INFO_MAC_SVID,
EFUSE_INFO_MAC_SMID,
EFUSE_INFO_MAC_MAX,
/* BB Part */
EFUSE_INFO_BB_ANTDIV,
EFUSE_INFO_BB_MAX,
/* RF Part */
EFUSE_INFO_RF_PKG_TYPE,
EFUSE_INFO_RF_PA,
EFUSE_INFO_RF_VALID_PATH,
EFUSE_INFO_RF_RFE,
EFUSE_INFO_RF_TXPWR,
EFUSE_INFO_RF_BOARD_OPTION,
EFUSE_INFO_RF_CHAN_PLAN,
EFUSE_INFO_RF_CHAN_PLAN_6GHZ,
EFUSE_INFO_RF_CHAN_PLAN_FORCE_HW,
EFUSE_INFO_RF_COUNTRY,
EFUSE_INFO_RF_THERMAL,
EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_1,
EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_2,
EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_3,
EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_4,
EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_5,
EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_6,
EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_1,
EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_2,
EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_3,
EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_4,
EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_5,
EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_1,
EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_2,
EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_3,
EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_4,
EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_5,
EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_6,
EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_7,
EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_8,
EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_9,
EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_10,
EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_11,
EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_12,
EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_13,
EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_14,
EFUSE_INFO_RF_5G_BW20M1S_BW40M1S_A_DIFF,
EFUSE_INFO_RF_5G_OFDM1T_BW40M1S_A_DIFF,
EFUSE_INFO_RF_5G_BW40M2S_BW40M1S_A_DIFF,
EFUSE_INFO_RF_5G_BW20M2S_BW20M1S_A_DIFF,
EFUSE_INFO_RF_5G_BW40M3S_BW40M2S_A_DIFF,
EFUSE_INFO_RF_5G_BW20M3S_BW20M2S_A_DIFF,
EFUSE_INFO_RF_5G_BW40M4S_BW40M3S_A_DIFF,
EFUSE_INFO_RF_5G_BW20M4S_BW20M3S_A_DIFF,
EFUSE_INFO_RF_5G_OFDM2T_OFDM1T_A_DIFF,
EFUSE_INFO_RF_5G_OFDM3T_OFDM2T_A_DIFF,
EFUSE_INFO_RF_5G_OFDM4T_OFDM3T_A_DIFF,
EFUSE_INFO_RF_5G_BW80M1S_BW40M1S_A_DIFF,
EFUSE_INFO_RF_5G_BW160M1S_BW80M1S_A_DIFF,
EFUSE_INFO_RF_5G_BW80M2S_BW80M1S_A_DIFF,
EFUSE_INFO_RF_5G_BW160M2S_BW160M1S_A_DIFF,
EFUSE_INFO_RF_5G_BW80M3S_BW80M2S_A_DIFF,
EFUSE_INFO_RF_5G_BW160M3S_BW160M2S_A_DIFF,
EFUSE_INFO_RF_5G_BW80M4S_BW80M3S_A_DIFF,
EFUSE_INFO_RF_5G_BW160M4S_BW160M3S_A_DIFF,
EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_1,
EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_2,
EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_3,
EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_4,
EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_5,
EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_6,
EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_1,
EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_2,
EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_3,
EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_4,
EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_5,
EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_1,
EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_2,
EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_3,
EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_4,
EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_5,
EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_6,
EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_7,
EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_8,
EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_9,
EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_10,
EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_11,
EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_12,
EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_13,
EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_14,
EFUSE_INFO_RF_5G_BW20M1S_BW40M1S_B_DIFF,
EFUSE_INFO_RF_5G_OFDM1T_BW40M1S_B_DIFF,
EFUSE_INFO_RF_5G_BW40M2S_BW40M1S_B_DIFF,
EFUSE_INFO_RF_5G_BW20M2S_BW20M1S_B_DIFF,
EFUSE_INFO_RF_5G_BW40M3S_BW40M2S_B_DIFF,
EFUSE_INFO_RF_5G_BW20M3S_BW20M2S_B_DIFF,
EFUSE_INFO_RF_5G_BW40M4S_BW40M3S_B_DIFF,
EFUSE_INFO_RF_5G_BW20M4S_BW20M3S_B_DIFF,
EFUSE_INFO_RF_5G_OFDM2T_OFDM1T_B_DIFF,
EFUSE_INFO_RF_5G_OFDM3T_OFDM2T_B_DIFF,
EFUSE_INFO_RF_5G_OFDM4T_OFDM3T_B_DIFF,
EFUSE_INFO_RF_5G_BW80M1S_BW40M1S_B_DIFF,
EFUSE_INFO_RF_5G_BW160M1S_BW80M1S_B_DIFF,
EFUSE_INFO_RF_5G_BW80M2S_BW80M1S_B_DIFF,
EFUSE_INFO_RF_5G_BW160M2S_BW160M1S_B_DIFF,
EFUSE_INFO_RF_5G_BW80M3S_BW80M2S_B_DIFF,
EFUSE_INFO_RF_5G_BW160M3S_BW160M2S_B_DIFF,
EFUSE_INFO_RF_5G_BW80M4S_BW80M3S_B_DIFF,
EFUSE_INFO_RF_5G_BW160M4S_BW160M3S_B_DIFF,
EFUSE_INFO_RF_2G_CCK_C_TSSI_DE_1,
EFUSE_INFO_RF_2G_CCK_C_TSSI_DE_2,
EFUSE_INFO_RF_2G_CCK_C_TSSI_DE_3,
EFUSE_INFO_RF_2G_CCK_C_TSSI_DE_4,
EFUSE_INFO_RF_2G_CCK_C_TSSI_DE_5,
EFUSE_INFO_RF_2G_CCK_C_TSSI_DE_6,
EFUSE_INFO_RF_2G_BW40M_C_TSSI_DE_1,
EFUSE_INFO_RF_2G_BW40M_C_TSSI_DE_2,
EFUSE_INFO_RF_2G_BW40M_C_TSSI_DE_3,
EFUSE_INFO_RF_2G_BW40M_C_TSSI_DE_4,
EFUSE_INFO_RF_2G_BW40M_C_TSSI_DE_5,
EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_1,
EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_2,
EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_3,
EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_4,
EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_5,
EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_6,
EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_7,
EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_8,
EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_9,
EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_10,
EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_11,
EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_12,
EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_13,
EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_14,
EFUSE_INFO_RF_5G_BW20M1S_BW40M1S_C_DIFF,
EFUSE_INFO_RF_5G_OFDM1T_BW40M1S_C_DIFF,
EFUSE_INFO_RF_5G_BW40M2S_BW40M1S_C_DIFF,
EFUSE_INFO_RF_5G_BW20M2S_BW20M1S_C_DIFF,
EFUSE_INFO_RF_5G_BW40M3S_BW40M2S_C_DIFF,
EFUSE_INFO_RF_5G_BW20M3S_BW20M2S_C_DIFF,
EFUSE_INFO_RF_5G_BW40M4S_BW40M3S_C_DIFF,
EFUSE_INFO_RF_5G_BW20M4S_BW20M3S_C_DIFF,
EFUSE_INFO_RF_5G_OFDM2T_OFDM1T_C_DIFF,
EFUSE_INFO_RF_5G_OFDM3T_OFDM2T_C_DIFF,
EFUSE_INFO_RF_5G_OFDM4T_OFDM3T_C_DIFF,
EFUSE_INFO_RF_5G_BW80M1S_BW40M1S_C_DIFF,
EFUSE_INFO_RF_5G_BW160M1S_BW80M1S_C_DIFF,
EFUSE_INFO_RF_5G_BW80M2S_BW80M1S_C_DIFF,
EFUSE_INFO_RF_5G_BW160M2S_BW160M1S_C_DIFF,
EFUSE_INFO_RF_5G_BW80M3S_BW80M2S_C_DIFF,
EFUSE_INFO_RF_5G_BW160M3S_BW160M2S_C_DIFF,
EFUSE_INFO_RF_5G_BW80M4S_BW80M3S_C_DIFF,
EFUSE_INFO_RF_5G_BW160M4S_BW160M3S_C_DIFF,
EFUSE_INFO_RF_2G_CCK_D_TSSI_DE_1,
EFUSE_INFO_RF_2G_CCK_D_TSSI_DE_2,
EFUSE_INFO_RF_2G_CCK_D_TSSI_DE_3,
EFUSE_INFO_RF_2G_CCK_D_TSSI_DE_4,
EFUSE_INFO_RF_2G_CCK_D_TSSI_DE_5,
EFUSE_INFO_RF_2G_CCK_D_TSSI_DE_6,
EFUSE_INFO_RF_2G_BW40M_D_TSSI_DE_1,
EFUSE_INFO_RF_2G_BW40M_D_TSSI_DE_2,
EFUSE_INFO_RF_2G_BW40M_D_TSSI_DE_3,
EFUSE_INFO_RF_2G_BW40M_D_TSSI_DE_4,
EFUSE_INFO_RF_2G_BW40M_D_TSSI_DE_5,
EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_1,
EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_2,
EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_3,
EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_4,
EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_5,
EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_6,
EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_7,
EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_8,
EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_9,
EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_10,
EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_11,
EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_12,
EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_13,
EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_14,
EFUSE_INFO_RF_5G_BW20M1S_BW40M1S_D_DIFF,
EFUSE_INFO_RF_5G_OFDM1T_BW40M1S_D_DIFF,
EFUSE_INFO_RF_5G_BW40M2S_BW40M1S_D_DIFF,
EFUSE_INFO_RF_5G_BW20M2S_BW20M1S_D_DIFF,
EFUSE_INFO_RF_5G_BW40M3S_BW40M2S_D_DIFF,
EFUSE_INFO_RF_5G_BW20M3S_BW20M2S_D_DIFF,
EFUSE_INFO_RF_5G_BW40M4S_BW40M3S_D_DIFF,
EFUSE_INFO_RF_5G_BW20M4S_BW20M3S_D_DIFF,
EFUSE_INFO_RF_5G_OFDM2T_OFDM1T_D_DIFF,
EFUSE_INFO_RF_5G_OFDM3T_OFDM2T_D_DIFF,
EFUSE_INFO_RF_5G_OFDM4T_OFDM3T_D_DIFF,
EFUSE_INFO_RF_5G_BW80M1S_BW40M1S_D_DIFF,
EFUSE_INFO_RF_5G_BW160M1S_BW80M1S_D_DIFF,
EFUSE_INFO_RF_5G_BW80M2S_BW80M1S_D_DIFF,
EFUSE_INFO_RF_5G_BW160M2S_BW160M1S_D_DIFF,
EFUSE_INFO_RF_5G_BW80M3S_BW80M2S_D_DIFF,
EFUSE_INFO_RF_5G_BW160M3S_BW160M2S_D_DIFF,
EFUSE_INFO_RF_5G_BW80M4S_BW80M3S_D_DIFF,
EFUSE_INFO_RF_5G_BW160M4S_BW160M3S_D_DIFF,
EFUSE_INFO_RF_THERMAL_A,
EFUSE_INFO_RF_THERMAL_B,
EFUSE_INFO_RF_THERMAL_C,
EFUSE_INFO_RF_THERMAL_D,
EFUSE_INFO_RF_XTAL,
EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_1,
EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_2,
EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_3,
EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_4,
EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_5,
EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_6,
EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_7,
EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_8,
EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_9,
EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_10,
EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_11,
EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_12,
EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_13,
EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_14,
EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_15,
EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_16,
EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_17,
EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_18,
EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_19,
EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_20,
EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_21,
EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_22,
EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_23,
EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_24,
EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_25,
EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_26,
EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_27,
EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_28,
EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_29,
EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_30,
EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_31,
EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_32,
EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_1,
EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_2,
EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_3,
EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_4,
EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_5,
EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_6,
EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_7,
EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_8,
EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_9,
EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_10,
EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_11,
EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_12,
EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_13,
EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_14,
EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_15,
EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_16,
EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_17,
EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_18,
EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_19,
EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_20,
EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_21,
EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_22,
EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_23,
EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_24,
EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_25,
EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_26,
EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_27,
EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_28,
EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_29,
EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_30,
EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_31,
EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_32,
EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_1,
EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_2,
EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_3,
EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_4,
EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_5,
EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_6,
EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_7,
EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_8,
EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_9,
EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_10,
EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_11,
EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_12,
EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_13,
EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_14,
EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_15,
EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_16,
EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_17,
EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_18,
EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_19,
EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_20,
EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_21,
EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_22,
EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_23,
EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_24,
EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_25,
EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_26,
EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_27,
EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_28,
EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_29,
EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_30,
EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_31,
EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_32,
EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_1,
EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_2,
EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_3,
EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_4,
EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_5,
EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_6,
EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_7,
EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_8,
EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_9,
EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_10,
EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_11,
EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_12,
EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_13,
EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_14,
EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_15,
EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_16,
EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_17,
EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_18,
EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_19,
EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_20,
EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_21,
EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_22,
EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_23,
EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_24,
EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_25,
EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_26,
EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_27,
EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_28,
EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_29,
EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_30,
EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_31,
EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_32,
/*RX Gain K*/
EFUSE_INFO_RF_RX_GAIN_K_A_2G_CCK,
EFUSE_INFO_RF_RX_GAIN_K_A_2G_OFMD,
EFUSE_INFO_RF_RX_GAIN_K_A_5GL,
EFUSE_INFO_RF_RX_GAIN_K_A_5GM,
EFUSE_INFO_RF_RX_GAIN_K_A_5GH,
EFUSE_INFO_RF_RX_GAIN_K_A_6GL1,
EFUSE_INFO_RF_RX_GAIN_K_A_6GL2,
EFUSE_INFO_RF_RX_GAIN_K_A_6GL3,
EFUSE_INFO_RF_RX_GAIN_K_A_6GM1,
EFUSE_INFO_RF_RX_GAIN_K_A_6GM2,
EFUSE_INFO_RF_RX_GAIN_K_A_6GM3,
EFUSE_INFO_RF_RX_GAIN_K_A_6GH1,
EFUSE_INFO_RF_RX_GAIN_K_A_6GH2,
/*RF BW Power Diff*/
EFUSE_INFO_RF_5G_BW160M_BW40M_DIFF,
EFUSE_INFO_RF_6G_BW160M_BW40M_DIFF,
EFUSE_INFO_RF_6G_BW320M_BW160M_DIFF,
EFUSE_INFO_RF_MAX,
/* BTCOEX Part */
EFUSE_INFO_BTCOEX_COEX,
EFUSE_INFO_BTCOEX_ANT_NUM,
EFUSE_INFO_BTCOEX_ANT_PATH,
EFUSE_INFO_BTCOEX_MAX,
};
enum rtw_cv {
CAV,
CBV,
CCV,
CDV,
CEV,
CFV,
CGV,
CTV,
CV_MAX,
};
enum rtw_fv {
FTV,
FUV,
FSV,
FGV,
FV_MAX
};
enum rtw_dv_sel {
DAV,
DDV,
};
enum hal_pwr_by_rate_setting {
PW_BY_RATE_ON = 0,
PW_BY_RATE_ALL_SAME = 1
};
enum hal_pwr_limit_type {
PWLMT_BY_EFUSE = 0,
PWLMT_DISABLE = 1,
PWBYRATE_AND_PWLMT = 2
};
enum wl_func {
EFUSE_WL_FUNC_NONE = 0,
EFUSE_WL_FUNC_DRAGON = 0xe,
EFUSE_WL_FUNC_GENERAL = 0xf
};
enum hw_stype{
EFUSE_HW_STYPE_NONE = 0x0,
EFUSE_HW_STYPE_GENERAL = 0xf
};
enum n_bb_path {
BB_0PATH = 0,
BB_1PATH = 1,
BB_2PATH = 2,
BB_3PATH = 3,
};
enum n_rf_entity {
RF_1ENTITY = 1,
RF_2ENTITY = 2
};
#define BB0_N_PATH_SFT 0
#define BB1_N_PATH_SFT 4
#define RF_N_ENTITY_SFT 12
enum mlo_dbcc_mode_type { /* for HALBB/HALRF reference */
MLO_DBCC_NOT_SUPPORT = 0,
MLO_0_PLUS_2_1RF = (RF_1ENTITY << RF_N_ENTITY_SFT | BB_2PATH << BB1_N_PATH_SFT | BB_0PATH),
MLO_0_PLUS_2_2RF = (RF_2ENTITY << RF_N_ENTITY_SFT | BB_2PATH << BB1_N_PATH_SFT | BB_0PATH),
MLO_1_PLUS_1_1RF = (RF_1ENTITY << RF_N_ENTITY_SFT | BB_1PATH << BB1_N_PATH_SFT | BB_1PATH),
MLO_1_PLUS_1_2RF = (RF_2ENTITY << RF_N_ENTITY_SFT | BB_1PATH << BB1_N_PATH_SFT | BB_1PATH),
MLO_2_PLUS_0_1RF = (RF_1ENTITY << RF_N_ENTITY_SFT | BB_0PATH << BB1_N_PATH_SFT | BB_2PATH),
MLO_2_PLUS_0_2RF = (RF_2ENTITY << RF_N_ENTITY_SFT | BB_0PATH << BB1_N_PATH_SFT | BB_2PATH),
MLO_2_PLUS_2_2RF = (RF_2ENTITY << RF_N_ENTITY_SFT | BB_2PATH << BB1_N_PATH_SFT | BB_2PATH),
DBCC_LEGACY = 0xffffffff /* ex:8852C DBCC (2PHY in 1BB) x 1 */
};
#endif /* _HAL_GENERAL_DEF_H_*/
3rd/devourer/hal/halbb/g6/shim/halbb_bridge.h
+68
View File
@@ -0,0 +1,68 @@
/* halbb-G6 shim bridge — the register/OS plane the vendored halbb/halrf C
* bottoms out in, routed to devourer's RtlAdapter. C ABI, shared by the shim'd
* vendor C and devourer's C++ (RtlKestrelDevice owns the bridge instance and
* installs the callbacks). See hal/halbb/g6/shim/ and tools/vendor_halbb_*.sh.
*
* The vendor code calls hal_write32(bb->hal_com, addr, val) etc.; hal_com's
* drv_priv points at a kestrel_halbb_bridge whose fn pointers reach the device.
*/
#ifndef KESTREL_HALBB_BRIDGE_H
#define KESTREL_HALBB_BRIDGE_H
#ifdef __cplusplus
extern "C" {
#endif
/* Which Kestrel chip the glue drives — selects ic_type/chip_id for the
* vendored cores' own runtime dispatch. */
enum kestrel_chip {
KESTREL_CHIP_8852B = 0,
KESTREL_CHIP_8852C = 1,
};
/* Opaque device cookie (a devourer RtlKestrelDevice* on the C++ side). */
struct kestrel_halbb_bridge {
void *dev; /* passed back to every callback */
unsigned int (*read32)(void *dev, unsigned int addr);
void (*write32)(void *dev, unsigned int addr, unsigned int val);
/* MAC power-register plane (rtw_hal_mac_*_pwr_reg): field/shift write. */
unsigned int (*read_pwr)(void *dev, unsigned int addr);
void (*write_pwr)(void *dev, unsigned int addr, unsigned int val);
/* RF-register plane (rtw_hal_*_rf_reg): 3-wire LSSI, masked field read/write
* per RF path. May be NULL when only the BB plane is used (halbb). */
unsigned int (*read_rf)(void *dev, unsigned int path, unsigned int addr,
unsigned int mask);
void (*write_rf)(void *dev, unsigned int path, unsigned int addr,
unsigned int mask, unsigned int val);
void (*delay_us)(void *dev, unsigned int us);
/* Logical-efuse field read: devourer parses `id` (enum rtw_efuse_info) out of
* its efuse shadow via the vendored 8852c map, writes `size` bytes to value.
* Returns nonzero on success. NULL on halbb-only / no-efuse builds. */
int (*efuse_get_info)(void *dev, unsigned int id, void *value,
unsigned int size);
/* diagnostic sink (BB_DBG/BB_WARNING) — may be NULL for no-op. */
void (*logline)(void *dev, const char *msg);
/* XTAL-SI plane (rtw_hal_mac_get/set_xsi): the 8852B's a-die SI reset
* (halrf_arfc_si_reset_8852b, on the halrf_dm_init RFK prologue) needs it.
* NULL-able: the shim falls back to a no-op (fine for the 8852C paths). */
unsigned char (*read_xsi)(void *dev, unsigned char offset);
void (*write_xsi)(void *dev, unsigned char offset, unsigned char val);
/* fwcmd H2C plane (rtw_hal_mac_send_h2c): `data` = content dwords,
* `len_bytes` = content length. The C++ side forwards ONLY the OUTSRC
* radio-page classes (8 = radio A, 9 = radio B, func = page#) into its
* mac_ax H2C encoder — every other halrf H2C stays inert, matching the
* validated bring-up. Returns 0 on success (and for ignored classes).
* NULL-able: the shim then reports success without sending. */
int (*send_h2c)(void *dev, unsigned char h2c_class, unsigned char h2c_func,
const unsigned int *data, unsigned short len_bytes);
/* The live struct bb_info* (set by kestrel_halbb_create). The shim's
* halrf->halbb cross-plane calls (rtw_hal_bb_backup_info / restore /
* tx_mode_switch — hal_api_bb.c in the vendor) resolve the bb instance
* through here, since the halrf ctx owns a different rtw_hal_com_t. */
void *bb_info;
};
#ifdef __cplusplus
}
#endif
#endif /* KESTREL_HALBB_BRIDGE_H */
3rd/devourer/hal/halbb/g6/shim/rtw_general_def.h
+683
View File
@@ -0,0 +1,683 @@
/******************************************************************************
*
* Copyright(c) 2019 - 2023 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _RTW_GENERAL_DEF_H_
#define _RTW_GENERAL_DEF_H_
#define SEC_CAP_CHK_BMC BIT0
#define BIT0 0x00000001
#define BIT1 0x00000002
#define BIT2 0x00000004
#define BIT3 0x00000008
#define BIT4 0x00000010
#define BIT5 0x00000020
#define BIT6 0x00000040
#define BIT7 0x00000080
#define BIT8 0x00000100
#define BIT9 0x00000200
#define BIT10 0x00000400
#define BIT11 0x00000800
#define BIT12 0x00001000
#define BIT13 0x00002000
#define BIT14 0x00004000
#define BIT15 0x00008000
#define BIT16 0x00010000
#define BIT17 0x00020000
#define BIT18 0x00040000
#define BIT19 0x00080000
#define BIT20 0x00100000
#define BIT21 0x00200000
#define BIT22 0x00400000
#define BIT23 0x00800000
#define BIT24 0x01000000
#define BIT25 0x02000000
#define BIT26 0x04000000
#define BIT27 0x08000000
#define BIT28 0x10000000
#define BIT29 0x20000000
#define BIT30 0x40000000
#define BIT31 0x80000000
#define RTW_U32_MAX 0xFFFFFFFF
enum rtl_ic_id {
RTL8852A,
RTL8834A,
RTL8852B,
RTL8852C,
RTL8842A,
RTL8852D,
RTL8192XB,
RTL8832BR,
RTL8852BP,
RTL8851B,
RTL8852BT,
RTL8852BPT,
MAX_IC_ID
};
/* BIT definition for combination */
enum rtw_hci_type {
RTW_HCI_PCIE = BIT0,
RTW_HCI_USB = BIT1,
RTW_HCI_SDIO = BIT2,
RTW_HCI_GSPI = BIT3,
RTW_HCI_MAX,
};
enum rtw_pcie_gen {
RTW_PCIE_GEN_UNKNOWN,
RTW_PCIE_GEN_1 = 1,
RTW_PCIE_GEN_2 = 2,
RTW_PCIE_GEN_MAX
};
#define SM_PS_STATIC 0
#define SM_PS_DYNAMIC 1
#define SM_PS_INVALID 2
#define SM_PS_DISABLE 3
#define MAC_ADDRESS_LENGTH 6
#define IPV4_ADDRESS_LENGTH 4
#define IPV6_ADDRESS_LENGTH 16
/* Core shall translate system condition into device state for PHL controller */
enum rtw_dev_state {
RTW_DEV_WORKING = BIT0,
RTW_DEV_SUSPENDING = BIT1,
RTW_DEV_RESUMING = BIT2,
RTW_DEV_SURPRISE_REMOVAL = BIT3,
RTW_DEV_IN_DFS_CAC_PERIOD = BIT4,
RTW_DEV_SHUTTING_DOWN = BIT5, /* set by core */
RTW_DEV_SUSPENDED = BIT6,
RTW_DEV_MAX
};
#define RTW_RATE_MODE_MASK (BIT(7) | BIT(8))
#define RTW_RATE_MODE_SHIFT 7
#define RTW_RATE_INDEX_MASK 0x007f
#define RTW_GET_RATE_MODE(_rtw_data_rate) (u16)((_rtw_data_rate & RTW_RATE_MODE_MASK) >> RTW_RATE_MODE_SHIFT)
#define RTW_GET_RATE_INDEX(_rtw_data_rate) (u16)(_rtw_data_rate & RTW_RATE_INDEX_MASK)
enum rtw_rate_mode {
RTW_LEGACY_MODE = 0,
RTW_HT_MODE = 1,
RTW_VHT_MODE = 2,
RTW_HE_MODE = 3
};
enum rtw_data_rate {
RTW_DATA_RATE_CCK1 = 0x0,
RTW_DATA_RATE_CCK2 = 0x1,
RTW_DATA_RATE_CCK5_5 = 0x2,
RTW_DATA_RATE_CCK11 = 0x3,
RTW_DATA_RATE_OFDM6 = 0x4,
RTW_DATA_RATE_OFDM9 = 0x5,
RTW_DATA_RATE_OFDM12 = 0x6,
RTW_DATA_RATE_OFDM18 = 0x7,
RTW_DATA_RATE_OFDM24 = 0x8,
RTW_DATA_RATE_OFDM36 = 0x9,
RTW_DATA_RATE_OFDM48 = 0xA,
RTW_DATA_RATE_OFDM54 = 0xB,
RTW_DATA_RATE_MCS0 = 0x80,
RTW_DATA_RATE_MCS1 = 0x81,
RTW_DATA_RATE_MCS2 = 0x82,
RTW_DATA_RATE_MCS3 = 0x83,
RTW_DATA_RATE_MCS4 = 0x84,
RTW_DATA_RATE_MCS5 = 0x85,
RTW_DATA_RATE_MCS6 = 0x86,
RTW_DATA_RATE_MCS7 = 0x87,
RTW_DATA_RATE_MCS8 = 0x88,
RTW_DATA_RATE_MCS9 = 0x89,
RTW_DATA_RATE_MCS10 = 0x8A,
RTW_DATA_RATE_MCS11 = 0x8B,
RTW_DATA_RATE_MCS12 = 0x8C,
RTW_DATA_RATE_MCS13 = 0x8D,
RTW_DATA_RATE_MCS14 = 0x8E,
RTW_DATA_RATE_MCS15 = 0x8F,
RTW_DATA_RATE_MCS16 = 0x90,
RTW_DATA_RATE_MCS17 = 0x91,
RTW_DATA_RATE_MCS18 = 0x92,
RTW_DATA_RATE_MCS19 = 0x93,
RTW_DATA_RATE_MCS20 = 0x94,
RTW_DATA_RATE_MCS21 = 0x95,
RTW_DATA_RATE_MCS22 = 0x96,
RTW_DATA_RATE_MCS23 = 0x97,
RTW_DATA_RATE_MCS24 = 0x98,
RTW_DATA_RATE_MCS25 = 0x99,
RTW_DATA_RATE_MCS26 = 0x9A,
RTW_DATA_RATE_MCS27 = 0x9B,
RTW_DATA_RATE_MCS28 = 0x9C,
RTW_DATA_RATE_MCS29 = 0x9D,
RTW_DATA_RATE_MCS30 = 0x9E,
RTW_DATA_RATE_MCS31 = 0x9F,
RTW_DATA_RATE_VHT_NSS1_MCS0 = 0x100,
RTW_DATA_RATE_VHT_NSS1_MCS1 = 0x101,
RTW_DATA_RATE_VHT_NSS1_MCS2 = 0x102,
RTW_DATA_RATE_VHT_NSS1_MCS3 = 0x103,
RTW_DATA_RATE_VHT_NSS1_MCS4 = 0x104,
RTW_DATA_RATE_VHT_NSS1_MCS5 = 0x105,
RTW_DATA_RATE_VHT_NSS1_MCS6 = 0x106,
RTW_DATA_RATE_VHT_NSS1_MCS7 = 0x107,
RTW_DATA_RATE_VHT_NSS1_MCS8 = 0x108,
RTW_DATA_RATE_VHT_NSS1_MCS9 = 0x109,
RTW_DATA_RATE_VHT_NSS2_MCS0 = 0x110,
RTW_DATA_RATE_VHT_NSS2_MCS1 = 0x111,
RTW_DATA_RATE_VHT_NSS2_MCS2 = 0x112,
RTW_DATA_RATE_VHT_NSS2_MCS3 = 0x113,
RTW_DATA_RATE_VHT_NSS2_MCS4 = 0x114,
RTW_DATA_RATE_VHT_NSS2_MCS5 = 0x115,
RTW_DATA_RATE_VHT_NSS2_MCS6 = 0x116,
RTW_DATA_RATE_VHT_NSS2_MCS7 = 0x117,
RTW_DATA_RATE_VHT_NSS2_MCS8 = 0x118,
RTW_DATA_RATE_VHT_NSS2_MCS9 = 0x119,
RTW_DATA_RATE_VHT_NSS3_MCS0 = 0x120,
RTW_DATA_RATE_VHT_NSS3_MCS1 = 0x121,
RTW_DATA_RATE_VHT_NSS3_MCS2 = 0x122,
RTW_DATA_RATE_VHT_NSS3_MCS3 = 0x123,
RTW_DATA_RATE_VHT_NSS3_MCS4 = 0x124,
RTW_DATA_RATE_VHT_NSS3_MCS5 = 0x125,
RTW_DATA_RATE_VHT_NSS3_MCS6 = 0x126,
RTW_DATA_RATE_VHT_NSS3_MCS7 = 0x127,
RTW_DATA_RATE_VHT_NSS3_MCS8 = 0x128,
RTW_DATA_RATE_VHT_NSS3_MCS9 = 0x129,
RTW_DATA_RATE_VHT_NSS4_MCS0 = 0x130,
RTW_DATA_RATE_VHT_NSS4_MCS1 = 0x131,
RTW_DATA_RATE_VHT_NSS4_MCS2 = 0x132,
RTW_DATA_RATE_VHT_NSS4_MCS3 = 0x133,
RTW_DATA_RATE_VHT_NSS4_MCS4 = 0x134,
RTW_DATA_RATE_VHT_NSS4_MCS5 = 0x135,
RTW_DATA_RATE_VHT_NSS4_MCS6 = 0x136,
RTW_DATA_RATE_VHT_NSS4_MCS7 = 0x137,
RTW_DATA_RATE_VHT_NSS4_MCS8 = 0x138,
RTW_DATA_RATE_VHT_NSS4_MCS9 = 0x139,
RTW_DATA_RATE_HE_NSS1_MCS0 = 0x180,
RTW_DATA_RATE_HE_NSS1_MCS1 = 0x181,
RTW_DATA_RATE_HE_NSS1_MCS2 = 0x182,
RTW_DATA_RATE_HE_NSS1_MCS3 = 0x183,
RTW_DATA_RATE_HE_NSS1_MCS4 = 0x184,
RTW_DATA_RATE_HE_NSS1_MCS5 = 0x185,
RTW_DATA_RATE_HE_NSS1_MCS6 = 0x186,
RTW_DATA_RATE_HE_NSS1_MCS7 = 0x187,
RTW_DATA_RATE_HE_NSS1_MCS8 = 0x188,
RTW_DATA_RATE_HE_NSS1_MCS9 = 0x189,
RTW_DATA_RATE_HE_NSS1_MCS10 = 0x18A,
RTW_DATA_RATE_HE_NSS1_MCS11 = 0x18B,
RTW_DATA_RATE_HE_NSS2_MCS0 = 0x190,
RTW_DATA_RATE_HE_NSS2_MCS1 = 0x191,
RTW_DATA_RATE_HE_NSS2_MCS2 = 0x192,
RTW_DATA_RATE_HE_NSS2_MCS3 = 0x193,
RTW_DATA_RATE_HE_NSS2_MCS4 = 0x194,
RTW_DATA_RATE_HE_NSS2_MCS5 = 0x195,
RTW_DATA_RATE_HE_NSS2_MCS6 = 0x196,
RTW_DATA_RATE_HE_NSS2_MCS7 = 0x197,
RTW_DATA_RATE_HE_NSS2_MCS8 = 0x198,
RTW_DATA_RATE_HE_NSS2_MCS9 = 0x199,
RTW_DATA_RATE_HE_NSS2_MCS10 = 0x19A,
RTW_DATA_RATE_HE_NSS2_MCS11 = 0x19B,
RTW_DATA_RATE_HE_NSS3_MCS0 = 0x1A0,
RTW_DATA_RATE_HE_NSS3_MCS1 = 0x1A1,
RTW_DATA_RATE_HE_NSS3_MCS2 = 0x1A2,
RTW_DATA_RATE_HE_NSS3_MCS3 = 0x1A3,
RTW_DATA_RATE_HE_NSS3_MCS4 = 0x1A4,
RTW_DATA_RATE_HE_NSS3_MCS5 = 0x1A5,
RTW_DATA_RATE_HE_NSS3_MCS6 = 0x1A6,
RTW_DATA_RATE_HE_NSS3_MCS7 = 0x1A7,
RTW_DATA_RATE_HE_NSS3_MCS8 = 0x1A8,
RTW_DATA_RATE_HE_NSS3_MCS9 = 0x1A9,
RTW_DATA_RATE_HE_NSS3_MCS10 = 0x1AA,
RTW_DATA_RATE_HE_NSS3_MCS11 = 0x1AB,
RTW_DATA_RATE_HE_NSS4_MCS0 = 0x1B0,
RTW_DATA_RATE_HE_NSS4_MCS1 = 0x1B1,
RTW_DATA_RATE_HE_NSS4_MCS2 = 0x1B2,
RTW_DATA_RATE_HE_NSS4_MCS3 = 0x1B3,
RTW_DATA_RATE_HE_NSS4_MCS4 = 0x1B4,
RTW_DATA_RATE_HE_NSS4_MCS5 = 0x1B5,
RTW_DATA_RATE_HE_NSS4_MCS6 = 0x1B6,
RTW_DATA_RATE_HE_NSS4_MCS7 = 0x1B7,
RTW_DATA_RATE_HE_NSS4_MCS8 = 0x1B8,
RTW_DATA_RATE_HE_NSS4_MCS9 = 0x1B9,
RTW_DATA_RATE_HE_NSS4_MCS10 = 0x1BA,
RTW_DATA_RATE_HE_NSS4_MCS11 = 0x1BB,
RTW_DATA_RATE_MAX = 0x1FF
};
enum rtw_gi_ltf {
RTW_GILTF_LGI_4XHE32 = 0,
RTW_GILTF_SGI_4XHE08 = 1,
RTW_GILTF_2XHE16 = 2,
RTW_GILTF_2XHE08 = 3,
RTW_GILTF_1XHE16 = 4,
RTW_GILTF_1XHE08 = 5,
RTW_GILTF_MAX
};
/* 11ax spec define for HE Trigger Frame, only used for HE Trigger Frame! */
enum rtw_gi_ltf_ul_tb {
RTW_TB_GILTF_1XHE16 = 0,
RTW_TB_GILTF_2XHE16 = 1,
RTW_TB_GILTF_4XHE32 = 2,
RTW_TB_GILTF_MAX
};
#define RTW_PHL_MAX_RF_PATH 4
enum rf_path {
RF_PATH_A = 0,
RF_PATH_B = 1,
RF_PATH_C = 2,
RF_PATH_D = 3,
RF_PATH_AB,
RF_PATH_AC,
RF_PATH_AD,
RF_PATH_BC,
RF_PATH_BD,
RF_PATH_CD,
RF_PATH_ABC,
RF_PATH_ABD,
RF_PATH_ACD,
RF_PATH_BCD,
RF_PATH_ABCD,
};
/*HW SPEC & SW/HW CAP*/
#define PROTO_CAP_11B BIT0
#define PROTO_CAP_11G BIT1
#define PROTO_CAP_11N BIT2
#define PROTO_CAP_11AC BIT3
#define PROTO_CAP_11AX BIT4
#define PROTO_CAP_BIT_NUM 4
enum wlan_mode {
WLAN_MD_INVALID = 0,
WLAN_MD_11B = BIT0,
WLAN_MD_11A = BIT1,
WLAN_MD_11G = BIT2,
WLAN_MD_11N = BIT3,
WLAN_MD_11AC = BIT4,
WLAN_MD_11AX = BIT5,
WLAN_MD_11BE = BIT6,
/* Type for current wireless mode */
WLAN_MD_11BG = (WLAN_MD_11B | WLAN_MD_11G),
WLAN_MD_11GN = (WLAN_MD_11G | WLAN_MD_11N),
WLAN_MD_11AN = (WLAN_MD_11A | WLAN_MD_11N),
WLAN_MD_11BN = (WLAN_MD_11B | WLAN_MD_11N),
WLAN_MD_11BGN = (WLAN_MD_11B | WLAN_MD_11G | WLAN_MD_11N),
WLAN_MD_11BGAC = (WLAN_MD_11B | WLAN_MD_11G | WLAN_MD_11AC),
WLAN_MD_11BGAX = (WLAN_MD_11B | WLAN_MD_11G | WLAN_MD_11AX),
WLAN_MD_11GAC = (WLAN_MD_11G | WLAN_MD_11AC),
WLAN_MD_11GAX = (WLAN_MD_11G | WLAN_MD_11AX),
WLAN_MD_11A_AC = (WLAN_MD_11A | WLAN_MD_11AC),
WLAN_MD_11A_AX = (WLAN_MD_11A | WLAN_MD_11AX),
/* Capability -Type for registry default wireless mode */
WLAN_MD_11AGN = (WLAN_MD_11A | WLAN_MD_11G | WLAN_MD_11N ),
WLAN_MD_11ABGN = (WLAN_MD_11A | WLAN_MD_11B | WLAN_MD_11G | WLAN_MD_11N ),
WLAN_MD_11ANAC = (WLAN_MD_11A | WLAN_MD_11N | WLAN_MD_11AC),
WLAN_MD_11BGNAC = (WLAN_MD_11B | WLAN_MD_11G | WLAN_MD_11N | WLAN_MD_11AC),
WLAN_MD_11GNAC = (WLAN_MD_11G | WLAN_MD_11N | WLAN_MD_11AC),
WLAN_MD_24G_MIX = (WLAN_MD_11B | WLAN_MD_11G | WLAN_MD_11N | WLAN_MD_11AC | WLAN_MD_11AX),
WLAN_MD_5G_MIX = (WLAN_MD_11A | WLAN_MD_11N | WLAN_MD_11AC | WLAN_MD_11AX),
WLAN_MD_6G_MIX = (WLAN_MD_11A | WLAN_MD_11AX),
WLAN_MD_MAX = (WLAN_MD_24G_MIX|WLAN_MD_5G_MIX),
};
enum band_type {
BAND_ON_24G = 0,
BAND_ON_5G = 1,
BAND_ON_6G = 2,
BAND_MAX,
};
/*HW SPEC & SW/HW CAP*/
#define BAND_CAP_2G BIT(BAND_ON_24G)
#define BAND_CAP_5G BIT(BAND_ON_5G)
#define BAND_CAP_6G BIT(BAND_ON_6G)
#define BAND_CAP_BIT_NUM 3
enum channel_width {
CHANNEL_WIDTH_20 = 0,
CHANNEL_WIDTH_40 = 1,
CHANNEL_WIDTH_80 = 2,
CHANNEL_WIDTH_160 = 3,
CHANNEL_WIDTH_320 = 4,
CHANNEL_WIDTH_80_80 = 5,
CHANNEL_WIDTH_5 = 6,
CHANNEL_WIDTH_10 = 7,
CHANNEL_WIDTH_MAX = 8,
};
/*HW SPEC & SW/HW CAP*/
#define BW_CAP_20M BIT(CHANNEL_WIDTH_20)
#define BW_CAP_40M BIT(CHANNEL_WIDTH_40)
#define BW_CAP_80M BIT(CHANNEL_WIDTH_80)
#define BW_CAP_160M BIT(CHANNEL_WIDTH_160)
#define BW_CAP_320M BIT(CHANNEL_WIDTH_320)
#define BW_CAP_80_80M BIT(CHANNEL_WIDTH_80_80)
#define BW_CAP_5M BIT(CHANNEL_WIDTH_5)
#define BW_CAP_10M BIT(CHANNEL_WIDTH_10)
#define BW_CAP_BIT_NUM 8
/*
* Represent Extention Channel Offset in HT Capabilities
* Secondary Channel Offset
* 0 -SCN, 1 -SCA, 2 -RSVD, 3 - SCB
*
*/
enum chan_offset {
CHAN_OFFSET_NO_EXT = 0, /*SCN - no secondary channel*/
CHAN_OFFSET_UPPER = 1, /*SCA - secondary channel above*/
CHAN_OFFSET_NO_DEF = 2, /*Reserved*/
CHAN_OFFSET_LOWER = 3, /*SCB - secondary channel below*/
CHAN_OFFSET_40M_UPPER = 4,
CHAN_OFFSET_40M_LOWER = 5,
CHAN_OFFSET_80M_UPPER = 6,
CHAN_OFFSET_80M_LOWER = 7,
};
enum rf_type {
RF_1T1R = 0,
RF_1T2R = 1,
RF_2T2R = 2,
RF_2T3R = 3,
RF_2T4R = 4,
RF_3T3R = 5,
RF_3T4R = 6,
RF_4T4R = 7,
RF_TYPE_MAX,
};
enum rtw_rf_state {
RTW_RF_ON,
RTW_RF_OFF,
RTW_RF_MAX
};
enum rtw_usb_speed {
RTW_USB_SPEED_LOW = 0, /*U2 (2.0)- 1.0 - 1.5 Mbps - 0.192MBs*/
RTW_USB_SPEED_FULL = 1, /*U2 (2.0)- 1.1 - 12 Mbps - 1.5MBs*/
RTW_USB_SPEED_HIGH = 2, /*U2 (2.0)- 2.1 - 480 Mbps - 60MBs*/
RTW_USB_SPEED_SUPER = 3, /*U3 (3.2 Gen 1)- 3.0 - 5 Gbps - 640MBs*/
RTW_USB_SPEED_SUPER_10G = 4, /*U3 (3.2 Gen 2)- 3.1 - 10 Gbps - 1280MBs*/
RTW_USB_SPEED_SUPER_20G = 5, /*U3 (3.2 Gen 2x2)- 3.2 - 20 Gbps - 2560MBs*/
/* keep last */
RTW_USB_SPEED_MAX,
RTW_USB_SPEED_UNKNOWN = RTW_USB_SPEED_MAX,
};
#define USB_SUPER_SPEED_BULK_SIZE 1024 /* usb 3.0 */
#define USB_HIGH_SPEED_BULK_SIZE 512 /* usb 2.0 */
#define USB_FULL_SPEED_BULK_SIZE 64 /* usb 1.1 */
#define IV_LENGTH 8
enum rtw_enc_algo {
RTW_ENC_NONE,
RTW_ENC_WEP40,
RTW_ENC_WEP104,
RTW_ENC_TKIP,
RTW_ENC_WAPI,
RTW_ENC_GCMSMS4,
RTW_ENC_CCMP,
RTW_ENC_CCMP256,
RTW_ENC_GCMP,
RTW_ENC_GCMP256,
RTW_ENC_BIP_CCMP128,
RTW_ENC_MAX
};
enum rtw_sec_ent_mode {
RTW_SEC_ENT_MODE_0, /* No key */
RTW_SEC_ENT_MODE_1, /* WEP */
RTW_SEC_ENT_MODE_2, /* 2 unicast + 3 multicast + 2 BIP keys */
RTW_SEC_ENT_MODE_3, /* 2 unicast + 4 multicast + 1 BIP keys */
};
enum rtw_sec_key_type {
RTW_SEC_KEY_UNICAST,
RTW_SEC_KEY_MULTICAST,
RTW_SEC_KEY_BIP,
RTW_SEC_KEY_MAX
};
/**
* Figure 27-7 + Table 9-31h from Ax Spec D4.2
* B7-B1:
* RU26 : 0 1 2 3 4 5 6 7 8 9 10 ... 36
* RU52 : 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
* RU106 : 53 54 55 56 57 58 59 60
* RU242 : 61 62 63 64
* RU484 : 65 66
* RU996 : 67
* RU996x2: 68
**/
enum rtw_he_ru_idx {
/* 20MHz - 1 */
RTW_HE_RU26_1 = 0,
RTW_HE_RU26_2,
RTW_HE_RU26_3,
RTW_HE_RU26_4,
RTW_HE_RU26_5,
RTW_HE_RU26_6,
RTW_HE_RU26_7,
RTW_HE_RU26_8,
RTW_HE_RU26_9,
/* 20MHz - 2 */
RTW_HE_RU26_10,
RTW_HE_RU26_11,
RTW_HE_RU26_12,
RTW_HE_RU26_13,
RTW_HE_RU26_14,
RTW_HE_RU26_15,
RTW_HE_RU26_16,
RTW_HE_RU26_17,
RTW_HE_RU26_18,
/* Center 26-tone */
RTW_HE_RU26_19,
/* 20MHz - 3 */
RTW_HE_RU26_20,
RTW_HE_RU26_21,
RTW_HE_RU26_22,
RTW_HE_RU26_23,
RTW_HE_RU26_24,
RTW_HE_RU26_25,
RTW_HE_RU26_26,
RTW_HE_RU26_27,
RTW_HE_RU26_28,
/* 20MHz - 4 */
RTW_HE_RU26_29,
RTW_HE_RU26_30,
RTW_HE_RU26_31,
RTW_HE_RU26_32,
RTW_HE_RU26_33,
RTW_HE_RU26_34,
RTW_HE_RU26_35,
RTW_HE_RU26_36,
RTW_HE_RU26_37 = 36,
/* 20MHz - 1 */
RTW_HE_RU52_1 = 37,
RTW_HE_RU52_2,
RTW_HE_RU52_3,
RTW_HE_RU52_4,
/* 20MHz - 2 */
RTW_HE_RU52_5,
RTW_HE_RU52_6,
RTW_HE_RU52_7,
RTW_HE_RU52_8,
/* 20MHz - 3 */
RTW_HE_RU52_9,
RTW_HE_RU52_10,
RTW_HE_RU52_11,
RTW_HE_RU52_12,
/* 20MHz - 4 */
RTW_HE_RU52_13,
RTW_HE_RU52_14,
RTW_HE_RU52_15,
RTW_HE_RU52_16 = 52,
/* 20MHz - 1 */
RTW_HE_RU106_1 = 53,
RTW_HE_RU106_2,
/* 20MHz - 2 */
RTW_HE_RU106_3,
RTW_HE_RU106_4,
/* 20MHz - 3 */
RTW_HE_RU106_5,
RTW_HE_RU106_6,
/* 20MHz - 4 */
RTW_HE_RU106_7,
RTW_HE_RU106_8 = 60,
/* 20MHz */
RTW_HE_RU242_1 = 61,
RTW_HE_RU242_2,
RTW_HE_RU242_3,
RTW_HE_RU242_4 = 64,
/* 40MHz */
RTW_HE_RU484_1 = 65,
RTW_HE_RU484_2 = 66,
/* 80MHz */
RTW_HE_RU996_1 = 67,
/* 160MHz */
RTW_HE_RU2x996_1 = 68,
};
enum rtw_protect_mode {
RTW_PROTECT_DISABLE = 0,
RTW_PROTECT_RTS = 1,
RTW_PROTECT_CTS2SELF = 2,
RTW_PROTECT_HW_RTS = 3
};
enum rtw_ac {
RTW_AC_BE = 0,
RTW_AC_BK = 1,
RTW_AC_VI = 2,
RTW_AC_VO = 3,
RTW_AC_MAX
};
enum rtw_edcca_mode {
RTW_EDCCA_NORMAL,
RTW_EDCCA_ETSI,
RTW_EDCCA_JP,
RTW_EDCCA_FCC,
RTW_EDCCA_MAX
};
enum rtw_mac_pwr_st {
RTW_MAC_PWR_NONE = 0,
RTW_MAC_PWR_OFF = 1,
RTW_MAC_PWR_ON = 2,
RTW_MAC_PWR_LPS = 3,
RTW_MAC_PWR_MAX = 0x4
};
enum rtw_pcie_bus_func_cap_t {
RTW_PCIE_BUS_FUNC_DISABLE = 0,
RTW_PCIE_BUS_FUNC_ENABLE = 1,
RTW_PCIE_BUS_FUNC_DEFAULT = 2,
RTW_PCIE_BUS_FUNC_IGNORE = 3
};
/* follow mac's definetion, mac_ax_sw_io_mode*/
enum rtw_gpio_mode {
RTW_AX_SW_IO_MODE_INPUT,
RTW_AX_SW_IO_MODE_OUTPUT_OD,
RTW_AX_SW_IO_MODE_OUTPUT_PP,
RTW_AX_SW_IO_MODE_MAX
};
enum rtw_p2p_app_type {
RTW_P2P_APP_NONE = 0,
RTW_P2P_APP_UNKNOWN = 1,
RTW_P2P_APP_GC = 2,
RTW_P2P_APP_GO_HOTSPOT =3,
RTW_P2P_APP_GO_SRC = 4,
RTW_P2P_APP_GO_SINK = 5,
RTW_P2P_APP_GO_SRC_SINK = 6,
RTW_P2P_SESSION_MAX
};
/*MAC_AX_PCIE_L0SDLY_IGNORE = 0xFF, MAC_AX_PCIE_L1DLY_IGNORE = 0xFF, MAC_AX_PCIE_CLKDLY_IGNORE = 0xFF */
#define RTW_PCIE_BUS_ASPM_DLY_IGNORE 0xFF /* Fully controlled by HW */
#define RTW_FRAME_TYPE_MGNT 0
#define RTW_FRAME_TYPE_CTRL 1
#define RTW_FRAME_TYPE_DATA 2
#define RTW_FRAME_TYPE_EXT_RSVD 3
/* Association Related PKT Type + SubType */
#define FRAME_OFFSET_FRAME_CONTROL 0
#define FRAME_OFFSET_DURATION 2
#define FRAME_OFFSET_ADDRESS1 4
#define FRAME_OFFSET_ADDRESS2 10
#define FRAME_OFFSET_ADDRESS3 16
#define FRAME_OFFSET_SEQUENCE 22
#define FRAME_OFFSET_ADDRESS4 24
#define PHL_GET_80211_HDR_TYPE(_hdr) LE_BITS_TO_2BYTE((u8 *)_hdr, 2, 6)
#define PHL_GET_80211_HDR_MORE_FRAG(_hdr) LE_BITS_TO_2BYTE((u8 *)_hdr, 10, 1)
#define PHL_GET_80211_HDR_RETRY(_hdr) LE_BITS_TO_2BYTE((u8 *)_hdr, 11, 1)
#define PHL_GET_80211_HDR_FRAG_NUM(_hdr) LE_BITS_TO_2BYTE((u8 *)_hdr + 22, 0, 4)
#define PHL_GET_80211_HDR_SEQUENCE(_hdr) LE_BITS_TO_2BYTE((u8 *)_hdr + 22, 4, 12)
#define PHL_GET_80211_HDR_ADDRESS2(_d, _hdr, _val) \
_os_mem_cpy(_d, (u8 *)_val, (u8 *)_hdr + FRAME_OFFSET_ADDRESS2, 6)
#define PHL_GET_80211_HDR_ADDRESS3(_d, _hdr, _val) \
_os_mem_cpy(_d, (u8 *)_val, (u8 *)_hdr + FRAME_OFFSET_ADDRESS3, 6)
#define RTW_FRAME_TYPE_BEACON 32
#define RTW_FRAME_TYPE_PROBE_RESP 20
#define RTW_FRAME_TYPE_ASOC_REQ 0
#define RTW_FRAME_TYPE_ASOC_RESP 4
#define RTW_FRAME_TYPE_REASOC_REQ 8
#define RTW_FRAME_TYPE_REASOC_RESP 12
#define RTW_FRAME_TYPE_ACK 53
#define RTW_FRAME_TYPE_MAX 0xFF
#define RTW_IS_ASOC_PKT(_TYPE) \
((_TYPE == RTW_FRAME_TYPE_REASOC_RESP) || \
(_TYPE == RTW_FRAME_TYPE_REASOC_REQ) || \
(_TYPE == RTW_FRAME_TYPE_ASOC_RESP) || \
(_TYPE == RTW_FRAME_TYPE_ASOC_REQ)) ? true : false
#define RTW_IS_ASOC_REQ_PKT(_TYPE) \
((_TYPE == RTW_FRAME_TYPE_REASOC_REQ) || \
(_TYPE == RTW_FRAME_TYPE_ASOC_REQ)) ? true : false
#define RTW_IS_BEACON_OR_PROBE_RESP_PKT(_TYPE) \
((_TYPE == RTW_FRAME_TYPE_BEACON) || \
(_TYPE == RTW_FRAME_TYPE_PROBE_RESP)) ? true : false
#define TU 1024 /* Time Unit (TU): 1024 us*/
#define RTW_MAX_ETH_PKT_LEN 1536
#define WL_SEQ_MASK 0xfff /* PHL_RXSC_AMPDU */
#define RX_DESC_PPDU_T_LCCK 0
#define RX_DESC_PPDU_T_SCCK 1
#define RX_DESC_PPDU_T_OFDM 2
#define RX_DESC_PPDU_T_HT 3
#define RX_DESC_PPDU_T_HTGF 4
#define RX_DESC_PPDU_T_VHT_SU 5
#define RX_DESC_PPDU_T_VHT_MU 6
#define RX_DESC_PPDU_T_HE_SU 7
#define RX_DESC_PPDU_T_HE_ERSU 8
#define RX_DESC_PPDU_T_HE_MU 9
#define RX_DESC_PPDU_T_HE_TB 10
#define RX_DESC_PPDU_T_UNKNOWN 15
#endif /*_RTW_GENERAL_DEF_H_*/
3rd/devourer/hal/halbb/g6/vendor/halbb.h
Vendored
+666
View File
@@ -0,0 +1,666 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_H__
#define __HALBB_H__
/*@--------------------------[Define] ---------------------------------------*/
#define ACTIVE_TP_THRESHOLD 1
#define BB_WATCH_DOG_PERIOD 2 /*sec*/
#define is_sta_active(sta) ((sta) && (sta->active))
#define HALBB_SNPRINT_SIZE 200
#define HALBB_SNPRINT_SIZE_S 20
#define BB_EFUSE_BAND_NUM 5
#define IC_LNA_NUM 7
#define IC_TIA_NUM 2
#define IC_LNA_OP1DB_NUM 7
#define IC_TIA_LNA_OP1DB_NUM 8
#define EFUSE_OFST_NUM 1
#define WB_GIDX_ELNA_NUM 16
#define GS_IDX_NUM 2
#define G_ELNA_NUM 2
/*@--------------------------[Enum]------------------------------------------*/
enum bb_trx_state_t {
BB_TX_STATE = 0,
BB_RX_STATE = 1,
BB_BI_DIR_STATE = 2
};
enum bb_trafic_t {
TRAFFIC_NO_TP = 0,
TRAFFIC_ULTRA_LOW = 1,
TRAFFIC_LOW = 2,
TRAFFIC_MID = 3,
TRAFFIC_HIGH = 4
};
enum efuse_bit_mask {
LOW_MASK = 0,
HIGH_MASK = 1
};
/*For 2G/5G/6G*/
enum mcc_band {
MCC_BAND_1 = 0,
MCC_BAND_2,
MCC_BAND_NUM
};
enum mr_band {
MR_BAND_1 = 0,
MR_BAND_2 = 1,
MR_BAND_3 = 2,
MR_BAND_NUM
};
enum bb_mcc_t {
BB_MCC_DISABLE = 0,
BB_MCC_ENABLE = 1,
BB_MCC_INVALID
};
enum halbb_mcc_reg {
SEG0R_PD_LOWER_BOUND = 0,
NUM_MAX_REG_CNT
};
enum halbb_mr_err_code{
BB_MRDM_DISABLE = 0,
BB_MRDM_REG_OVERFLOW = 1,
BB_MRDM_CLR_CH = 2,
BB_MRDM_SEARCH_CH_FAIL = 3,
BB_MRDM_ONE_CH_ONLY = 4,
BB_MRDM_SWITCH_CR = 5,
BB_MRDM_START = 6,
BB_MRDM_ERR_MAX
};
/*@--------------------------[Structure]-------------------------------------*/
struct halbb_pause_lv {
s8 lv_fa_cnt;
s8 lv_dig;
s8 lv_env_mntr;
s8 lv_cfo;
s8 lv_edcca;
s8 lv_path_div;
s8 lv_ant_div;
};
struct bb_func_hooker_info {
void (*pause_bb_dm_handler)(struct bb_info *bb, u32 *val_buf, u8 val_len);
};
struct bb_iot_info {
u8 is_linked_cmw500:1;
u8 patch_id_00000000:1;
u8 rsvd:6;
};
struct bb_path_info {
/*[Path info]*/
u8 tx_path_en; /*TX path enable*/
u8 rx_path_en; /*RX path enable*/
#ifdef HALBB_COMPILE_ABOVE_4SS
enum bb_path tx_4ss_path_map; /*@Use N-X for 4STS rate*/
#endif
#ifdef HALBB_COMPILE_ABOVE_3SS
enum bb_path tx_3ss_path_map; /*@Use N-X for 3STS rate*/
#endif
#ifdef HALBB_COMPILE_ABOVE_2SS
enum bb_path tx_2ss_path_map; /*@Use N-X for 2STS rate*/
#endif
enum bb_path tx_1ss_path_map; /*@Use N-X for 1STS rate*/
};
struct bb_link_info {
/*[Link Info]*/
bool is_linked;
bool is_linked_pre;
bool first_connect;
bool first_disconnect;
enum bb_trx_state_t txrx_state_all;
enum bb_bw_type bb_bw;
/*[One Entry TP Info]*/
bool is_one_entry_only;
u32 one_entry_macid;
u32 first_entry_macid;
u32 one_entry_tp;
u32 one_entry_tp_pre;
u16 tp_active_th;
bool one_entry_tp_active_occur;
bool is_match_bssid;
/*[Client Number]*/
u8 num_linked_client;
u8 num_linked_client_pre;
u8 num_active_client;
u8 num_active_client_pre;
/*[TP & Traffic]*/
u8 traffic_load;
u8 traffic_load_pre;
u16 tx_rate; /*from the first sta*/
u16 rx_rate_plurality;
u16 rx_rate_plurality_mu;
u16 rx_utility;
u16 tx_utility;
u16 avg_phy_rate; /*Rx avg phy rate*/
u16 tx_avg_phy_rate; /*Tx avg phy rate*/
u32 tx_tp; /*@Mbps*/
u32 rx_tp; /*@Mbps*/
u32 total_tp; /*@Mbps*/
u16 consecutive_idle_time; /*@unit: second*/
u16 wlan_mode_bitmap; /*enum wlan_mode*/
/*[at least one macid BFer & BFee chk]*/
bool at_least_one_bfer; /*at least one macid Tx BFer*/
bool at_least_one_bfee; /*at least one macid Rx BFee*/
};
struct bb_ch_info {
u8 fc_ch_idx;
bool is_2g;
u8 rssi_min; /*U(8.1), external rssi (from antenna)*/
u16 rssi_min_macid;
u8 pre_rssi_min;
u8 rssi_max; /*U(8.1), external rssi (from antenna)*/
u16 rssi_max_macid;
u8 rxsc_160;
u8 rxsc_80;
u8 rxsc_40;
u8 rxsc_20;
u8 rxsc_l;
u8 is_noisy;
u8 rf_central_ch_cfg; /*report in phy-sts*/
s8 ext_loss[HALBB_MAX_PATH]; /*S(8.2), update when switching ch*/
s8 ext_loss_avg; /*S(8.2), update when switching ch*/
u8 int_rssi_min; /*U(8.1), internal rssi (from ADC output) = external rssi - ext_loss*/
u8 int_rssi_max; /*U(8.1), internal rssi (from ADC output) = external rssi - ext_loss*/
u8 drv_op_ch[MR_BAND_NUM];
u8 drv_op_bw[MR_BAND_NUM];
u8 drv_op_band[MR_BAND_NUM];
};
struct bb_cmn_backup_info {
u8 cur_tx_path;
u8 cur_rx_path;
s16 cur_tx_pwr;
u8 cur_pd_lower_bound;
u8 last_rpl;
u32 last_rssi;
u16 last_cfo;
s32 cck_ps_th_bk;
s32 cck_rssi_ofst_bk;
s32 cck_sbd_th_bk;
u32 cur_rfmode_a_12ac;
u32 cur_rfmode_a_12b0;
u32 cur_rfmode_b_32ac;
u32 cur_rfmode_b_32b0;
struct rssi_physts last_rssi_rpt;
struct rxevm_physts last_rxevm_rpt;
};
struct bb_gain_info {
s8 lna_gain[BB_GAIN_BAND_NUM][HALBB_MAX_PATH][IC_LNA_NUM];
s8 tia_gain[BB_GAIN_BAND_NUM][HALBB_MAX_PATH][IC_TIA_NUM];
s8 lna_gain_bypass[BB_GAIN_BAND_NUM][HALBB_MAX_PATH][IC_LNA_NUM];
s8 lna_op1db[BB_GAIN_BAND_NUM][HALBB_MAX_PATH][IC_LNA_NUM];
s8 tia_lna_op1db[BB_GAIN_BAND_NUM][HALBB_MAX_PATH][IC_LNA_NUM + 1]; // TIA0_LNA0~6 + TIA1_LNA6
s8 efuse_ofst[BB_GAIN_BAND_NUM][HALBB_MAX_PATH][EFUSE_OFST_NUM];
s8 rpl_ofst_20[BB_GAIN_BAND_NUM][HALBB_MAX_PATH];
s8 rpl_ofst_40[BB_GAIN_BAND_NUM][HALBB_MAX_PATH][BB_RXSC_NUM_40];
s8 rpl_ofst_80[BB_GAIN_BAND_NUM][HALBB_MAX_PATH][BB_RXSC_NUM_80];
s8 rpl_ofst_160[BB_GAIN_BAND_NUM][HALBB_MAX_PATH][BB_RXSC_NUM_160];
u32 wb_gidx_elna[BB_GAIN_BAND_NUM][HALBB_MAX_PATH]; // {bit(15) ~ bit(0)}: {wb_gidx_15_elna ~ wb_gidx_0_elna}
u8 wb_gidx_lna_tia[BB_GAIN_BAND_NUM][HALBB_MAX_PATH][WB_GIDX_ELNA_NUM];
u32 gs_idx[BB_GAIN_BAND_NUM][HALBB_MAX_PATH][GS_IDX_NUM];
u8 g_elna[BB_GAIN_BAND_NUM][HALBB_MAX_PATH][G_ELNA_NUM];
};
struct bb_efuse_info{
bool normal_efuse_check;
bool hidden_efuse_check;
s8 gain_offset[HALBB_MAX_PATH][BB_BAND_NUM_MAX + 1]; // S(8,0)
s8 gain_cs[HALBB_MAX_PATH][BB_BAND_NUM_MAX]; // S(8,0)
s8 gain_cg[HALBB_MAX_PATH][BB_BAND_NUM_MAX]; // S(8,0)
s8 hidden_efuse[BB_HIDE_EFUSE_SIZE];
s8 lna_err_2g[HALBB_MAX_PATH][7]; // S(6,2)
s8 lna_err_5g[HALBB_MAX_PATH][7]; // S(6,2)
s8 frontend_loss[HALBB_MAX_PATH];
s8 rpl_bias_comp[HALBB_MAX_PATH];
s8 rssi_bias_comp[HALBB_MAX_PATH];
s8 efuse_ofst[HW_PHY_MAX]; // 8852A:S(5,2) 8852B:S(8,4)
s8 efuse_ofst_path[HALBB_MAX_PATH]; // 8852C: S(8,4)
s8 efuse_ofst_tb[HW_PHY_MAX]; // 8852A:S(7,4) 8852B:S(8,4)
s8 efuse_ofst_tb_path[HALBB_MAX_PATH]; // 8852C: S(8,4)
s8 rpl_ofst_cck; // 8852D: S(8,0)
u8 efuse_ft; // 8192XB: U(8,0)
u8 efuse_adc_td; // 8192XB: U(2,0)
s8 cck_rpl_ofst_ref;
};
struct vht_mu_cr_backup_table {
u32 muic_en_a;
u32 lpbw_sw_symb0_a;
u32 ch_tracking_symb0_a;
u32 lpbw_sel_d1_a;
u32 ch_tracking_symb1_a;
u32 ch_tracking_a1_a;
u32 lpbw_sel_p1_a;
u32 noise_tracking_en_a;
};
struct bb_cmn_dbg_info {
bool cmn_log_2_cnsl_en;
bool cmn_log_2_drv_statistic_en;
};
struct bb_cmn_info {
enum wlan_mode wlan_mode_max;
u8 bb_dm_number;
bool cck_blk_en;
enum phl_phy_idx cck_phy_map;
bool bb_dbcc_en;
bool ic_dual_phy_support;
bool ic_dbcc_support;
bool lbk_verify_en;
bool watchdog_io_saving_en;
bool scan_in_drv;
enum halbb_drv_type bb_drv_type;
#ifdef HALBB_COMPILE_IC_DBCC_MLO
enum mlo_dbcc_mode_type bb_mlo_dbcc_mode_t;
#endif
#ifdef HALBB_RA_SUPPORT
struct bb_ra_info bb_ra_i[PHL_MAX_STA_NUM];
struct bb_ra_drv_info bb_ra_drv_i;
struct bb_ra_dbg_info bb_ra_dbg_i;
#endif
#ifdef HALBB_PSD_SUPPORT
struct bb_psd_info bb_psd_i;
#endif
#ifdef HALBB_LA_MODE_SUPPORT
struct bb_la_mode_info bb_la_mode_i;
#endif
#ifdef HALBB_SNIF_SUPPORT
struct bb_snif_info bb_snif_i;
#endif
#ifdef HALBB_DYN_CSI_RSP_SUPPORT
struct bf_ch_raw_info bf_ch_raw_i;
#endif
struct bb_spur_info bb_spur_i;
struct bb_echo_cmd_info bb_echo_cmd_i;
struct bb_func_hooker_info bb_func_hooker_i;
struct bb_cmn_dbg_info bb_cmn_dbg_i;
#ifdef HALBB_FW_OFLD_SUPPORT
u8 bbcr_fwofld_state;
bool skip_io_init_en;
bool is_io_ofld_success;
#endif
bool bb_fwofld_in_progress;
u32 bb_fwofld_sup_bitmap; /*enum fw_ofld_type.For HALBB to control DBCC-OFLD manully*/
u32 bb_fwofld_start_time;
struct bb_dbg_cr_info bb_dbg_cr_i;
struct bb_physts_cr_info bb_physts_cr_i;
#ifdef HALBB_STATISTICS_SUPPORT
struct bb_stat_cr_info bb_stat_cr_i;
#endif
#ifdef HALBB_DIG_SUPPORT
struct bb_dig_cr_info bb_dig_cr_i;
#endif
#ifdef HALBB_ENV_MNTR_SUPPORT
struct bb_env_mntr_cr_info bb_env_mntr_cr_i;
#endif
#ifdef HALBB_EDCCA_SUPPORT
struct bb_edcca_cr_info bb_edcca_cr_i;
#endif
#ifdef HALBB_DFS_SUPPORT
struct bb_dfs_cr_info bb_dfs_cr_i;
#endif
#ifdef HALBB_ANT_DIV_SUPPORT
struct bb_antdiv_cr_info bb_antdiv_cr_i;
#endif
#ifdef HALBB_PMAC_TX_SUPPORT
struct bb_plcp_cr_info bb_plcp_cr_i;
#endif
struct bb_rpt_info bb_rpt_i;
#ifdef HALBB_CH_INFO_SUPPORT
struct bb_ch_info_cr_info bb_ch_info_cr_i; /*CR callback table*/
#endif
#ifdef HALBB_CFO_TRK_SUPPORT
struct bb_cfo_trk_cr_info bb_cfo_trk_cr_i;
#endif
#ifdef HALBB_UL_TB_CTRL_SUPPORT
struct bb_ul_tb_cr_info bb_ul_tb_cr_i;
#endif
#ifdef HALBB_SR_SUPPORT
struct bb_spatial_reuse_cr_info bb_spatial_reuse_cr_i;
#endif
#ifdef HALBB_SNIF_SUPPORT
struct bb_snif_cr_info bb_snif_cr_i;
#endif
struct bb_hw_cfg_cr_info bb_hw_cfg_cr_i;
};
#define PD_IDX_MIN 0
#define INVALID_INIT_VAL 0xff
#ifdef HALBB_MCC_SUPPORT
struct halbb_mcc_dm {
enum bb_mcc_t mcc_pre_status_en;
u8 mcc_reg_id[NUM_MAX_REG_CNT];
u8 sta_cnt[MR_BAND_NUM];
u16 mcc_dm_reg[NUM_MAX_REG_CNT];
u16 mcc_dm_mask[NUM_MAX_REG_CNT];
u16 mcc_dm_val[NUM_MAX_REG_CNT][MR_BAND_NUM];
/*mcc DIG*/
u8 rssi_min[MR_BAND_NUM];
/* need to be config by driver*/
enum bb_mcc_t mcc_status_en;
u8 mr_num;
u8 softap_macid;
struct rtw_chan_def mcc_rf_ch[MR_BAND_NUM];
};
/**
* @struct _mcc_h2c_
* @brief _mcc_h2c_
*
*/
struct mcc_h2c_reg_content {
// MCCDM
u8 addr_lsb;
u8 addr_msb;
u8 bmask_lsb;
u8 bmask_msb;
u8 val_lsb;
u8 val_msb;
u8 rsvd0;
u8 rsvd1;
};
#if PLATFOM_IS_LITTLE_ENDIAN
struct mcc_h2c {
// MCCDM
u8 reg_cnt;
u8 mcc_dm_en: 1;
u8 mcc_idx: 2;
u8 mcc_set: 1;
u8 phy0_en: 1;
u8 phy1_en: 1;
u8 rsvd0: 2;
u8 center_ch;
u8 band_type;
struct mcc_h2c_reg_content mcc_reg_content[NUM_MAX_REG_CNT];
};
#else
struct mcc_h2c {
// MCCDM
u8 reg_cnt;
u8 rsvd0: 2;
u8 phy1_en: 1;
u8 phy0_en: 1;
u8 mcc_set: 1;
u8 mcc_idx: 2;
u8 mcc_dm_en: 1;
u8 center_ch;
u8 band_type;
struct mcc_h2c_reg_content mcc_reg_content[NUM_MAX_REG_CNT];
};
#endif
#endif
struct bb_scan_h2c_info {
u8 scan_mode;
u8 op_ch_band;
u8 op_ch;
u8 scan_ofdm_pd;
u8 op_ch_ofdm_pd;
u8 op_ch_idx;
u8 phy_idx;
u8 scan_cck_pd;
u8 op_ch_cck_pd;
u8 rsvd0;
u8 rsvd1;
u8 rsvd2;
};
struct bb_scan_c2h_rpt {
u8 phy_idx;
u8 band;
u8 center_ch;
u8 ofdm_pd_idx;
u8 cck_pd_idx;
u8 rsvd0;
u8 rsvd1;
u8 rsvd2;
};
struct bb_info {
struct rtw_phl_com_t *phl_com;
struct rtw_hal_com_t *hal_com;
struct rtw_phl_stainfo_t *phl_sta_info[PHL_MAX_STA_NUM];
u16 phl2bb_macid_table[PHL_MAX_STA_NUM];
bool sta_exist[PHL_MAX_STA_NUM];
/*[DBCC]*/
#ifdef HALBB_DBCC_SUPPORT
struct bb_info *bb_phy_hooker;
#endif
enum phl_phy_idx bb_phy_idx;
struct bb_cmn_info *bb_cmn_hooker;
/*[Common Info]*/
u32 bb0_cr_offset;
u32 bb0_mcu_cr_offset;
struct bb_gain_info bb_gain_i;
struct bb_gain_gen2_info bb_gain_gen2_i;
struct bb_efuse_info bb_efuse_i;
enum bb_ic_t ic_type;
enum bb_ic_sub_t ic_sub_type;
u32 a_die_id;
u32 a_die_cv;
u8 a_die_num;
enum bb_cr_t cr_type;
enum bb_80211spec_t bb_80211spec;
u8 num_ss; /*SS*/
u8 num_rf_path; /*STS*/
u8 num_tx_path; /*MAX TX PATH*/
u16 bb_sta_cnt;
/*[System Info]*/
bool is_mp_mode_pre;
enum bb_watchdog_mode_t bb_watchdog_mode;
bool bb_cmn_info_init_ready;
bool bb_dm_init_ready;
u32 bb_sys_up_time;
bool bb_watchdog_en;
u8 bb_watchdog_period; /*2s, 4s, 8s...,254s*/
bool bb_ic_api_en;
u8 pre_dbg_priority;
char dbg_buf[HALBB_SNPRINT_SIZE];
/*[DM Info]*/
bool is_noisy;
bool adv_bb_dm_en;
u64 support_ability; /*HALBB function Supportability*/
u64 manual_support_ability;
u32 pause_ability; /*HALBB function pause Supportability*/
struct halbb_pause_lv pause_lv_table;
/*[FW Info]*/
u8 fwofld_last_cmd;
u64 fw_dbg_component;
/*[Drv Dbg Info]*/
u64 dbg_component;
u64 mcu_dbg_component;
u8 cmn_dbg_msg_period;
u16 cmn_dbg_msg_component;
u8 cmn_dbg_msg_cnt;
bool is_disable_phy_api;
/*[Dummy]*/
bool bool_dummy;
u8 u8_dummy;
u16 u16_dummy;
u32 u32_dummy;
/*[Link Info]*/
enum rf_path tx_path; /*PMAC Tx Path*/
enum rf_path rx_path;
/*[pmac]*/
bool dyn_pmac_tri_en;
bool pmac_tri_en;
bool pwr_comp_en;
u32 pmac_tri_idx;
u32 pmac_pwr_ofst;
/*[btc]*/
bool bt_en; /*bt_en=1 when is_share_ant=0 and is_2g, backup for ch_bw switch*/
/*[Ch_Trk WR]*/
bool pre_ch_trk_state;
/*[npath enable]*/
bool npath_en;
/*@=== [HALBB Structure] ============================================*/
struct bb_hw_cfg_info bb_hw_cfg_i;
#ifdef BB_8852A_2_SUPPORT
struct bb_8852a_2_info bb_8852a_2_i;
struct bb_h2c_fw_cmw bb_fw_cmw_i;
struct vht_mu_cr_backup_table vht_mu_backup_val;
#endif
#ifdef HALBB_DBCC_SUPPORT
struct bb_dbcc_info bb_dbcc_i;
#endif
#ifdef HALBB_ENV_MNTR_SUPPORT
struct bb_env_mntr_info bb_env_mntr_i;
#endif
#ifdef HALBB_EDCCA_SUPPORT
struct bb_edcca_info bb_edcca_i;
#endif
#ifdef HALBB_DFS_SUPPORT
struct bb_dfs_info bb_dfs_i;
#endif
#ifdef HALBB_STATISTICS_SUPPORT
struct bb_stat_info bb_stat_i;
#endif
#ifdef HALBB_DIG_SUPPORT
struct bb_dig_info bb_dig_i;
#endif
#ifdef HALBB_CFO_TRK_SUPPORT
struct bb_cfo_trk_info bb_cfo_trk_i;
#endif
#ifdef HALBB_UL_TB_CTRL_SUPPORT
struct bb_ul_tb_info bb_ul_tb_i;
#endif
#ifdef HALBB_PHYSTS_PARSING_SUPPORT
struct bb_physts_info bb_physts_i;
struct bb_rxd_info bb_rxd_i;
#endif
#ifdef HALBB_LA_MODE_SUPPORT
struct bb_la_mode_info bb_la_mode_i;
#endif
#ifdef HALBB_PWR_CTRL_SUPPORT
struct bb_pwr_ctrl_info bb_pwr_ctrl_i;
struct bb_dyncca_info bb_dyncca_i;
#endif
#ifdef HALBB_PMAC_TX_SUPPORT
struct bb_plcp_info bb_plcp_i;
#endif
struct bb_link_info bb_link_i;
struct bb_path_info bb_path_i;
struct bb_ch_info bb_ch_i;
struct bb_api_info bb_api_i;
struct bb_iot_info bb_iot_i;
struct bb_dbg_info bb_dbg_i;
struct bb_c2h_fw_tx_rpt bb_fwtx_c2h_i;
struct bb_h2c_fw_tx_setting bb_fwtx_h2c_i;
struct bb_h2c_fw_edcca bb_fw_edcca_i;
struct bb_h2c_ehtsig_sigb bb_h2c_ehtsig_sigb_i;
struct bb_fw_dbg_cmn_info bb_fwdbg_i;
struct bb_cmn_rpt_info bb_cmn_rpt_i;
struct bb_ra_tx_hist_c2h_rpt bb_tx_hist_rpt_i;
struct rxevm_physts rxevm;
struct bb_cmn_backup_info bb_cmn_backup_i;
struct bb_spur_info bb_spur_i;
#ifdef HALBB_CH_INFO_SUPPORT
struct bb_ch_rpt_info bb_ch_rpt_i;
#endif
#ifdef HALBB_AUTO_DBG_SUPPORT
struct bb_auto_dbg_info bb_auto_dbg_i;
#endif
#ifdef HALBB_ANT_DIV_SUPPORT
struct bb_antdiv_info bb_ant_div_i;
#endif
#ifdef HALBB_DYN_L2H_SUPPORT
struct bb_dyn_l2h_info bb_dyn_l2h_i;
#endif
#ifdef HALBB_PATH_DIV_SUPPORT
struct bb_pathdiv_info bb_path_div_i;
#endif
#ifdef HALBB_SR_SUPPORT
struct bb_spatial_reuse_info bb_sr_i;
#endif
/*@=== [HALBB Timer] ================================================*/
#ifdef HALBB_RUA_SUPPORT
/*struct rtw_rua_tbl rtw_rua_t;*/
#endif
#ifdef HALBB_MCC_SUPPORT
struct halbb_mcc_dm mcc_dm;
#endif
#ifdef HALBB_DYN_1R_CCA_SUPPORT
struct bb_dyn_1r_cca_info bb_dyn_1r_cca_i;
#endif
#ifdef HALBB_DYN_DTR_SUPPORT
struct bb_dyn_dtr_info bb_dyn_dtr_i;
#endif
#ifdef HALBB_FW_OFLD_SUPPORT
enum phl_msg_evt_id bb_phl_evt;
#endif
#ifdef HALBB_DV_PXP_DBG_SUPPORT
struct bb_dv_pxp_dbg_info bb_dv_pxp_dbg_i;
#endif
struct halbb_plcp_info plcp_in;
struct halbb_pmac_info pmac_in;
struct halbb_lbk_info bb_lbk_i;
struct bb_scan_h2c_info bb_scan_h2c_i;
};
/*@--------------------------[Prptotype]-------------------------------------*/
u8 halbb_get_rssi_min(struct bb_info *bb);
void halbb_cmn_info_self_reset(struct bb_info *bb);
void halbb_sta_info_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len);
void halbb_supportability_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len);
void halbb_pause_func_init(struct bb_info *bb);
void halbb_pause_func_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len);
void halbb_store_data(struct bb_info *bb);
u32 halbb_scan_ofld_c2h(struct bb_info *bb_0, u16 len, u8 *c2h);
#endif
3rd/devourer/hal/halbb/g6/vendor/halbb_8852b/halbb_8852b.c
Vendored
+516
View File
@@ -0,0 +1,516 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "../halbb_precomp.h"
#ifdef BB_8852B_SUPPORT
bool halbb_chk_pkg_valid_8852b(struct bb_info *bb, u8 bb_ver, u8 rf_ver)
{
bool valid = true;
#if 0
if (bb_ver >= X && rf_ver >= Y)
valid = true;
else if (bb_ver < X && rf_ver < Y)
valid = true;
else
valid = false;
#endif
if (!valid) {
/*halbb_set_reg(bb, 0x1c3c, (BIT(0) | BIT(1)), 0x0);*/
BB_WARNING("[%s] Pkg_ver{bb, rf}={%d, %d} disable all BB block\n",
__func__, bb_ver, rf_ver);
}
return valid;
}
bool halbb_chk_tx_idle_8852b(struct bb_info *bb, enum phl_phy_idx phy_idx)
{
u8 tx_state = 0;
bool idle = false;
u32 dbg_port = 0x30002;
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
if (phy_idx == HW_PHY_1)
return false;
if (halbb_bb_dbg_port_racing(bb, DBGPORT_PRI_3)) {
halbb_dbg_port_sel(bb, (u16)(dbg_port & 0xffff),
(u8)((dbg_port & 0xff0000) >> 16), 0x0, 0x1);
BB_DBG(bb, DBG_PHY_CONFIG,
"*Set dbg_port=(0x%x)\n", dbg_port);
} else {
dbg_port = halbb_get_bb_dbg_port_idx(bb);
BB_DBG(bb, DBG_PHY_CONFIG,
"[Set dbg_port fail!] Curr-DbgPort=0x%x\n", dbg_port);
return false;
}
/* Release DBG port */
halbb_release_bb_dbg_port(bb);
tx_state = (u8)(halbb_get_bb_dbg_port_val(bb) & 0x3f);
if (tx_state == 0)
idle = true;
else
idle = false;
return idle;
}
void halbb_stop_pmac_tx_8852b(struct bb_info *bb,
struct halbb_pmac_info *tx_info,
enum phl_phy_idx phy_idx)
{
if (tx_info->is_cck) { // CCK
if (tx_info->mode == CONT_TX) {
halbb_set_reg(bb, 0x2300, BIT(26), 1);
halbb_set_reg(bb, 0x2338, BIT(17), 0);
halbb_set_reg(bb, 0x2300, BIT(28), 0);
halbb_set_reg(bb, 0x2300, BIT(26), 0);
} else if (tx_info->mode == PKTS_TX) {
halbb_set_reg_cmn(bb, 0x9c4, BIT(4), 0, phy_idx);
}
} else { // OFDM
if (tx_info->mode == CONT_TX)
halbb_set_reg_cmn(bb, 0x9c4, BIT(0), 0, phy_idx);
else if (tx_info->mode == PKTS_TX)
halbb_set_reg_cmn(bb, 0x9c4, BIT(4), 0, phy_idx);
}
}
void halbb_start_pmac_tx_8852b(struct bb_info *bb,
struct halbb_pmac_info *tx_info,
enum halbb_pmac_mode mode, u32 pkt_cnt,u16 period,
enum phl_phy_idx phy_idx)
{
if (mode == CONT_TX) {
if (tx_info->is_cck) {
halbb_set_reg(bb, 0x2338, BIT(17), 1);
halbb_set_reg(bb, 0x2300, BIT(28), 0);
} else {
halbb_set_reg_cmn(bb, 0x9c4, BIT(0), 1, phy_idx);
}
} else if (mode == PKTS_TX) {
/*Tx_N_PACKET_EN */
halbb_set_reg_cmn(bb, 0x9c4, BIT(4), 1, phy_idx);
/*Tx_N_PERIOD */
halbb_set_reg_cmn(bb, 0x9c4, 0xffffff00, period, phy_idx);
/*Tx_N_PACKET */
halbb_set_reg_cmn(bb, 0x9c8, 0xffffffff, pkt_cnt, phy_idx);
} else if (mode == CCK_CARRIER_SIPPRESSION_TX) {
if (tx_info->is_cck) {
/*Carrier Suppress Tx*/
halbb_set_reg(bb, 0x2338, BIT(18), 1);
/*Disable scrambler at payload part*/
halbb_set_reg(bb, 0x2304, BIT(26), 1);
} else {
return;
}
/*Tx_N_PACKET_EN */
halbb_set_reg_cmn(bb, 0x9c4, BIT(4), 1, phy_idx);
/*Tx_N_PERIOD */
halbb_set_reg_cmn(bb, 0x9c4, 0xffffff00, period, phy_idx);
/*Tx_N_PACKET */
halbb_set_reg_cmn(bb, 0x9c8, 0xffffffff, pkt_cnt, phy_idx);
}
/*Tx_EN */
halbb_set_reg_cmn(bb, 0x9c0, BIT(0), 1, phy_idx);
halbb_set_reg_cmn(bb, 0x9c0, BIT(0), 0, phy_idx);
}
void halbb_set_pmac_tx_8852b(struct bb_info *bb, struct halbb_pmac_info *tx_info,
enum phl_phy_idx phy_idx)
{
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
if (!tx_info->en_pmac_tx) {
halbb_stop_pmac_tx_8852b(bb, tx_info, phy_idx);
/* PD hit enable */
halbb_set_reg_cmn(bb, 0xc3c, BIT(9), 0, phy_idx);
halbb_set_reg(bb, 0x2344, BIT(31), 0);
return;
}
/*Turn on PMAC */
/* Tx */
halbb_set_reg_cmn(bb, 0x0980, BIT(0), 1, phy_idx);
/* Rx */
halbb_set_reg_cmn(bb, 0x0980, BIT(16), 1, phy_idx);
halbb_set_reg_cmn(bb, 0x0988, 0x3f, 0x3f, phy_idx);
/* PD hit enable */
halbb_set_reg_cmn(bb, 0xc3c, BIT(9), 1, phy_idx);
halbb_set_reg(bb, 0x2344, BIT(31), 1);
/*Protest SW-SI */
halbb_set_reg(bb, 0x1200, 0x70000000, 0x7);
halbb_set_reg(bb, 0x3200, 0x70000000, 0x7);
halbb_delay_us(bb, 1);
/*BB reset*/
halbb_set_reg(bb, 0x704, BIT(1), 0x0);
halbb_set_reg(bb, 0x1200, 0x70000000, 0x0);
halbb_set_reg(bb, 0x3200, 0x70000000, 0x0);
halbb_set_reg(bb, 0x704, BIT(1), 0x1);
//halbb_bb_reset_all_8852b(bb, HW_PHY_0);
halbb_start_pmac_tx_8852b(bb, tx_info, tx_info->mode, tx_info->tx_cnt,
tx_info->period, phy_idx);
}
void halbb_set_tmac_tx_8852b(struct bb_info *bb, enum phl_phy_idx phy_idx)
{
/* To do: 0x0d80[16] [25] / 0x0d88[5:0] Should be set to default value in parameter package*/
/* Turn on TMAC */
halbb_set_reg_cmn(bb, 0x0980, BIT(0), 0, phy_idx);
halbb_set_reg_cmn(bb, 0x0980, BIT(16), 0, phy_idx);
halbb_set_reg_cmn(bb, 0x0988, 0xfff, 0, phy_idx);
halbb_set_reg_cmn(bb, 0x0994, 0xf0, 0, phy_idx);
// PDP bypass from TMAC
halbb_set_reg_cmn(bb, 0x09a4, BIT(10), 0, phy_idx);
// TMAC Tx path
halbb_set_reg_cmn(bb, 0x09a4, 0x1c, 0, phy_idx);
// TMAC Tx power
halbb_set_reg_cmn(bb, 0x09a4, BIT(16), 0, phy_idx);
}
void halbb_ic_hw_setting_init_8852b(struct bb_info *bb)
{
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
if(phl_is_mp_mode(bb->phl_com)) {
// r_en_sound_wo_ndp
halbb_set_reg(bb, 0xd7c, BIT(1), 1);
halbb_set_reg(bb, 0x2d7c, BIT(1), 1);
} else {
// r_en_sound_wo_ndp
halbb_set_reg(bb, 0xd7c, BIT(1), 0);
halbb_set_reg(bb, 0x2d7c, BIT(1), 0);
}
if (bb->hal_com->cv != CAV) {
//set minimum UL txpwr requirement to -10dBm
halbb_write_mask_pwr_reg_cmn(bb, HW_PHY_0, 0xd240, 0x3fe00, 0x1d8);
halbb_write_mask_pwr_reg_cmn(bb, HW_PHY_1, 0xd240, 0x3fe00, 0x1d8);
//set UL txpwr compensation to 0dB
halbb_write_mask_pwr_reg_cmn(bb, HW_PHY_0, 0xd290, 0x1f, 0);
halbb_write_mask_pwr_reg_cmn(bb, HW_PHY_1, 0xd290, 0x1f, 0);
}
}
void halbb_ic_hw_setting_8852b(struct bb_info *bb)
{
bool btg_en;
struct bb_env_mntr_info *env = &bb->bb_env_mntr_i;
struct bb_link_info *link = &bb->bb_link_i;
struct rtw_phl_stainfo_t *sta = NULL;
struct rtw_rssi_info *sta_rssi = NULL;
#ifdef HALBB_STATISTICS_SUPPORT
u32 cnt_diff = 0;
struct bb_stat_info *stat = &bb->bb_stat_i;
struct bb_cca_info *cca = &stat->bb_cca_i;
struct bb_fa_info *fa = &stat->bb_fa_i;
#endif
u16 rssi_a = 0;
u16 rssi_b = 0;
u16 rssi_path_diff = 0;
u32 id = bb->phl_com->id.id & 0xFFFF;
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
if (!link->is_linked)
return;
if (!link->is_one_entry_only)
return;
sta = bb->phl_sta_info[link->one_entry_macid];
sta_rssi = &sta->hal_sta->rssi_stat;
rssi_a = sta_rssi->rssi_ma_path[0];
rssi_b = sta_rssi->rssi_ma_path[1];
rssi_path_diff = DIFF_2(rssi_a, rssi_b) >> 5;
btg_en = (bb->hal_com->band[0].cur_chandef.band == BAND_ON_24G) &&
((bb->rx_path == RF_PATH_B) || (bb->rx_path == RF_PATH_AB)) ? true : false;
if (btg_en && bb->bb_link_i.is_linked && (bb->bb_ch_i.rssi_min < (75 << 1))) {// if rssi < -35 dbm
halbb_set_reg(bb, 0x4aa4, BIT(18), 0x0);
BB_DBG(bb, DBG_PHY_CONFIG, "[BT] BTG enable, Is linked\n");
BB_DBG(bb, DBG_PHY_CONFIG, "[BT][RSSI] rssi_min=0x%x\n", bb->bb_ch_i.rssi_min >> 1);
} else {
halbb_set_reg(bb, 0x4aa4, BIT(18), 0x1);
BB_DBG(bb, DBG_PHY_CONFIG, "[BT] btg_en=%d, is_linked=%d\n", btg_en, bb->bb_link_i.is_linked);
BB_DBG(bb, DBG_PHY_CONFIG, "[BT][RSSI] rssi_min=0x%x\n", bb->bb_ch_i.rssi_min >> 1);
}
// for wrc
if ((bb->hal_com->band[0].cur_chandef.band == BAND_ON_5G) && (id == 0x112))
halbb_set_reg(bb, 0x4408, BIT(25), 0x1);
else
halbb_set_reg(bb, 0x4408, BIT(25), 0x0);
if (rssi_path_diff > 15) {
halbb_set_reg(bb, 0x4964, BIT(31), 0);
BB_DBG(bb, DBG_PHY_CONFIG,
"rssi(a,b)=(%d,%d),rssi_diff=(%d),ant_wgt_normalize_mode_OFF\n",
rssi_a, rssi_b, rssi_path_diff);
} else {
halbb_set_reg(bb, 0x4964, BIT(31), 1);
BB_DBG(bb, DBG_PHY_CONFIG,
"rssi(a,b)=(%d,%d),rssi_diff=(%d),ant_wgt_normalize_mode_ON\n",
rssi_a, rssi_b, rssi_path_diff);
}
#ifdef HALBB_STATISTICS_SUPPORT
cnt_diff = cca->cnt_ofdm_cca - fa->cnt_ofdm_fail;
#endif
// dynamic setting for anti-interference
/* if (env->nhm_ratio > 20) {
halbb_set_reg(bb, 0x46F8, 0xffffffff, 0x13c6);
halbb_set_reg(bb, 0x4440, BIT(31), 0x1);
}
*/
}
bool halbb_set_pd_lower_bound_8852b(struct bb_info *bb, u8 bound,
enum channel_width bw,
enum phl_phy_idx phy_idx)
{
/*
Range of bound value:
BW20: 95~33
BW40: 92~30
BW80: 89~27
*/
#ifdef HALBB_DIG_TDMA_SUPPORT
struct bb_dig_info *bb_dig = &bb->bb_dig_i;
struct bb_dig_op_unit *bb_dig_u = bb_dig->p_cur_dig_unit;
#endif
u8 bw_attenuation = 0;
u8 subband_filter_atteniation = 7;
u8 bound_idx = 0;
bool rpt = true;
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
if (bound == 0) {
halbb_set_reg_cmn(bb, 0x4860, BIT(30), 0, phy_idx);
BB_DBG(bb, DBG_PHY_CONFIG,
"[PD Bound] Set Boundary to default!\n");
return true;
}
bb->bb_cmn_backup_i.cur_pd_lower_bound = bound;
if ((bw == CHANNEL_WIDTH_20) || (bw == CHANNEL_WIDTH_10) || (bw == CHANNEL_WIDTH_5)) {
bw_attenuation = 0;
} else if (bw == CHANNEL_WIDTH_40) {
bw_attenuation = 3;
} else if (bw == CHANNEL_WIDTH_80) {
bw_attenuation = 6;
} else {
BB_DBG(bb, DBG_PHY_CONFIG,
"[PD Bound] Only support BW20/40/80 !\n");
return false;
}
bound += (bw_attenuation + subband_filter_atteniation);
// If Boundary dbm is odd, set it to even number
bound = bound % 2 ? bound + 1 : bound;
if (bound < 40) {
BB_DBG(bb, DBG_PHY_CONFIG,
"[PD Bound] Threshold too high, set to highest level!\n");
bound = 40;
rpt = false;
}
if (bound > 102) {
BB_DBG(bb, DBG_PHY_CONFIG,
"[PD Bound] Threshold too low, disable PD lower bound function!\n");
halbb_set_reg_cmn(bb, 0x4860, BIT(30), 0, phy_idx);
return true;
}
bound_idx = (102 - bound) >> 1;
halbb_set_reg_cmn(bb, 0x4860, 0x7c0, bound_idx, phy_idx);
halbb_set_reg_cmn(bb, 0x4860, BIT(30), 1, phy_idx);
BB_DBG(bb, DBG_PHY_CONFIG, "[PD Bound] Set Boundary Success!\n");
#ifdef HALBB_DIG_TDMA_SUPPORT
if ((bb_dig->dig_mode != DIG_TDMA) && (bb_dig->dig_mode != DIG_TDMA_ADV))
return rpt;
if (bb_dig_u->state_identifier == DIG_TDMA_LOW)
bb_dig->dig_state_l_i.pd_low_th = bound;
else
bb_dig->dig_state_h_i.pd_low_th = bound;
#endif
return rpt;
}
bool halbb_set_pd_lower_bound_cck_8852b(struct bb_info *bb, u8 bound,
enum channel_width bw,
enum phl_phy_idx phy_idx)
{
#ifdef HALBB_DIG_TDMA_SUPPORT
struct bb_dig_info *bb_dig = &bb->bb_dig_i;
struct bb_dig_op_unit *bb_dig_u = bb_dig->p_cur_dig_unit;
#endif
u8 bw_attenuation = 0;
u8 subband_filter_atteniation = 5;
s8 bound_tmp = 0;
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
if (bb->hal_com->cv < CBV) {
BB_DBG(bb, DBG_PHY_CONFIG, "[PD Bound] CCK pd_lower_bound CV not support!\n");
return false;
}
if (bound == 0) {
halbb_set_reg_cmn(bb, 0x23b0, BIT(23), 0, phy_idx);
BB_DBG(bb, DBG_PHY_CONFIG,
"[PD Bound] Set Boundary to default!\n");
return true;
}
if ((bw == CHANNEL_WIDTH_20) || (bw == CHANNEL_WIDTH_10) || (bw == CHANNEL_WIDTH_5)) {
bw_attenuation = 0;
}
else if (bw == CHANNEL_WIDTH_40) {
bw_attenuation = 3;
}
else if (bw == CHANNEL_WIDTH_80) {
bw_attenuation = 6;
}
else {
BB_DBG(bb, DBG_PHY_CONFIG,
"[PD Bound] Only support BW20/40/80 !\n");
return true;
}
bound += (bw_attenuation + subband_filter_atteniation);
bound_tmp = (-1) * MIN_2(bound, 128);
halbb_set_reg_cmn(bb, 0x23b0, 0xff000000, bound_tmp, phy_idx);
halbb_set_reg_cmn(bb, 0x23b4, 0xff000000, 0x7f, phy_idx);
halbb_set_reg_cmn(bb, 0x23b0, BIT(23), 1, phy_idx);
BB_DBG(bb, DBG_PHY_CONFIG, "[PD Bound] Set CCK Boundary Success!\n");
#ifdef HALBB_DIG_TDMA_SUPPORT
if ((bb_dig->dig_mode != DIG_TDMA) && (bb_dig->dig_mode != DIG_TDMA_ADV))
return true;
if (bb_dig_u->state_identifier == DIG_TDMA_LOW)
bb_dig->dig_state_l_i.rssi_nocca_low_th= bound_tmp;
else
bb_dig->dig_state_h_i.rssi_nocca_low_th = bound_tmp;
#endif
return true;
}
u8 halbb_querry_pd_lower_bound_8852b(struct bb_info *bb, bool get_en_info, enum phl_phy_idx phy_idx)
{
u8 tmp;
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
if (get_en_info)
tmp = (u8)halbb_get_reg_cmn(bb, 0x4860, BIT(30), phy_idx);
else
tmp = bb->bb_cmn_backup_i.cur_pd_lower_bound;
return tmp;
}
void halbb_pop_en_8852b(struct bb_info *bb, bool en, enum phl_phy_idx phy_idx)
{
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
if (en) {
halbb_set_reg_cmn(bb, 0x47D4, BIT(8), 1, phy_idx);
} else {
halbb_set_reg_cmn(bb, 0x47D4, BIT(8), 0, phy_idx);
}
}
bool halbb_querry_pop_en_8852b(struct bb_info *bb, enum phl_phy_idx phy_idx)
{
bool en;
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
en = (bool)halbb_get_reg_cmn(bb, 0x47D4, BIT(8), phy_idx);
return en;
}
void halbb_dyn_mu_bypass_vht_sigb_8852b(struct bb_info *bb)
{
struct bb_cmn_rpt_info *cmn_rpt = &bb->bb_cmn_rpt_i;
struct bb_pkt_cnt_mu_info *pkt_cnt = &cmn_rpt->bb_pkt_cnt_mu_i;
u8 offset = 0;
u32 vht_mu_pkt_th = 10;
u32 vht_mu_pkt = 0;
for (offset = 0; offset < VHT_RATE_NUM; offset++) {
vht_mu_pkt += pkt_cnt->pkt_cnt_vht[offset];
}
if (vht_mu_pkt > vht_mu_pkt_th) {
halbb_set_reg(bb, 0x4414, BIT(5), 1); // loop filter bandwidth selection slicer for 1st step to 2nd step
halbb_set_reg(bb, 0x4400, 0x07000000, 0x3); // channel tracking coefficients selection slicer for 1st step to 2nd step
halbb_set_reg(bb, 0x4404, 0x000f8000, 0x1f); // data tracking loop filter bandwidth selection for 2nd step
halbb_set_reg(bb, 0x4404, 0x0000001f, 0x4); // channel tracking coefficients selection slicer for 2nd step to 3rd step
halbb_set_reg(bb, 0x43f8, 0x00fc0000, 0x0); // channel tracking coefficients for 2nd step
halbb_set_reg(bb, 0x440c, 0x000f8000, 0x1f); // pilot tracking loop filter bandwidth selection for 2nd step
halbb_set_reg(bb, 0x43f8, BIT(30), 0); // enable noise variance tracking
} else {
halbb_set_reg(bb, 0x4414, BIT(5), 0); // loop filter bandwidth selection slicer for 1st step to 2nd step
halbb_set_reg(bb, 0x4400, 0x07000000, 0x4); // channel tracking coefficients selection slicer for 1st step to 2nd step
halbb_set_reg(bb, 0x4404, 0x000f8000, 0x1); // data tracking loop filter bandwidth selection for 2nd step
halbb_set_reg(bb, 0x4404, 0x0000001f, 0x8); // channel tracking coefficients selection slicer for 2nd step to 3rd step
halbb_set_reg(bb, 0x43f8, 0x00fc0000, 0x4); // channel tracking coefficients for 2nd step
halbb_set_reg(bb, 0x440c, 0x000f8000, 0x1); // pilot tracking loop filter bandwidth selection for 2nd step
halbb_set_reg(bb, 0x43fc, BIT(30), 1); // enable noise variance tracking
}
}
#endif
3rd/devourer/hal/halbb/g6/vendor/halbb_8852b/halbb_8852b.h
Vendored
+54
View File
@@ -0,0 +1,54 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_8852B_H__
#define __HALBB_8852B_H__
#ifdef BB_8852B_SUPPORT
#include "../halbb_pmac_setting_ex.h"
struct bb_info;
bool halbb_chk_pkg_valid_8852b(struct bb_info *bb, u8 bb_ver, u8 rf_ver);
void halbb_set_pmac_tx_8852b(struct bb_info *bb, struct halbb_pmac_info *tx_info,
enum phl_phy_idx phy_idx);
void halbb_set_tmac_tx_8852b(struct bb_info *bb, enum phl_phy_idx phy_idx);
void halbb_ic_hw_setting_init_8852b(struct bb_info *bb);
void halbb_ic_hw_setting_8852b(struct bb_info *bb);
bool halbb_set_pd_lower_bound_8852b(struct bb_info *bb, u8 bound,
enum channel_width bw,
enum phl_phy_idx phy_idx);
bool halbb_set_pd_lower_bound_cck_8852b(struct bb_info *bb, u8 bound,
enum channel_width bw,
enum phl_phy_idx phy_idx);
u8 halbb_querry_pd_lower_bound_8852b(struct bb_info *bb, bool get_en_info,
enum phl_phy_idx phy_idx);
void halbb_pop_en_8852b(struct bb_info *bb, bool en, enum phl_phy_idx phy_idx);
bool halbb_querry_pop_en_8852b(struct bb_info *bb, enum phl_phy_idx phy_idx);
void halbb_dyn_mu_bypass_vht_sigb_8852b(struct bb_info *bb);
bool halbb_chk_tx_idle_8852b(struct bb_info *bb, enum phl_phy_idx phy_idx);
#endif
#endif /* __HALBB_8852b_H__ */
3rd/devourer/hal/halbb/g6/vendor/halbb_8852b/halbb_8852b_api.c
Vendored
+3176
View File
File diff suppressed because it is too large Load Diff
3rd/devourer/hal/halbb/g6/vendor/halbb_8852b/halbb_8852b_api.h
Vendored
+270
View File
@@ -0,0 +1,270 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_8852B_API_H__
#define __HALBB_8852B_API_H__
#ifdef BB_8852B_SUPPORT
#ifdef HALBB_CONFIG_RUN_IN_DRV
#include "../halbb_api.h"
#endif
/*@--------------------------[Define]-------------------------------------*/
#define INVALID_RF_DATA 0xffffffff
#define BB_PATH_MAX_8852B 2
#define GAIN_HIDE_EFUSE_A_2G_8852B 0x5BB
#define GAIN_HIDE_EFUSE_A_5GL_8852B 0x5BA
#define GAIN_HIDE_EFUSE_A_5GM_8852B 0x5B9
#define GAIN_HIDE_EFUSE_A_5GH_8852B 0x5B8
#define GAIN_HIDE_EFUSE_B_2G_8852B 0x590
#define GAIN_HIDE_EFUSE_B_5GL_8852B 0x58F
#define GAIN_HIDE_EFUSE_B_5GM_8852B 0x58E
#define GAIN_HIDE_EFUSE_B_5GH_8852B 0x58D
#define GAIN_HIDE_EFUSE_A_6GH_0_8852BP 0x5B7
#define GAIN_HIDE_EFUSE_A_6GH_1_8852BP 0x5B6
#define GAIN_HIDE_EFUSE_A_6GH_2_8852BP 0x5B5
#define GAIN_HIDE_EFUSE_A_6GH_3_8852BP 0x5B4
#define GAIN_HIDE_EFUSE_A_6GH_4_8852BP 0x5B3
#define GAIN_HIDE_EFUSE_A_6GH_5_8852BP 0x5B2
#define GAIN_HIDE_EFUSE_A_6GH_6_8852BP 0x5B1
#define GAIN_HIDE_EFUSE_A_6GH_7_8852BP 0x5B0
#define GAIN_HIDE_EFUSE_B_6GH_0_8852BP 0x58C
#define GAIN_HIDE_EFUSE_B_6GH_1_8852BP 0x58B
#define GAIN_HIDE_EFUSE_B_6GH_2_8852BP 0x58A
#define GAIN_HIDE_EFUSE_B_6GH_3_8852BP 0x589
#define GAIN_HIDE_EFUSE_B_6GH_4_8852BP 0x588
#define GAIN_HIDE_EFUSE_B_6GH_5_8852BP 0x587
#define GAIN_HIDE_EFUSE_B_6GH_6_8852BP 0x586
#define GAIN_HIDE_EFUSE_B_6GH_7_8852BP 0x585
/*@--------------------------[Enum]------------------------------------------*/
/*@--------------------------[Structure]-------------------------------------*/
struct bb_h2c_lps_info_8852b {
u8 central_ch;
u8 pri_ch;
u8 bw;
u8 band_type;
};
/*@--------------------------[Prptotype]-------------------------------------*/
struct bb_info;
u8 halbb_ex_cn_report_8852b(struct bb_info *bb);
u8 halbb_ex_evm_1ss_report_8852b(struct bb_info *bb);
u8 halbb_ex_evm_max_report_8852b(struct bb_info *bb);
u8 halbb_ex_evm_min_report_8852b(struct bb_info *bb);
bool halbb_set_pwr_ul_tb_ofst_8852b(struct bb_info *bb,
s16 pw_ofst, enum phl_phy_idx phy_idx);
bool halbb_lps_info_8852b(struct bb_info *bb, u16 mac_id);
bool halbb_lps_cmn_info_8852b(struct bb_info *bb);
void halbb_digital_cfo_comp_8852b(struct bb_info *bb, s32 curr_cfo);
void halbb_tx_triangular_shap_cfg_8852b(struct bb_info *bb, u8 shape_idx,
enum phl_phy_idx phy_idx);
void halbb_tx_dfir_shap_cck_8852b(struct bb_info *bb, u8 ch, u8 shape_idx,
enum phl_phy_idx phy_idx);
void halbb_bb_reset_all_8852b(struct bb_info * bb, enum phl_phy_idx phy_idx);
bool halbb_spur_location_8852b(struct bb_info *bb, u8 central_ch,
enum channel_width bw, enum band_type band,
u32 *intf);
bool halbb_ctrl_bw_ch_8852b(struct bb_info *bb, u8 pri_ch, u8 central_ch,
enum channel_width bw, enum band_type band,
enum phl_phy_idx phy_idx);
bool halbb_ctrl_rx_path_8852b(struct bb_info *bb, enum rf_path rx_path);
bool halbb_ctrl_tx_path_pmac_8852b(struct bb_info *bb, enum rf_path tx_path);
bool halbb_ctrl_tx_path_tmac_8852b(struct bb_info *bb, enum rf_path tx_path_1sts);
bool halbb_ctrl_tx_path_8852b(struct bb_info *bb, enum rf_path tx_path);
#ifdef HALBB_CONFIG_RUN_IN_DRV
void halbb_gpio_ctrl_dump_8852b(struct bb_info *bb);
void halbb_gpio_rfm_8852b(struct bb_info *bb, enum bb_path path,
enum bb_rfe_src_sel src, bool dis_tx_gnt_wl,
bool active_tx_opt, bool act_bt_en, u8 rfm_output_val);
void halbb_gpio_trsw_table_8852b(struct bb_info *bb, enum bb_path path,
bool path_en, bool trsw_tx,
bool trsw_rx, bool trsw, bool trsw_b);
void halbb_gpio_setting_8852b(struct bb_info *bb, u8 gpio_idx,
enum bb_path path, bool inv,
enum bb_rfe_src_sel src);
void halbb_gpio_setting_all_8852b(struct bb_info *bb, u8 rfe_idx);
void halbb_gpio_setting_init_8852b(struct bb_info *bb);
void halbb_bb_reset_8852b(struct bb_info *bb, enum phl_phy_idx phy_idx);
void halbb_dfs_en_8852b(struct bb_info *bb, bool en);
void halbb_adc_en_8852b(struct bb_info *bb, bool en);
bool halbb_adc_cfg_8852bt(struct bb_info *bb, enum channel_width bw,
enum rf_path path);
bool halbb_adc_cfg_8852bpt(struct bb_info *bb, enum channel_width bw,
enum rf_path path);
void halbb_tssi_cont_en_8852b(struct bb_info *bb, bool en, enum rf_path path);
void halbb_bb_reset_en_8852b(struct bb_info *bb, bool en, enum phl_phy_idx phy_idx);
u32 halbb_read_rf_reg_8852b_a(struct bb_info *bb, enum rf_path path,
u32 reg_addr, u32 bit_mask);
u32 halbb_read_rf_reg_8852b_d(struct bb_info *bb, enum rf_path path,
u32 reg_addr, u32 bit_mask);
u32 halbb_read_rf_reg_8852b(struct bb_info *bb, enum rf_path path, u32 reg_addr,
u32 bit_mask);
bool halbb_write_rf_reg_8852b_a(struct bb_info *bb, enum rf_path path,
u32 reg_addr, u32 bit_mask, u32 data);
bool halbb_write_rf_reg_8852b_d(struct bb_info *bb, enum rf_path path,
u32 reg_addr, u32 bit_mask, u32 data);
bool halbb_write_rf_reg_8852b(struct bb_info *bb, enum rf_path path, u32 reg_addr,
u32 bit_mask, u32 data);
bool halbb_ctrl_bw_8852b(struct bb_info *bb, u8 pri_ch, enum channel_width bw,
enum phl_phy_idx phy_idx);
bool halbb_ctrl_ch_8852b(struct bb_info *bb, u8 central_ch, enum band_type band,
enum phl_phy_idx phy_idx);
void halbb_ctrl_cck_en_8852b(struct bb_info *bb, bool cck_en,
enum phl_phy_idx phy_idx);
void halbb_ctrl_trx_path_8852b(struct bb_info *bb, enum rf_path tx_path,
u8 tx_nss, enum rf_path rx_path, u8 rx_nss);
void halbb_tssi_bb_reset_8852b(struct bb_info *bb);
bool halbb_ctrl_sco_cck_8852b(struct bb_info *bb, u8 pri_ch);
bool halbb_bw_setting_8852b(struct bb_info *bb, enum channel_width bw,
enum rf_path path);
bool halbb_ch_setting_8852b(struct bb_info *bb, u8 central_ch, enum rf_path path,
bool *is_2g_ch);
void halbb_ctrl_rf_mode_8852b(struct bb_info *bb, enum phl_rf_mode mode);
void halbb_ctrl_rf_mode_rx_path_8852b(struct bb_info *bb, enum rf_path rx_path);
bool halbb_ctrl_ch2_80p80_8852b(struct bb_info *bb, u8 central_ch);
void halbb_ctrl_rx_cca_8852b(struct bb_info *bb, bool cca_en, enum phl_phy_idx phy_idx);
void halbb_ctrl_ofdm_en_8852b(struct bb_info *bb, bool ofdm_en,
enum phl_phy_idx phy_idx);
bool halbb_set_txpwr_dbm_8852b(struct bb_info *bb, s16 power_dbm,
enum phl_phy_idx phy_idx);
void halbb_reset_bb_hw_cnt_8852b(struct bb_info *bb);
s16 halbb_get_txpwr_dbm_8852b(struct bb_info *bb, enum phl_phy_idx phy_idx);
s16 halbb_get_txinfo_txpwr_dbm_8852b(struct bb_info *bb);
bool halbb_set_cck_txpwr_idx_8852b(struct bb_info *bb, u16 power_idx,
enum rf_path tx_path);
u16 halbb_get_cck_txpwr_idx_8852b(struct bb_info *bb, enum rf_path tx_path);
s16 halbb_get_cck_ref_dbm_8852b(struct bb_info *bb, enum rf_path tx_path);
bool halbb_set_ofdm_txpwr_idx_8852b(struct bb_info *bb, u16 power_idx,
enum rf_path tx_path);
u16 halbb_get_ofdm_txpwr_idx_8852b(struct bb_info *bb, enum rf_path tx_path);
s16 halbb_get_ofdm_ref_dbm_8852b(struct bb_info *bb, enum rf_path tx_path);
void halbb_backup_info_8852b(struct bb_info *bb, enum phl_phy_idx phy_idx);
bool halbb_cfg_lbk_8852b(struct bb_info *bb, bool lbk_en, bool is_dgt_lbk,
enum rf_path tx_path, enum rf_path rx_path,
enum channel_width bw, enum phl_phy_idx phy_idx);
bool halbb_cfg_lbk_cck_8852b(struct bb_info *bb, bool lbk_en, bool is_dgt_lbk,
enum rf_path tx_path, enum rf_path rx_path,
enum channel_width bw, enum phl_phy_idx phy_idx);
void halbb_restore_info_8852b(struct bb_info *bb, enum phl_phy_idx phy_idx);
void halbb_ctrl_btg_8852b(struct bb_info *bb, bool btg);
void halbb_ctrl_btc_preagc_8852b(struct bb_info *bb, bool bt_en);
bool halbb_set_txsc_8852b(struct bb_info *bb, u8 txsc, enum phl_phy_idx phy_idx);
bool halbb_set_bss_color_8852b(struct bb_info *bb, u8 bss_color,
enum phl_phy_idx phy_idx);
bool halbb_set_sta_id_8852b(struct bb_info *bb, u16 sta_id,
enum phl_phy_idx phy_idx);
void halbb_set_igi_8852b(struct bb_info *bb, u8 lna_idx, bool tia_idx,
u8 rxbb_idx, enum rf_path path);
void halbb_set_tx_pow_ref_8852b(struct bb_info *bb, s16 pw_dbm_ofdm,
s16 pw_dbm_cck, s8 ofst,
u8 base_cw_0db, u16 tssi_16dBm_cw,
u16 *ofdm_cw, u16 *cck_cw,
enum phl_phy_idx phy_idx);
void halbb_dump_bb_reg_8852b(struct bb_info *bb, u32 *_used, char *output,
u32 *_out_len, bool dump_2_buff);
void halbb_dbgport_dump_all_8852b(struct bb_info *bb, u32 *_used, char *output,
u32 *_out_len);
void halbb_physts_brk_fail_pkt_rpt_8852b(struct bb_info *bb, bool enable,
enum phl_phy_idx phy_idx);
bool halbb_rf_write_bb_reg_8852b(struct bb_info *bb, u32 addr, u32 mask, u32 data);
void halbb_pre_agc_en_8852b(struct bb_info *bb, bool enable);
void halbb_agc_fix_gain_8852b(struct bb_info *bb, bool enable, enum rf_path path);
void halbb_agc_tia_shrink_8852b(struct bb_info *bb, bool shrink_en,
bool shrink_init, enum rf_path path);
void halbb_agc_step_en_8852b(struct bb_info *bb, bool pre_pd_agc_en,
bool linear_agc_en, bool post_pd_agc_en,
bool nlgc_agc_en, enum rf_path path);
void halbb_set_gain_error_8852b(struct bb_info *bb, u8 central_ch, enum band_type band_type);
void halbb_set_efuse_8852b(struct bb_info *bb, u8 central_ch, enum phl_phy_idx phy_idx);
void halbb_get_efuse_ofst_init_8852b(struct bb_info *bb);
void halbb_get_normal_efuse_init_8852b(struct bb_info *bb);
void halbb_get_hide_efuse_init_8852b(struct bb_info *bb);
void halbb_set_rxsc_rpl_comp_8852b(struct bb_info *bb, u8 central_ch, enum band_type band_type);
void halbb_normal_efuse_verify_8852b(struct bb_info *bb, s8 rx_gain_offset,
enum rf_path rx_path,
enum phl_phy_idx phy_idx);
void halbb_normal_efuse_verify_cck_8852b(struct bb_info *bb, s8 rx_gain_offset,
enum rf_path rx_path,
enum phl_phy_idx phy_idx);
void halbb_nvar_src_sel_8852b(struct bb_info *bb, bool is_BF);
#endif
#endif
#endif /* __INC_PHYDM_API_H_8852A__ */
3rd/devourer/hal/halbb/g6/vendor/halbb_8852b/halbb_8852b_api_ex.h
Vendored
+35
View File
@@ -0,0 +1,35 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_8852B_API_EX_H__
#define __HALBB_8852B_API_EX_H__
#ifdef BB_8852B_SUPPORT
/*@--------------------------[Prptotype]-------------------------------------*/
struct bb_info;
u16 halbb_cfg_cmac_tx_ant_8852b(struct bb_info *bb, enum rf_path tx_path);
#endif
#endif /* __INC_PHYDM_API_H_8852A__ */
3rd/devourer/hal/halbb/g6/vendor/halbb_8852b/halbb_8852b_fwofld_api.h
Vendored
+61
View File
@@ -0,0 +1,61 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_8852B_FWOFLD_API_H__
#define __HALBB_8852B_FWOFLD_API_H__
#ifdef BB_8852B_SUPPORT
#ifdef HALBB_CONFIG_RUN_IN_DRV
#include "../halbb_api.h"
#include "../halbb_fwofld_ex.h"
#endif
/*@--------------------------[Define] ---------------------------------------*/
/*@--------------------------[Enum]------------------------------------------*/
/*@--------------------------[Structure]-------------------------------------*/
struct bb_info;
/*@--------------------------[Prptotype]-------------------------------------*/
#ifdef HALBB_FW_OFLD_SUPPORT
void halbb_fwofld_bb_reset_8852b(struct bb_info *bb, enum phl_phy_idx phy_idx);
bool halbb_fwcfg_bb_phy_8852b(struct bb_info *bb, u32 addr, u32 data,
enum phl_phy_idx phy_idx);
bool halbb_fwofld_ctrl_ch_8852b(struct bb_info *bb, u8 central_ch, enum band_type band,
enum phl_phy_idx phy_idx);
bool halbb_fwofld_ctrl_bw_ch_8852b(struct bb_info *bb, u8 pri_ch, u8 central_ch,
enum channel_width bw, enum band_type band,
enum phl_phy_idx phy_idx);
void halbb_fwofld_ctrl_cck_en_8852b(struct bb_info *bb, bool cck_en,
enum phl_phy_idx phy_idx);
void halbb_fwofld_set_efuse_8852b(struct bb_info *bb, u8 central_ch, enum phl_phy_idx phy_idx);
void halbb_fwofld_set_gain_error_8852b(struct bb_info *bb, u8 central_ch, enum band_type band_type);
void halbb_fwofld_set_rxsc_rpl_comp_8852b(struct bb_info *bb, u8 central_ch, enum band_type band_type);
void halbb_fwofld_set_pmac_tx_8852b(struct bb_info *bb, struct halbb_pmac_info *tx_info,
enum phl_phy_idx phy_idx);
#endif
#endif
#endif
3rd/devourer/hal/halbb/g6/vendor/halbb_8852b/halbb_cr_info_8852b.h
Vendored
+13843
View File
File diff suppressed because it is too large Load Diff
3rd/devourer/hal/halbb/g6/vendor/halbb_8852b/halbb_hwimg_8852b.c
Vendored
+369
View File
@@ -0,0 +1,369 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "../halbb_precomp.h"
#include "halbb_hwimg_raw_data_8852b.h"
#include "halbb_hwimg_raw_data_8852bp.h"
#include "halbb_hwimg_raw_data_8852bt.h"
#include "halbb_hwimg_raw_data_8852bpt.h"
#include "halbb_hwimg_raw_data_8852b_gain.h"
#ifdef BB_8852B_SUPPORT
#if 0
bool halbb_sel_headline_8852b(struct bb_info *bb, u32 *array, u32 array_len,
u8 *headline_size, u8 *headline_idx)
{
bool case_match = false;
u32 cut_drv = (u32)bb->hal_com->cv;
u32 rfe_drv = (u32)bb->phl_com->dev_cap.rfe_type;
u32 cut_para = 0, rfe_para = 0;
u32 compare_target = 0;
u32 cut_max = 0;
u32 i = 0;
*headline_idx = 0;
*headline_size = 0;
if (bb->bb_dbg_i.cr_dbg_mode_en) {
rfe_drv = bb->bb_dbg_i.rfe_type_curr_dbg;
cut_drv = bb->bb_dbg_i.cut_curr_dbg;
}
BB_DBG(bb, DBG_INIT, "{RFE, Cart}={%d, %d}, dbg_en=%d\n",
rfe_drv, cut_drv, bb->bb_dbg_i.cr_dbg_mode_en);
while ((i + 1) < array_len) {
if ((array[i] >> 28) != 0xf) {
*headline_size = (u8)i;
break;
}
BB_DBG(bb, DBG_INIT, "array[%02d]=0x%08x, array[%02d]=0x%08x\n",
i, array[i], i+1, array[i+1]);
i += 2;
}
BB_DBG(bb, DBG_INIT, "headline_size=%d\n", i);
if (i == 0)
return true;
/*case_idx:1 {RFE:Match, CV:Match}*/
compare_target = ((rfe_drv & 0xff) << 16) | (cut_drv & 0xff);
BB_DBG(bb, DBG_INIT, "[1] CHK {RFE:Match, CV:Match}\n");
for (i = 0; i < *headline_size; i += 2) {
if ((array[i] & 0x0fffffff) == compare_target) {
*headline_idx = (u8)(i >> 1);
return true;
}
}
BB_DBG(bb, DBG_INIT, "\t fail\n");
/*case_idx:2 {RFE:Match, CV:Dont care}*/
compare_target = ((rfe_drv & 0xff) << 16) | (DONT_CARE_8852B & 0xff);
BB_DBG(bb, DBG_INIT, "[2] CHK {RFE:Match, CV:Dont_Care}\n");
for (i = 0; i < *headline_size; i += 2) {
if ((array[i] & 0x0fffffff) == compare_target) {
*headline_idx = (u8)(i >> 1);
return true;
}
}
BB_DBG(bb, DBG_INIT, "\t fail\n");
/*case_idx:3 {RFE:Match, CV:Max_in_Table}*/
BB_DBG(bb, DBG_INIT, "[3] CHK {RFE:Match, CV:Max_in_Table}\n");
for (i = 0; i < *headline_size; i += 2) {
rfe_para = (array[i] & 0x00ff0000) >> 16;
cut_para = array[i] & 0x0ff;
if (rfe_para == rfe_drv) {
if (cut_para >= cut_max) {
cut_max = cut_para;
*headline_idx = (u8)(i >> 1);
BB_DBG(bb, DBG_INIT, "cut_max:%d\n", cut_max);
case_match = true;
}
}
}
if (case_match) {
return true;
}
BB_DBG(bb, DBG_INIT, "\t fail\n");
/*case_idx:4 {RFE:Dont Care, CV:Max_in_Table}*/
BB_DBG(bb, DBG_INIT, "[4] CHK {RFE:Dont_Care, CV:Max_in_Table}\n");
for (i = 0; i < *headline_size; i += 2) {
rfe_para = (array[i] & 0x00ff0000) >> 16;
cut_para = array[i] & 0x0ff;
if (rfe_para == DONT_CARE_8852B) {
if (cut_para >= cut_max) {
cut_max = cut_para;
*headline_idx = (u8)(i >> 1);
BB_DBG(bb, DBG_INIT, "cut_max:%d\n", cut_max);
case_match = true;
}
}
}
if (case_match) {
return true;
}
BB_DBG(bb, DBG_INIT, "\t fail\n");
/*case_idx:5 {RFE:Not_Match, CV:Not_Match}*/
BB_DBG(bb, DBG_INIT, "[5] CHK {RFE:Not_Match, CV:Not_Match}\n");
BB_DBG(bb, DBG_INIT, "\t all fail\n");
return false;
}
#endif
void halbb_flag_2_default_8852b(bool *is_matched, bool *find_target)
{
*is_matched = true;
*find_target = false;
}
bool halbb_cfg_bbcr_ax_8852b(struct bb_info *bb, bool is_form_folder,
u32 folder_len, u32 *folder_array,
enum phl_phy_idx phy_idx)
{
bool is_matched, find_target;
u32 cfg_target = 0, cfg_para = 0;
u32 i = 0;
u32 array_len = 0;
u32 *array = NULL;
u32 v1 = 0, v2 = 0;
u8 h_size = 0;
u8 h_idx = 0;
bool ret = false;
BB_DBG(bb, DBG_INIT, "===> %s\n", __func__);
if (is_form_folder) {
array_len = folder_len;
array = folder_array;
} else if (bb->ic_sub_type == BB_IC_SUB_TYPE_8852B_8852BP) {
array_len = sizeof(array_mp_8852bp_phy_reg) / sizeof(u32);
array = (u32 *)array_mp_8852bp_phy_reg;
} else if (bb->ic_sub_type == BB_IC_SUB_TYPE_8852B_8852BT) {
array_len = sizeof(array_mp_8852bt_phy_reg) / sizeof(u32);
array = (u32 *)array_mp_8852bt_phy_reg;
} else if (bb->ic_sub_type == BB_IC_SUB_TYPE_8852B_8852BPT) {
array_len = sizeof(array_mp_8852bpt_phy_reg) / sizeof(u32);
array = (u32 *)array_mp_8852bpt_phy_reg;
} else {
array_len = sizeof(array_mp_8852b_phy_reg) / sizeof(u32);
array = (u32 *)array_mp_8852b_phy_reg;
}
BB_DBG(bb, DBG_INIT, "BBCR_form_folder=%d, len=%d, phy_idx=%d\n",
is_form_folder, array_len, phy_idx);
if (!halbb_sel_headline(bb, array, array_len, &h_size, &h_idx)) {
BB_WARNING("[%s]Invalid BB CR Pkg\n", __func__);
return false;
}
BB_DBG(bb, DBG_INIT, "h_size = %d, h_idx = %d\n", h_size, h_idx);
if (h_size != 0) {
cfg_target = array[h_idx << 1] & 0x0fffffff;
}
i += h_size;
BB_DBG(bb, DBG_INIT, "cfg_target = 0x%x\n", cfg_target);
BB_DBG(bb, DBG_INIT, "array[i] = 0x%x, array[i+1] = 0x%x\n", array[i], array[i + 1]);
halbb_flag_2_default_8852b(&is_matched, &find_target);
#ifdef HALBB_FW_OFLD_SUPPORT
if (halbb_check_fw_ofld(bb))
BB_DBG(bb, DBG_FW_INFO, "Becareful it is fwofld mode in BB init !!");
#endif
while ((i + 1) < array_len) {
v1 = array[i];
v2 = array[i + 1];
i += 2;
switch (v1 >> 28) {
case IF_8852B:
case ELSE_IF_8852B:
cfg_para = v1 & 0x0fffffff;
BB_DBG(bb, DBG_INIT, "*if (rfe=%d, cart=%d)\n",
(cfg_para & 0xff0000) >> 16, cfg_para & 0xff);
break;
case ELSE_8852B:
BB_DBG(bb, DBG_INIT, "*else\n");
is_matched = false;
if (!find_target) {
BB_WARNING("Init BBCR Fail in Reg 0x%x\n", array[i]);
return false;
}
break;
case END_8852B:
BB_DBG(bb, DBG_INIT, "*endif\n");
halbb_flag_2_default_8852b(&is_matched, &find_target);
break;
case CHK_8852B:
/*Check this para meets driver's requirement or not*/
if (find_target) {
BB_DBG(bb, DBG_INIT, "\t skip\n");
is_matched = false;
break;
}
if (cfg_para == cfg_target) {
is_matched = true;
find_target = true;
} else {
is_matched = false;
find_target = false;
}
BB_DBG(bb, DBG_INIT, "\t match=%d\n", is_matched);
break;
default:
if (is_matched)
#ifdef HALBB_FW_OFLD_SUPPORT
ret = halbb_fwcfg_bb_phy_8852b(bb, v1, v2, phy_idx);
#else
halbb_cfg_bb_phy_8852b(bb, v1, v2, phy_idx);
#endif
break;
}
}
BB_DBG(bb, DBG_INIT, "BBCR Init Success\n\n");
#ifdef HALBB_FW_OFLD_SUPPORT
return ret;
#else
return true;
#endif
}
bool halbb_cfg_bb_gain_ax_8852b(struct bb_info *bb, bool is_form_folder,
u32 folder_len, u32 *folder_array)
{
bool is_matched, find_target;
u32 cfg_target = 0, cfg_para = 0;
u32 i = 0;
u32 array_len = 0;
u32 *array = NULL;
u32 v1 = 0, v2 = 0;
u8 h_size = 0;
u8 h_idx = 0;
BB_DBG(bb, DBG_INIT, "===> %s\n", __func__);
if (is_form_folder) {
array_len = folder_len;
array = folder_array;
} else if (bb->ic_sub_type == BB_IC_SUB_TYPE_8852B_8852BP) {
array_len = sizeof(array_mp_8852bp_phy_reg_gain) / sizeof(u32);
array = (u32 *)array_mp_8852bp_phy_reg_gain;
} else if (bb->ic_sub_type == BB_IC_SUB_TYPE_8852B_8852BT) {
array_len = sizeof(array_mp_8852bt_phy_reg_gain) / sizeof(u32);
array = (u32 *)array_mp_8852bt_phy_reg_gain;
} else if (bb->ic_sub_type == BB_IC_SUB_TYPE_8852B_8852BPT) {
array_len = sizeof(array_mp_8852bpt_phy_reg_gain) / sizeof(u32);
array = (u32 *)array_mp_8852bpt_phy_reg_gain;
} else {
array_len = sizeof(array_mp_8852b_phy_reg_gain) / sizeof(u32);
array = (u32 *)array_mp_8852b_phy_reg_gain;
}
BB_DBG(bb, DBG_INIT, "GAIN_TABLE_form_folder=%d, len=%d\n",
is_form_folder, array_len);
if (!halbb_sel_headline(bb, array, array_len, &h_size, &h_idx)) {
BB_WARNING("[%s]Invalid BB CR Pkg\n", __func__);
return false;
}
BB_DBG(bb, DBG_INIT, "h_size = %d, h_idx = %d\n", h_size, h_idx);
if (h_size != 0) {
cfg_target = array[h_idx << 1] & 0x0fffffff;
}
i += h_size;
BB_DBG(bb, DBG_INIT, "cfg_target = 0x%x\n", cfg_target);
BB_DBG(bb, DBG_INIT, "array[i] = 0x%x, array[i+1] = 0x%x\n", array[i], array[i + 1]);
halbb_flag_2_default_8852b(&is_matched, &find_target);
while ((i + 1) < array_len) {
v1 = array[i];
v2 = array[i + 1];
i += 2;
switch (v1 >> 28) {
case IF_8852B:
case ELSE_IF_8852B:
cfg_para = v1 & 0x0fffffff;
BB_DBG(bb, DBG_INIT, "*if (rfe=%d, cart=%d)\n",
(cfg_para & 0xff0000) >> 16, cfg_para & 0xff);
break;
case ELSE_8852B:
BB_DBG(bb, DBG_INIT, "*else\n");
is_matched = false;
if (!find_target) {
BB_WARNING("Init BBCR Fail in Reg 0x%x\n", array[i]);
return false;
}
break;
case END_8852B:
BB_DBG(bb, DBG_INIT, "*endif\n");
halbb_flag_2_default_8852b(&is_matched, &find_target);
break;
case CHK_8852B:
/*Check this para meets driver's requirement or not*/
if (find_target) {
BB_DBG(bb, DBG_INIT, "\t skip\n");
is_matched = false;
break;
}
if (cfg_para == cfg_target) {
is_matched = true;
find_target = true;
} else {
is_matched = false;
find_target = false;
}
BB_DBG(bb, DBG_INIT, "\t match=%d\n", is_matched);
break;
default:
if (is_matched)
halbb_cfg_bb_gain_8852b(bb, v1, v2);
break;
}
}
BB_DBG(bb, DBG_INIT, "BBCR gain Init Success\n\n");
return true;
}
u32
halbb_get_8852b_phy_reg_ver(void)
{
return (u32)BB_REG_RELEASE_VERSION_8852B;
}
#endif /* end of HWIMG_SUPPORT*/
3rd/devourer/hal/halbb/g6/vendor/halbb_8852b/halbb_hwimg_8852b.h
Vendored
+50
View File
@@ -0,0 +1,50 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef _HALBB_HW_IMG_8852B_H_
#define _HALBB_HW_IMG_8852B_H_
/******************************************************************************
* phy_reg.TXT
******************************************************************************/
#define DONT_CARE_8852B 0xff
#define IF_8852B 0x8
#define ELSE_IF_8852B 0x9
#define ELSE_8852B 0xa
#define END_8852B 0xb
#define CHK_8852B 0x4
bool halbb_cfg_bbcr_ax_8852b(struct bb_info *bb, bool is_form_folder,
u32 folder_len, u32 *folder_array,
enum phl_phy_idx phy_idx);
bool halbb_cfg_bb_gain_ax_8852b(struct bb_info *bb, bool is_form_folder,
u32 folder_len, u32 *folder_array);
u32 halbb_get_8852b_phy_reg_ver(void);
#endif /* end of HWIMG_SUPPORT*/
3rd/devourer/hal/halbb/g6/vendor/halbb_8852b/halbb_hwimg_raw_data_8852b.h
Vendored
+1133
View File
File diff suppressed because it is too large Load Diff
3rd/devourer/hal/halbb/g6/vendor/halbb_8852b/halbb_hwimg_raw_data_8852b_gain.h
Vendored
+31
View File
@@ -0,0 +1,31 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
/*Image2HeaderVersion: R3 2.0.1.2*/
#ifndef _HALBB_HWIMG_RAW_DATA_8852B_GAIN_H
#define _HALBB_HWIMG_RAW_DATA_8852B_GAIN_H
#endif /* _HALBB_HWIMG_RAW_DATA_8852B_GAIN_H */
3rd/devourer/hal/halbb/g6/vendor/halbb_8852b/halbb_hwimg_raw_data_8852bp.h
Vendored
+1202
View File
File diff suppressed because it is too large Load Diff
3rd/devourer/hal/halbb/g6/vendor/halbb_8852b/halbb_hwimg_raw_data_8852bpt.h
Vendored
+1288
View File
File diff suppressed because it is too large Load Diff
3rd/devourer/hal/halbb/g6/vendor/halbb_8852b/halbb_hwimg_raw_data_8852bt.h
Vendored
+1144
View File
File diff suppressed because it is too large Load Diff
3rd/devourer/hal/halbb/g6/vendor/halbb_8852b/halbb_reg_cfg_8852b.c
Vendored
+154
View File
@@ -0,0 +1,154 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "../halbb_precomp.h"
#ifdef BB_8852B_SUPPORT
void halbb_cfg_rf_reg_8852b(struct bb_info *bb, u32 addr, u32 data,
enum rf_path rf_path, u32 reg_addr)
{
}
void halbb_cfg_rf_radio_a_8852b(struct bb_info *bb, u32 addr, u32 data)
{
}
void halbb_cfg_rf_radio_b_8852b(struct bb_info *bb, u32 addr, u32 data)
{
}
void halbb_cfg_bb_phy_8852b(struct bb_info *bb, u32 addr, u32 data,
enum phl_phy_idx phy_idx)
{
#ifdef HALBB_DBCC_SUPPORT
u32 ofst = 0;
#endif
if (addr == 0xfe) {
halbb_delay_ms(bb, 50);
BB_DBG(bb, DBG_INIT, "Delay 50 ms\n");
} else if (addr == 0xfd) {
halbb_delay_ms(bb, 5);
BB_DBG(bb, DBG_INIT, "Delay 5 ms\n");
} else if (addr == 0xfc) {
halbb_delay_ms(bb, 1);
BB_DBG(bb, DBG_INIT, "Delay 1 ms\n");
} else if (addr == 0xfb) {
halbb_delay_us(bb, 50);
BB_DBG(bb, DBG_INIT, "Delay 50 us\n");
} else if (addr == 0xfa) {
halbb_delay_us(bb, 5);
BB_DBG(bb, DBG_INIT, "Delay 5 us\n");
} else if (addr == 0xf9) {
halbb_delay_us(bb, 1);
BB_DBG(bb, DBG_INIT, "Delay 1 us\n");
} else {
#ifdef HALBB_DBCC_SUPPORT
if ((bb->hal_com->dbcc_en || bb->bb_dbg_i.cr_dbg_mode_en) &&
phy_idx == HW_PHY_1) {
ofst = halbb_phy0_to_phy1_ofst(bb, addr, phy_idx);
if (ofst == 0)
return;
addr += ofst;
} else {
phy_idx = HW_PHY_0;
}
BB_DBG(bb, DBG_INIT, "[REG][%d]0x%04X = 0x%08X\n", phy_idx, addr, data);
#else
BB_DBG(bb, DBG_INIT, "[REG]0x%04X = 0x%08X\n", addr, data);
#endif
halbb_set_reg(bb, addr, MASKDWORD, data);
}
}
void halbb_cfg_bb_gain_8852b(struct bb_info *bb, u32 addr, u32 data)
{
struct bb_gain_info *gain = &bb->bb_gain_i;
u8 cfg_type = (u8)((addr & 0xff000000) >> 24);
enum bb_band_t band_idx = (enum bb_band_t)((addr & 0xff0000) >> 16);
u8 path = (u8)((addr & 0xff00) >> 8);
u8 type;
u8 i = 0;
if (band_idx >= BB_GAIN_BAND_NUM)
return;
if (path >= HALBB_MAX_PATH)
return;
if (addr == 0xfe) {
halbb_delay_ms(bb, 50);
BB_DBG(bb, DBG_INIT, "Delay 50 ms\n");
} else if (addr == 0xfd) {
halbb_delay_ms(bb, 5);
BB_DBG(bb, DBG_INIT, "Delay 5 ms\n");
} else if (addr == 0xfc) {
halbb_delay_ms(bb, 1);
BB_DBG(bb, DBG_INIT, "Delay 1 ms\n");
} else if (addr == 0xfb) {
halbb_delay_us(bb, 50);
BB_DBG(bb, DBG_INIT, "Delay 50 us\n");
} else if (addr == 0xfa) {
halbb_delay_us(bb, 5);
BB_DBG(bb, DBG_INIT, "Delay 5 us\n");
} else if (addr == 0xf9) {
halbb_delay_us(bb, 1);
BB_DBG(bb, DBG_INIT, "Delay 1 us\n");
} else if (cfg_type ==0) { /*GAIN ERROR*/
type = (u8)(addr & 0xff);
if (type == 0) {
for (i = 0; i < 4; i++)
gain->lna_gain[band_idx][path][i] = (data >> (8 * i)) & 0xff;
} else if (type == 1) {
for (i = 0; i < 3; i++)
gain->lna_gain[band_idx][path][4 + i] = (data >> (8 * i)) & 0xff;
} else if (type == 2) {
for (i = 0; i < 2; i++)
gain->tia_gain[band_idx][path][i] = (data >> (8 * i)) & 0xff;
}
if ((band_idx >= 4) && (band_idx <= 7)) { /*Avoid phy_reg_gain does not support band_idx 8~11*/
if (type == 0) {
for (i = 0; i < 4; i++)
gain->lna_gain[band_idx + 4][path][i] = (data >> (8 * i)) & 0xff;
} else if (type == 1) {
for (i = 0; i < 3; i++)
gain->lna_gain[band_idx + 4][path][4 + i] = (data >> (8 * i)) & 0xff;
} else if (type == 2) {
for (i = 0; i < 2; i++)
gain->tia_gain[band_idx + 4][path][i] = (data >> (8 * i)) & 0xff;
}
}
} else if (cfg_type == 1) { /*RPL Offset*/
halbb_cfg_bb_rpl_ofst(bb, band_idx, path, addr, data);
if ((band_idx >= 4) && (band_idx <= 7)) /*Avoid phy_reg_gain does not support band_idx 8~11*/
halbb_cfg_bb_rpl_ofst(bb, band_idx + 4, path, addr, data);
} else {
BB_WARNING("cfg_type=%d\n", cfg_type);
}
}
#endif
3rd/devourer/hal/halbb/g6/vendor/halbb_8852b/halbb_reg_cfg_8852b.h
Vendored
+34
View File
@@ -0,0 +1,34 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef _HALBB_REG_CFG_8852B_H_
#define _HALBB_REG_CFG_8852B_H_
#ifdef BB_8852B_SUPPORT
void halbb_cfg_bb_phy_8852b(struct bb_info *bb, u32 addr, u32 data,
enum phl_phy_idx phy_idx);
void halbb_cfg_bb_gain_8852b(struct bb_info *bb, u32 addr, u32 data);
#endif
#endif /* RTL8852B_SUPPORT*/
3rd/devourer/hal/halbb/g6/vendor/halbb_8852b/halbb_version_rtl8852b.h
Vendored
+30
View File
@@ -0,0 +1,30 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
/*RTL8852B BB Parameters*/
#ifndef _HALBB_VERSION_8852B_H_
#define _HALBB_VERSION_8852B_H_
#define BB_REG_RELEASE_DATE_8852B 20221220
#define BB_REG_RELEASE_VERSION_8852B 31
#endif
3rd/devourer/hal/halbb/g6/vendor/halbb_8852b/halbb_version_rtl8852bp.h
Vendored
+30
View File
@@ -0,0 +1,30 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
/*RTL8852BP BB Parameters*/
#ifndef _HALBB_VERSION_8852BP_H_
#define _HALBB_VERSION_8852BP_H_
#define BB_REG_RELEASE_DATE_8852BP 20230417
#define BB_REG_RELEASE_VERSION_8852BP 5
#endif
3rd/devourer/hal/halbb/g6/vendor/halbb_8852b/halbb_version_rtl8852bpt.h
Vendored
+30
View File
@@ -0,0 +1,30 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
/*RTL8852BPT BB Parameters*/
#ifndef _HALBB_VERSION_8852BPT_H_
#define _HALBB_VERSION_8852BPT_H_
#define BB_REG_RELEASE_DATE_8852BPT 20240223
#define BB_REG_RELEASE_VERSION_8852BPT 3
#endif
3rd/devourer/hal/halbb/g6/vendor/halbb_8852b/halbb_version_rtl8852bt.h
Vendored
+30
View File
@@ -0,0 +1,30 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
/*RTL8852BT BB Parameters*/
#ifndef _HALBB_VERSION_8852BT_H_
#define _HALBB_VERSION_8852BT_H_
#define BB_REG_RELEASE_DATE_8852BT 20240205
#define BB_REG_RELEASE_VERSION_8852BT 7
#endif
3rd/devourer/hal/halbb/g6/vendor/halbb_8852c/halbb_8852c.c
Vendored
+486
View File
@@ -0,0 +1,486 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "../halbb_precomp.h"
#ifdef BB_8852C_SUPPORT
void halbb_bfee_en_8852c(struct bb_info *bb, bool csi_en)
{
if (csi_en) {
rtw_hal_mac_ax_init_bf_role(bb->hal_com, 0, HW_PHY_0);
rtw_hal_mac_ax_init_bf_role(bb->hal_com, 0, HW_PHY_1);
} else {
rtw_hal_mac_ax_deinit_bfee(bb->hal_com, HW_PHY_0);
rtw_hal_mac_ax_deinit_bfee(bb->hal_com, HW_PHY_1);
}
}
bool halbb_chk_pkg_valid_8852c(struct bb_info *bb, u8 bb_ver, u8 rf_ver)
{
bool valid = true;
#if 0
if (bb_ver >= X && rf_ver >= Y)
valid = true;
else if (bb_ver < X && rf_ver < Y)
valid = true;
else
valid = false;
#endif
if (!valid) {
/*halbb_set_reg(bb, 0x1c3c, (BIT(0) | BIT(1)), 0x0);*/
BB_WARNING("[%s] Pkg_ver{bb, rf}={%d, %d} disable all BB block\n",
__func__, bb_ver, rf_ver);
}
return valid;
}
bool halbb_chk_tx_idle_8852c(struct bb_info *bb, enum phl_phy_idx phy_idx)
{
u8 tx_state = 0;
bool idle = false;
u32 dbg_port = 0x30002;
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
if (phy_idx == HW_PHY_1)
dbg_port = 0x30005;
if (halbb_bb_dbg_port_racing(bb, DBGPORT_PRI_3)) {
halbb_dbg_port_sel(bb, (u16)(dbg_port & 0xffff),
(u8)((dbg_port & 0xff0000) >> 16), 0x0, 0x1);
BB_DBG(bb, DBG_PHY_CONFIG,
"*Set dbg_port=(0x%x)\n", dbg_port);
} else {
dbg_port = halbb_get_bb_dbg_port_idx(bb);
BB_DBG(bb, DBG_PHY_CONFIG,
"[Set dbg_port fail!] Curr-DbgPort=0x%x\n", dbg_port);
return false;
}
/* Release DBG port */
halbb_release_bb_dbg_port(bb);
tx_state = (u8)(halbb_get_bb_dbg_port_val(bb) & 0x3f);
if (tx_state == 0)
idle = true;
else
idle = false;
return idle;
}
void halbb_stop_pmac_tx_8852c(struct bb_info *bb,
struct halbb_pmac_info *tx_info,
enum phl_phy_idx phy_idx)
{
if (tx_info->is_cck) { // CCK
if (tx_info->mode == CONT_TX) {
halbb_set_reg(bb, 0x231c, BIT(1), 1);
halbb_set_reg(bb, 0x2318, BIT(8), 0);
halbb_set_reg(bb, 0x231c, BIT(21), 0);
halbb_set_reg(bb, 0x231c, BIT(1), 0);
} else if (tx_info->mode == PKTS_TX) {
halbb_set_reg_cmn(bb, 0x9c4, BIT(4), 0, phy_idx);
} else if (tx_info->mode == CCK_CARRIER_SIPPRESSION_TX) {
halbb_set_reg_cmn(bb, 0x9c4, BIT(4), 0, phy_idx);
/*Carrier Suppress Tx*/
halbb_set_reg(bb, 0x2318, BIT(9), 0);
/*Enable scrambler at payload part*/
halbb_set_reg(bb, 0x231c, BIT(7), 0);
}
} else { // OFDM
if (tx_info->mode == CONT_TX)
halbb_set_reg_cmn(bb, 0x9c4, BIT(0), 0, phy_idx);
else if (tx_info->mode == PKTS_TX)
halbb_set_reg_cmn(bb, 0x9c4, BIT(4), 0, phy_idx);
}
}
void halbb_start_pmac_tx_8852c(struct bb_info *bb,
struct halbb_pmac_info *tx_info,
enum halbb_pmac_mode mode, u32 pkt_cnt,u16 period,
enum phl_phy_idx phy_idx)
{
if (mode == CONT_TX) {
if (tx_info->is_cck) {
halbb_set_reg(bb, 0x2318, BIT(8), 1);
halbb_set_reg(bb, 0x231c, BIT(21), 1);
} else {
halbb_set_reg_cmn(bb, 0x9c4, BIT(0), 1, phy_idx);
}
} else if (mode == PKTS_TX) {
/*Tx_N_PACKET_EN */
halbb_set_reg_cmn(bb, 0x9c4, BIT(4), 1, phy_idx);
/*Tx_N_PERIOD */
halbb_set_reg_cmn(bb, 0x9c4, 0xffffff00, period, phy_idx);
/*Tx_N_PACKET */
halbb_set_reg_cmn(bb, 0x9c8, 0xffffffff, pkt_cnt, phy_idx);
} else if (mode == CCK_CARRIER_SIPPRESSION_TX) {
if (tx_info->is_cck) {
/*Carrier Suppress Tx*/
halbb_set_reg(bb, 0x2318, BIT(9), 1);
/*Disable scrambler at payload part*/
halbb_set_reg(bb, 0x231c, BIT(7), 1);
} else {
return;
}
/*Tx_N_PACKET_EN */
halbb_set_reg_cmn(bb, 0x9c4, BIT(4), 1, phy_idx);
/*Tx_N_PERIOD */
halbb_set_reg_cmn(bb, 0x9c4, 0xffffff00, period, phy_idx);
/*Tx_N_PACKET */
halbb_set_reg_cmn(bb, 0x9c8, 0xffffffff, pkt_cnt, phy_idx);
}
/*Tx_EN */
halbb_set_reg_cmn(bb, 0x9c0, BIT(0), 1, phy_idx);
halbb_set_reg_cmn(bb, 0x9c0, BIT(0), 0, phy_idx);
}
void halbb_set_pmac_tx_8852c(struct bb_info *bb_0, struct halbb_pmac_info *tx_info,
enum phl_phy_idx phy_idx)
{
struct bb_info *bb = bb_0;
#ifdef HALBB_DBCC_SUPPORT
HALBB_GET_PHY_PTR(bb_0, bb, phy_idx);
#endif
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
if (!tx_info->en_pmac_tx) {
halbb_stop_pmac_tx_8852c(bb, tx_info, phy_idx);
/* PD hit enable */
halbb_set_reg_cmn(bb, 0xc3c, BIT(9), 0, phy_idx);
if (bb->bb_ch_i.is_2g)
halbb_set_reg(bb, 0x2320, BIT(0), 0);
return;
}
/*Turn on PMAC */
/* Tx */
halbb_set_reg_cmn(bb, 0x0980, BIT(0), 1, phy_idx);
/* Rx */
halbb_set_reg_cmn(bb, 0x0980, BIT(16), 1, phy_idx);
halbb_set_reg_cmn(bb, 0x0988, 0x3f, 0x3f, phy_idx);
/* PD hit enable */
halbb_set_reg_cmn(bb, 0x704, BIT(1), 0, phy_idx);
halbb_set_reg_cmn(bb, 0xc3c, BIT(9), 1, phy_idx);
if (tx_info->cck_lbk_en) {
halbb_set_reg(bb, 0x2320, BIT(0), 0);
} else {
if (bb->bb_ch_i.is_2g)
halbb_set_reg(bb, 0x2320, BIT(0), 1);
}
halbb_set_reg_cmn(bb, 0x704, BIT(1), 1, phy_idx);
halbb_start_pmac_tx_8852c(bb, tx_info, tx_info->mode, tx_info->tx_cnt,
tx_info->period, phy_idx);
BB_DBG(bb, DBG_PHY_CONFIG, "[PMAC Tx] cck_lbk_en=%d\n", tx_info->cck_lbk_en);
}
void halbb_set_tmac_tx_8852c(struct bb_info *bb, enum phl_phy_idx phy_idx)
{
/* To do: 0x0d80[16] [25] / 0x0d88[5:0] Should be set to default value in parameter package*/
/* Turn on TMAC */
halbb_set_reg_cmn(bb, 0x0980, BIT(0), 0, phy_idx);
halbb_set_reg_cmn(bb, 0x0980, BIT(16), 0, phy_idx);
halbb_set_reg_cmn(bb, 0x0988, 0xfff, 0, phy_idx);
halbb_set_reg_cmn(bb, 0x0994, 0xf0, 0, phy_idx);
// PDP bypass from TMAC
halbb_set_reg_cmn(bb, 0x09a4, BIT(10), 0, phy_idx);
// TMAC Tx path
halbb_set_reg_cmn(bb, 0x09a4, 0x1c, 0, phy_idx);
// TMAC Tx power
halbb_set_reg_cmn(bb, 0x09a4, BIT(16), 0, phy_idx);
// TMAC Tx OFDM triangular shaping filter
halbb_set_reg_cmn(bb, 0x09a4, BIT(31), 0, phy_idx);
}
void halbb_dpd_bypass_8852c(struct bb_info *bb, bool pdp_bypass,
enum phl_phy_idx phy_idx)
{
halbb_set_reg_cmn(bb, 0x09a4, BIT(10), 1, phy_idx);
halbb_set_reg_cmn(bb, 0x45b8, BIT(16), pdp_bypass, phy_idx);
}
void halbb_ic_hw_setting_init_8852c(struct bb_info *bb)
{
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
//Set dbcc_80p80_sel_evm_rpt_en
halbb_set_reg(bb, 0xa10, BIT(0), 1);
halbb_set_reg(bb, 0x2a10, BIT(0), 1);
if (bb->hal_com->cv != CAV) {
//set minimum UL txpwr requirement to -10dBm
halbb_write_mask_pwr_reg_cmn(bb, HW_PHY_0, 0xd240, 0x3fe00, 0x1d8);
halbb_write_mask_pwr_reg_cmn(bb, HW_PHY_1, 0xd240, 0x3fe00, 0x1d8);
//set UL txpwr compensation to 0dB
halbb_write_mask_pwr_reg_cmn(bb, HW_PHY_0, 0xd290, 0xff, 0);
halbb_write_mask_pwr_reg_cmn(bb, HW_PHY_1, 0xd290, 0xff, 0);
}
}
void halbb_ic_hw_setting_8852c(struct bb_info *bb)
{
bool btg_en;
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
btg_en = (bb->hal_com->band[0].cur_chandef.band == BAND_ON_24G) &&
((bb->rx_path == RF_PATH_B) || (bb->rx_path == RF_PATH_AB)) ? true : false;
if (btg_en && bb->bb_link_i.is_linked && (bb->bb_ch_i.rssi_min < (75 << 1))) {// if rssi < -35 dbm
halbb_set_reg(bb, 0x4aa4, BIT(18), 0x0);
BB_DBG(bb, DBG_PHY_CONFIG, "[BT] BTG enable, Is linked\n");
BB_DBG(bb, DBG_PHY_CONFIG, "[BT][RSSI] rssi_min=0x%x\n", bb->bb_ch_i.rssi_min >> 1);
} else {
halbb_set_reg(bb, 0x4aa4, BIT(18), 0x1);
BB_DBG(bb, DBG_PHY_CONFIG, "[BT] btg_en=%d, is_linked=%d\n", btg_en, bb->bb_link_i.is_linked);
BB_DBG(bb, DBG_PHY_CONFIG, "[BT][RSSI] rssi_min=0x%x\n", bb->bb_ch_i.rssi_min >> 1);
}
}
bool halbb_set_pd_lower_bound_8852c(struct bb_info *bb, u8 bound,
enum channel_width bw,
enum phl_phy_idx phy_idx)
{
/*
Range of bound value:
BW20: 95~33
BW40: 92~30
BW80: 89~27
*/
#ifdef HALBB_DIG_TDMA_SUPPORT
struct bb_dig_info *bb_dig = &bb->bb_dig_i;
struct bb_dig_op_unit *bb_dig_u = bb_dig->p_cur_dig_unit;
#endif
u8 bw_attenuation = 0;
u8 subband_filter_atteniation = 7;
u8 bound_idx = 0;
bool rpt = true;
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
if (bound == 0) {
halbb_set_reg_cmn(bb, 0x481C, BIT(29), 0, phy_idx);
BB_DBG(bb, DBG_PHY_CONFIG,
"[PD Bound] Set Boundary to default!\n");
return true;
}
bb->bb_cmn_backup_i.cur_pd_lower_bound = bound;
if ((bw == CHANNEL_WIDTH_20) || (bw == CHANNEL_WIDTH_10) || (bw == CHANNEL_WIDTH_5)) {
bw_attenuation = 0;
} else if (bw == CHANNEL_WIDTH_40) {
bw_attenuation = 3;
} else if (bw == CHANNEL_WIDTH_80) {
bw_attenuation = 6;
} else if (bw == CHANNEL_WIDTH_160) {
bw_attenuation = 9;
} else {
BB_DBG(bb, DBG_PHY_CONFIG,
"[PD Bound] Only support BW5/10/20/40/80/160 !\n");
return false;
}
bound += (bw_attenuation + subband_filter_atteniation);
// If Boundary dbm is odd, set it to even number
bound = bound % 2 ? bound + 1 : bound;
if (bound < 40) {
BB_DBG(bb, DBG_PHY_CONFIG,
"[PD Bound] Threshold too high, set to highest level!\n");
bound = 40;
rpt = false;
}
if (bound > 102) {
BB_DBG(bb, DBG_PHY_CONFIG,
"[PD Bound] Threshold too low, disable PD lower bound function!\n");
halbb_set_reg_cmn(bb, 0x481C, BIT(29), 0, phy_idx);
return true;
}
bound_idx = (102 - bound) >> 1;
halbb_set_reg_cmn(bb, 0x481C, 0x7c0, bound_idx, phy_idx);
halbb_set_reg_cmn(bb, 0x481C, BIT(29), 1, phy_idx);
BB_DBG(bb, DBG_PHY_CONFIG, "[PD Bound] Set Boundary Success!\n");
#ifdef HALBB_DIG_TDMA_SUPPORT
if ((bb_dig->dig_mode != DIG_TDMA) && (bb_dig->dig_mode != DIG_TDMA_ADV))
return rpt;
if (bb_dig_u->state_identifier == DIG_TDMA_LOW)
bb_dig->dig_state_l_i.pd_low_th = bound;
else
bb_dig->dig_state_h_i.pd_low_th = bound;
#endif
return rpt;
}
bool halbb_set_pd_lower_bound_cck_8852c(struct bb_info *bb, u8 bound,
enum channel_width bw,
enum phl_phy_idx phy_idx)
{
#ifdef HALBB_DIG_TDMA_SUPPORT
struct bb_dig_info *bb_dig = &bb->bb_dig_i;
struct bb_dig_op_unit *bb_dig_u = bb_dig->p_cur_dig_unit;
#endif
struct bb_scan_h2c_info *scan_ofld = &bb->bb_scan_h2c_i;
u8 bw_attenuation = 0;
u8 subband_filter_atteniation = 5;
s8 bound_tmp = 0;
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
if (bound == 0 && scan_ofld->scan_mode != BB_P2P_SCAN) {
halbb_set_reg_cmn(bb, 0x4b74, BIT(30), 0, phy_idx);
BB_DBG(bb, DBG_PHY_CONFIG,
"[PD Bound] Set Boundary to default!\n");
return true;
}
if ((bw == CHANNEL_WIDTH_20) || (bw == CHANNEL_WIDTH_10) || (bw == CHANNEL_WIDTH_5)) {
bw_attenuation = 0;
} else if (bw == CHANNEL_WIDTH_40) {
bw_attenuation = 3;
} else if (bw == CHANNEL_WIDTH_80) {
bw_attenuation = 6;
} else if (bw == CHANNEL_WIDTH_160) {
bw_attenuation = 9;
} else {
BB_DBG(bb, DBG_PHY_CONFIG,
"[PD Bound] Only support BW5/10/20/40/80/160 !\n");
return false;
}
bound += (bw_attenuation + subband_filter_atteniation);
bound_tmp = (-1) * MIN_2(bound, 128);
halbb_set_reg_cmn(bb, 0x4b64, 0xff000000, bound_tmp, phy_idx);
halbb_set_reg_cmn(bb, 0x4b64, 0xff0000, 0x7f, phy_idx);
halbb_set_reg_cmn(bb, 0x4b74, BIT(30), 1, phy_idx);
BB_DBG(bb, DBG_PHY_CONFIG, "[PD Bound] Set CCK Boundary Success!\n");
#ifdef HALBB_DIG_TDMA_SUPPORT
if ((bb_dig->dig_mode != DIG_TDMA) && (bb_dig->dig_mode != DIG_TDMA_ADV))
return true;
if (bb_dig_u->state_identifier == DIG_TDMA_LOW)
bb_dig->dig_state_l_i.rssi_nocca_low_th= bound_tmp;
else
bb_dig->dig_state_h_i.rssi_nocca_low_th = bound_tmp;
#endif
return true;
}
u8 halbb_querry_pd_lower_bound_8852c(struct bb_info *bb, bool get_en_info, enum phl_phy_idx phy_idx)
{
u8 tmp;
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
if (get_en_info)
tmp = (u8)halbb_get_reg_cmn(bb, 0x481C, BIT(29), phy_idx);
else
tmp = bb->bb_cmn_backup_i.cur_pd_lower_bound;
return tmp;
}
void halbb_pop_en_8852c(struct bb_info *bb, bool en, enum phl_phy_idx phy_idx)
{
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
if (en) {
halbb_set_reg_cmn(bb, 0x4798, BIT(8), 1, phy_idx);
halbb_set_reg_cmn(bb, 0xc54, 0x6, 0, phy_idx);
halbb_set_reg_cmn(bb, 0xc68, 0xff, 0x50, phy_idx);
halbb_set_reg_cmn(bb, 0x4794, 0xF8000, 0xc, phy_idx);
halbb_set_reg_cmn(bb, 0x4794, 0x1F00000, 8, phy_idx);
halbb_set_reg_cmn(bb, 0x4798, BIT(9), 0, phy_idx);
} else {
halbb_set_reg_cmn(bb, 0x4798, BIT(8), 0, phy_idx);
}
}
bool halbb_querry_pop_en_8852c(struct bb_info *bb, enum phl_phy_idx phy_idx)
{
bool en;
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
en = (bool)halbb_get_reg_cmn(bb, 0x4798, BIT(8), phy_idx);
return en;
}
u16 halbb_get_per_8852c(struct bb_info *bb, enum phl_phy_idx phy_idx)
{
u16 per;
u32 crc_ok, crc_err, brk_cnt;
u32 numer, denomer;
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
crc_ok = halbb_mp_get_rx_crc_ok(bb, phy_idx);
crc_err = halbb_mp_get_rx_crc_err(bb, phy_idx);
brk_cnt = halbb_get_reg_cmn(bb, 0x1a08, MASKHWORD, phy_idx);
if ((crc_ok > 0xffff) || (crc_err > 0xffff)) {
BB_DBG(bb, DBG_DBG_API, "[PER] Value > Brk cnt upper bound!\n");
return 0xffff;
}
denomer = crc_ok + crc_err + brk_cnt;
numer = crc_err + brk_cnt + (denomer >> 1);
per = (u16)HALBB_DIV(numer * 100, denomer);
return per;
}
u8 halbb_get_losel_8852c(struct bb_info *bb)
{
u8 tmp = 0;
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
tmp = (u8)halbb_get_reg(bb, 0x35c, BIT(11) | BIT(10));
return tmp;
}
#endif
3rd/devourer/hal/halbb/g6/vendor/halbb_8852c/halbb_8852c.h
Vendored
+57
View File
@@ -0,0 +1,57 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_8852C_H__
#define __HALBB_8852C_H__
#ifdef BB_8852C_SUPPORT
#include "../halbb_pmac_setting_ex.h"
struct bb_info;
void halbb_bfee_en_8852c(struct bb_info *bb, bool csi_en);
bool halbb_chk_pkg_valid_8852c(struct bb_info *bb, u8 bb_ver, u8 rf_ver);
void halbb_set_pmac_tx_8852c(struct bb_info *bb, struct halbb_pmac_info *tx_info,
enum phl_phy_idx phy_idx);
void halbb_set_tmac_tx_8852c(struct bb_info *bb, enum phl_phy_idx phy_idx);
void halbb_dpd_bypass_8852c(struct bb_info *bb, bool pdp_bypass,
enum phl_phy_idx phy_idx);
void halbb_ic_hw_setting_init_8852c(struct bb_info *bb);
void halbb_ic_hw_setting_8852c(struct bb_info *bb);
bool halbb_set_pd_lower_bound_8852c(struct bb_info *bb, u8 bound,
enum channel_width bw,
enum phl_phy_idx phy_idx);
bool halbb_set_pd_lower_bound_cck_8852c(struct bb_info *bb, u8 bound,
enum channel_width bw,
enum phl_phy_idx phy_idx);
u8 halbb_querry_pd_lower_bound_8852c(struct bb_info *bb, bool get_en_info,
enum phl_phy_idx phy_idx);
void halbb_pop_en_8852c(struct bb_info *bb, bool en, enum phl_phy_idx phy_idx);
bool halbb_querry_pop_en_8852c(struct bb_info *bb, enum phl_phy_idx phy_idx);
u16 halbb_get_per_8852c(struct bb_info *bb, enum phl_phy_idx phy_idx);
u8 halbb_get_losel_8852c(struct bb_info *bb);
bool halbb_chk_tx_idle_8852c(struct bb_info *bb, enum phl_phy_idx phy_idx);
#endif
#endif /* __HALBB_8852C_H__ */
3rd/devourer/hal/halbb/g6/vendor/halbb_8852c/halbb_8852c_api.c
Vendored
+4369
View File
File diff suppressed because it is too large Load Diff
3rd/devourer/hal/halbb/g6/vendor/halbb_8852c/halbb_8852c_api.h
Vendored
+290
View File
@@ -0,0 +1,290 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_8852C_API_H__
#define __HALBB_8852C_API_H__
#ifdef BB_8852C_SUPPORT
#include "../halbb_api.h"
/*@--------------------------[Define]-------------------------------------*/
#define INVALID_RF_DATA 0xffffffff
#define BB_PATH_MAX_8852C 2
#define HE_N_USER_MAX_8852C 8
#define GAIN_HIDE_EFUSE_START_ADDR_8852C 0x585
#define GAIN_HIDE_EFUSE_A_2G_8852C 0x5BB
#define GAIN_HIDE_EFUSE_A_5GL_8852C 0x5BA
#define GAIN_HIDE_EFUSE_A_5GM_8852C 0x5B9
#define GAIN_HIDE_EFUSE_A_5GH_8852C 0x5B8
#define GAIN_HIDE_EFUSE_A_6GH_0_8852C 0x5B7
#define GAIN_HIDE_EFUSE_A_6GH_1_8852C 0x5B6
#define GAIN_HIDE_EFUSE_A_6GH_2_8852C 0x5B5
#define GAIN_HIDE_EFUSE_A_6GH_3_8852C 0x5B4
#define GAIN_HIDE_EFUSE_A_6GH_4_8852C 0x5B3
#define GAIN_HIDE_EFUSE_A_6GH_5_8852C 0x5B2
#define GAIN_HIDE_EFUSE_A_6GH_6_8852C 0x5B1
#define GAIN_HIDE_EFUSE_A_6GH_7_8852C 0x5B0
#define GAIN_HIDE_EFUSE_B_2G_8852C 0x590
#define GAIN_HIDE_EFUSE_B_5GL_8852C 0x58F
#define GAIN_HIDE_EFUSE_B_5GM_8852C 0x58E
#define GAIN_HIDE_EFUSE_B_5GH_8852C 0x58D
#define GAIN_HIDE_EFUSE_B_6GH_0_8852C 0x58C
#define GAIN_HIDE_EFUSE_B_6GH_1_8852C 0x58B
#define GAIN_HIDE_EFUSE_B_6GH_2_8852C 0x58A
#define GAIN_HIDE_EFUSE_B_6GH_3_8852C 0x589
#define GAIN_HIDE_EFUSE_B_6GH_4_8852C 0x588
#define GAIN_HIDE_EFUSE_B_6GH_5_8852C 0x587
#define GAIN_HIDE_EFUSE_B_6GH_6_8852C 0x586
#define GAIN_HIDE_EFUSE_B_6GH_7_8852C 0x585
/*@--------------------------[Feature]---------------------------------------*/
/*@--------------------------[Enum]------------------------------------------*/
/*@--------------------------[Structure]-------------------------------------*/
struct bb_h2c_lps_info_8852c {
u8 central_ch;
u8 pri_ch;
u8 bw;
u8 band_type;
};
/*@--------------------------[Prptotype]-------------------------------------*/
struct bb_info;
u8 halbb_ex_evm_1ss_report_8852c(struct bb_info *bb);
u8 halbb_ex_evm_max_report_8852c(struct bb_info *bb);
u8 halbb_ex_evm_min_report_8852c(struct bb_info *bb);
bool halbb_set_vht_mu_user_idx_8852c(struct bb_info *bb, bool en, u8 idx,
enum phl_phy_idx phy_idx);
bool halbb_set_pwr_ul_tb_ofst_8852c(struct bb_info *bb,
s8 pw_ofst, enum phl_phy_idx phy_idx);
bool halbb_lps_info_8852c(struct bb_info *bb, u16 mac_id);
bool halbb_lps_cmn_info_8852c(struct bb_info *bb);
void halbb_digital_cfo_comp_8852c(struct bb_info *bb, s32 curr_cfo);
void halbb_tx_triangular_shap_cfg_8852c(struct bb_info *bb, u8 shape_idx,
enum phl_phy_idx phy_idx);
void halbb_set_digital_pwr_comp_8852c(struct bb_info *bb, bool en,
enum phl_phy_idx phy_idx);
void halbb_tx_dfir_shap_cck_8852c(struct bb_info *bb, u8 ch, u8 shape_idx,
enum phl_phy_idx phy_idx);
bool halbb_ctrl_bw_ch_8852c(struct bb_info *bb, u8 pri_ch, u8 central_ch,
enum channel_width bw, enum band_type band,
enum phl_phy_idx phy_idx);
void halbb_1r_cca_cr_cfg_8852c(struct bb_info *bb, enum rf_path rx_path);
bool halbb_ctrl_rx_path_8852c(struct bb_info *bb, enum rf_path rx_path, bool dbcc_en);
bool halbb_ctrl_tx_path_pmac_8852c(struct bb_info *bb, enum rf_path tx_path, bool dbcc_en);
bool halbb_ctrl_tx_path_tmac_8852c(struct bb_info *bb, enum rf_path tx_path_1sts, bool dbcc_en);
bool halbb_ctrl_tx_path_8852c(struct bb_info *bb, enum rf_path tx_path);
#ifdef HALBB_PWR_CTRL_SUPPORT
void halbb_tssi_ctrl_set_dbw_table_8852c(struct bb_info *bb);
#endif
#if 0
bool halbb_cfg_rx_path_8852c(struct bb_info *bb, enum rf_path rx_path,
u8 rx_nss, enum phl_phy_idx phy_idx);
bool halbb_cfg_tx_path_8852c(struct bb_info *bb, enum rf_path tx_path,
u8 tx_nss,enum phl_phy_idx phy_idx);
#endif
u32 halbb_phy0_to_phy1_ofst_8852c(struct bb_info *bb, u32 addr);
void halbb_gpio_ctrl_dump_8852c(struct bb_info *bb);
void halbb_gpio_rfm_8852c(struct bb_info *bb, enum bb_path path,
enum bb_rfe_src_sel src, bool dis_tx_gnt_wl,
bool active_tx_opt, bool act_bt_en, u8 rfm_output_val);
void halbb_gpio_trsw_table_8852c(struct bb_info *bb, enum bb_path path,
bool path_en, bool trsw_tx,
bool trsw_rx, bool trsw, bool trsw_b);
void halbb_gpio_setting_8852c(struct bb_info *bb, u8 gpio_idx,
enum bb_path path, bool inv,
enum bb_rfe_src_sel src);
void halbb_gpio_setting_all_8852c(struct bb_info *bb, u8 rfe_idx);
void halbb_gpio_setting_init_8852c(struct bb_info *bb);
void halbb_bb_reset_8852c(struct bb_info *bb, enum phl_phy_idx phy_idx);
u32 halbb_read_rf_reg_8852c(struct bb_info *bb, enum rf_path path, u32 reg_addr,
u32 bit_mask);
bool halbb_write_rf_reg_8852c(struct bb_info *bb, enum rf_path path, u32 reg_addr,
u32 bit_mask, u32 data);
bool halbb_spur_location_8852c(struct bb_info *bb, u8 central_ch,
enum channel_width bw, enum band_type band,
u32 *intf);
bool halbb_spur_location_for_CSI_8852c(struct bb_info *bb, u8 central_ch,
enum channel_width bw, enum band_type band,
u32 *intf);
bool halbb_ctrl_bw_8852c(struct bb_info *bb, u8 pri_ch, enum channel_width bw,
bool is_efem, enum phl_phy_idx phy_idx);
bool halbb_query_cck_en_8852c(struct bb_info *bb, enum phl_phy_idx phy_idx,
u8 func_idx);
void halbb_ctrl_cck_en_8852c(struct bb_info *bb, bool cck_en,
enum phl_phy_idx phy_idx, u8 func_idx);
u16 halbb_cfg_cmac_tx_ant_8852c(struct bb_info *bb, enum rf_path tx_path);
void halbb_ctrl_trx_path_8852c(struct bb_info *bb, enum rf_path tx_path,
u8 tx_nss, enum rf_path rx_path, u8 rx_nss);
#if 0
void halbb_cfg_trx_path_8852c(struct bb_info *bb, enum rf_path tx_path,
u8 tx_nss, enum rf_path rx_path, u8 rx_nss,
enum phl_phy_idx phy_idx, bool tmac_en);
#endif
void halbb_dfs_en_8852c(struct bb_info *bb, bool en);
void halbb_adc_en_8852c(struct bb_info *bb, bool en, enum phl_phy_idx phy_idx);
void halbb_tssi_cont_en_8852c(struct bb_info *bb, bool en, enum rf_path path);
void halbb_bb_reset_en_8852c(struct bb_info *bb, bool en, enum phl_phy_idx phy_idx);
void halbb_fix_rx_htmcs0_8852c(struct bb_info *bb, bool en, enum phl_phy_idx phy_idx);
void halbb_tssi_bb_reset_8852c(struct bb_info *bb);
bool halbb_ctrl_sco_cck_8852c(struct bb_info *bb, u8 pri_ch);
bool halbb_adc_cfg_8852c(struct bb_info *bb, enum channel_width bw, bool is_efem,
enum rf_path path);
void halbb_ctrl_rf_mode_8852c(struct bb_info *bb, enum phl_rf_mode mode);
bool halbb_ctrl_ch2_80p80_8852c(struct bb_info *bb, u8 central_ch);
#ifdef HALBB_DBCC_SUPPORT
void halbb_ctrl_dbcc_8852c(struct bb_info *bb, bool dbcc_en);
void halbb_cfg_dbcc_cck_phy_map_8852c(struct bb_info *bb, bool dbcc_en,
enum phl_phy_idx cck_phy_map);
void halbb_cfg_dbcc_8852c(struct bb_info *bb, struct bb_dbcc_cfg_info *cfg);
#endif
void halbb_ctrl_rx_cca_8852c(struct bb_info *bb, bool cca_en, enum phl_phy_idx phy_idx);
void halbb_ctrl_ofdm_en_8852c(struct bb_info *bb, bool ofdm_en,
enum phl_phy_idx phy_idx);
bool halbb_set_txpwr_dbm_8852c(struct bb_info *bb, s16 power_dbm,
enum phl_phy_idx phy_idx);
void halbb_reset_bb_hw_cnt_8852c(struct bb_info *bb);
s16 halbb_get_txpwr_dbm_8852c(struct bb_info *bb, enum phl_phy_idx phy_idx);
s16 halbb_get_txinfo_txpwr_dbm_8852c(struct bb_info *bb);
bool halbb_set_cck_txpwr_idx_8852c(struct bb_info *bb, u16 power_idx,
enum rf_path tx_path);
u16 halbb_get_cck_txpwr_idx_8852c(struct bb_info *bb, enum rf_path tx_path);
s16 halbb_get_cck_ref_dbm_8852c(struct bb_info *bb, enum rf_path tx_path);
bool halbb_set_ofdm_txpwr_idx_8852c(struct bb_info *bb, u16 power_idx,
enum rf_path tx_path);
u16 halbb_get_ofdm_txpwr_idx_8852c(struct bb_info *bb, enum rf_path tx_path);
s16 halbb_get_ofdm_ref_dbm_8852c(struct bb_info *bb, enum rf_path tx_path);
void halbb_backup_info_8852c(struct bb_info *bb, enum phl_phy_idx phy_idx);
void halbb_restore_info_8852c(struct bb_info *bb, enum phl_phy_idx phy_idx);
bool halbb_cfg_lbk_8852c(struct bb_info *bb, bool lbk_en, bool is_dgt_lbk,
enum rf_path tx_path, enum rf_path rx_path,
enum channel_width bw, enum phl_phy_idx phy_idx);
bool halbb_cfg_lbk_cck_8852c(struct bb_info *bb, bool lbk_en, bool is_dgt_lbk,
enum rf_path tx_path, enum rf_path rx_path,
enum channel_width bw, enum phl_phy_idx phy_idx);
void halbb_ctrl_btg_8852c(struct bb_info *bb, bool btg);
void halbb_ctrl_btc_preagc_8852c(struct bb_info *bb, bool bt_en);
bool halbb_set_txsc_8852c(struct bb_info *bb, u8 txsc, enum phl_phy_idx phy_idx);
bool halbb_set_bss_color_8852c(struct bb_info *bb, u8 bss_color,
enum phl_phy_idx phy_idx);
bool halbb_set_sta_id_8852c(struct bb_info *bb, u16 sta_id,
enum phl_phy_idx phy_idx);
void halbb_set_igi_8852c(struct bb_info *bb, u8 lna_idx, bool tia_idx,
u8 rxbb_idx, enum rf_path path);
void halbb_set_tx_pow_per_path_lmt_8852c(struct bb_info *bb, s16 pwr_lmt_a, s16 pwr_lmt_b);
void halbb_set_tx_pow_ref_8852c(struct bb_info *bb, s16 pw_dbm_ofdm, /*s(9,2)*/
s16 pw_dbm_cck, s8 ofst,
u8 base_cw_0db, u16 tssi_16dBm_cw,
u16 *ofdm_cw, u16 *cck_cw,
enum phl_phy_idx phy_idx);
void halbb_dump_bb_reg_8852c(struct bb_info *bb, u32 *_used, char *output,
u32 *_out_len, bool dump_2_buff, enum bb_frc_phy_dump_reg frc_phy_dump);
void halbb_dbgport_dump_all_8852c(struct bb_info *bb, u32 *_used, char *output,
u32 *_out_len);
void halbb_physts_brk_fail_pkt_rpt_8852c(struct bb_info *bb, bool enable,
enum phl_phy_idx phy_idx);
bool halbb_rf_write_bb_reg_8852c(struct bb_info *bb, u32 addr, u32 mask, u32 data);
void halbb_pre_agc_en_8852c(struct bb_info *bb, bool enable);
void halbb_agc_fix_gain_8852c(struct bb_info *bb, bool enable, enum rf_path path);
void halbb_agc_elna_idx_8852c(struct bb_info *bb, bool elna_idx, enum rf_path path);
void halbb_agc_tia_shrink_8852c(struct bb_info *bb, bool shrink_en,
bool shrink_init, enum rf_path path);
void halbb_agc_step_en_8852c(struct bb_info *bb, bool pre_pd_agc_en,
bool linear_agc_en, bool post_pd_agc_en,
bool nlgc_agc_en, enum rf_path path);
void halbb_get_efuse_ofst_init_8852c(struct bb_info *bb);
void halbb_get_normal_efuse_init_8852c(struct bb_info *bb);
void halbb_get_hidden_efuse_init_8852c(struct bb_info *bb);
void halbb_set_hidden_efuse_8852c(struct bb_info *bb, u8 central_ch, enum band_type band_type, bool is_efem, enum rf_path path);
void halbb_set_normal_efuse_8852c(struct bb_info *bb, u8 central_ch, enum band_type band_type, enum rf_path path);
void halbb_set_gain_cr_init_8852c(struct bb_info *bb);
void halbb_set_gain_error_8852c(struct bb_info *bb, u8 central_ch, enum band_type band, bool is_efem, enum rf_path path);
void halbb_set_rxsc_rpl_comp_8852c(struct bb_info* bb, u8 central_ch, enum band_type band_type);
void halbb_normal_efuse_verify_8852c(struct bb_info *bb, s8 rx_gain_offset,
enum rf_path rx_path,
enum phl_phy_idx phy_idx);
void halbb_normal_efuse_verify_cck_8852c(struct bb_info *bb, s8 rx_gain_offset,
enum rf_path rx_path,
enum phl_phy_idx phy_idx);
void halbb_show_gain_err_8852c(struct bb_info *bb, char input[][16],
u32 *_used, char *output, u32 *_out_len);
void halbb_rx_op1db_dbg_8852c(struct bb_info *bb, char input[][16],
u32 *_used, char *output, u32 *_out_len);
void halbb_clk_en_8852c(struct bb_info *bb, bool en, enum phl_phy_idx phy_idx);
void halbb_pwr_en_8852c(struct bb_info *bb, bool en);
#endif
#endif
3rd/devourer/hal/halbb/g6/vendor/halbb_8852c/halbb_8852c_api_ex.h
Vendored
+34
View File
@@ -0,0 +1,34 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_8852C_API_EX_H__
#define __HALBB_8852C_API_EX_H__
#ifdef BB_8852C_SUPPORT
/*@--------------------------[Prptotype]-------------------------------------*/
struct bb_info;
#endif
#endif /* __INC_PHYDM_API_H_8852C__ */
3rd/devourer/hal/halbb/g6/vendor/halbb_8852c/halbb_8852c_dcra.h
Vendored
+78
View File
@@ -0,0 +1,78 @@
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HALBB_XBOX_RA_H_
#define _HALBB_XBOX_RA_H_
#ifdef BB_8852C_SUPPORT
#ifdef HALBB_DCRA_EN
/*@--------------------------[Define] ---------------------------------------*/
#define RATE_UP_TH 7
enum highest_mcs {
L0_HIGHEST_MCS = 0x82,
L1_HIGHEST_MCS = 0x83,
L2_HIGHEST_MCS = 0x86,
L3_HIGHEST_MCS = 0x87
};
enum power_setting {
power_boost = 0x1E,
non_power_boost = 0x14
};
enum msft_rate {
MCS0 = 0x0,
MCS1 = 0x1,
MCS2 = 0x2,
MCS3 = 0x3,
MCS4 = 0x4,
MCS5 = 0x5,
MCS6 = 0x6,
MCS7 = 0x7,
MCS8 = 0x8,
MCS9 = 0x9
};
/*@--------------------------[Structure]-------------------------------------*/
struct bb_category_info {
u8 total;
u8 pkt_ok_num;
u8 boost_pwr: 4;
u8 rate_down_flag: 4;
u8 rate_up_cnt;
u16 initial_rate;
u16 absolute_highest_mcs;
u16 report_highest_success_mcs;
u16 report_lowest_fail_mcs;
u32 start_time;
};
/*@--------------------------[Prptotype]-------------------------------------*/
void halbb_upt_mcs_table(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i, struct rtw_xpltfm_mcs_table *mcs_table);
void halbb_category_init(bb, bb_category);
void halbb_mcs_info_parsing(struct bb_info *bb, struct bb_category_info *category, struct rtw_phl_stainfo_t *phl_sta_i, struct rtw_xpltfm_mcs_table *mcs_table);
void halbb_tx_report_parsing(struct bb_info *bb, struct bb_category_info *category, struct rtw_phl_stainfo_t *phl_sta_i);
void halbb_rate_decision(struct bb_info *bb, struct bb_category_info *category, struct rtw_xpltfm_mcs_table *mcs_table);
void halbb_rate_down(struct bb_info *bb, struct bb_category_info *category, struct rtw_xpltfm_mcs_table *mcs_table, u8 length_category);
void halbb_rate_up(struct bb_info *bb, struct bb_category_info *category, struct rtw_xpltfm_mcs_table *mcs_table, u8 length_category);
void halbb_modify_timer(struct bb_info *bb, struct bb_category_info *category, struct rtw_phl_stainfo_t *phl_sta_i);
u8 halbb_arfr_table(struct bb_info *bb, u16 init_rate, u8 switch_table);
#endif
#endif
#endif
3rd/devourer/hal/halbb/g6/vendor/halbb_8852c/halbb_8852c_dcra_ex.h
Vendored
+34
View File
@@ -0,0 +1,34 @@
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HALBB_XBOX_RA_EX_H_
#define _HALBB_XBOX_RA_EX_H_
#ifdef BB_8852C_SUPPORT
/*@--------------------------[Define] ---------------------------------------*/
/*@--------------------------[Enum]------------------------------------------*/
/*@--------------------------[Structure]-------------------------------------*/
struct rtw_xpltfm_mcs_table;
/*@--------------------------[Prptotype]-------------------------------------*/
void halbb_upt_mcs_table(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i, struct rtw_xpltfm_mcs_table *mcs_table);
u8 halbb_arfr_table(struct bb_info *bb, u16 init_rate, u8 switch_table);
#endif
#endif
3rd/devourer/hal/halbb/g6/vendor/halbb_8852c/halbb_8852c_fwofld_api.h
Vendored
+62
View File
@@ -0,0 +1,62 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_8852C_FWOFLD_API_H__
#define __HALBB_8852C_FWOFLD_API_H__
#ifdef BB_8852C_SUPPORT
#ifdef HALBB_CONFIG_RUN_IN_DRV
#include "../halbb_api.h"
#include "../halbb_fwofld_ex.h"
#endif
/*@--------------------------[Define] ---------------------------------------*/
/*@--------------------------[Enum]------------------------------------------*/
/*@--------------------------[Structure]-------------------------------------*/
struct bb_info;
/*@--------------------------[Prptotype]-------------------------------------*/
#ifdef HALBB_FW_OFLD_SUPPORT
bool halbb_fwcfg_bb_phy_8852c(struct bb_info *bb, u32 addr, u32 data,
enum phl_phy_idx phy_idx);
bool halbb_fwofld_ctrl_ch_8852c(struct bb_info *bb, u8 central_ch, enum band_type band,
enum phl_phy_idx phy_idx);
bool halbb_fwofld_ctrl_bw_ch_8852c(struct bb_info *bb, u8 pri_ch, u8 central_ch,
enum channel_width bw, enum band_type band,
enum phl_phy_idx phy_idx);
void halbb_fwofld_ctrl_cck_en_8852c(struct bb_info *bb, bool cck_en,
enum phl_phy_idx phy_idx);
void halbb_fwofld_set_hidden_efuse_8852c(struct bb_info *bb, u8 central_ch, enum band_type band_type, enum rf_path path);
void halbb_fwofld_set_normal_efuse_8852c(struct bb_info *bb, u8 central_ch, enum band_type band_type, enum rf_path path);
void halbb_fwofld_set_gain_error_8852c(struct bb_info *bb, u8 central_ch,
enum band_type band_type,
enum rf_path path);
void halbb_fwofld_set_gain_cr_init_8852c(struct bb_info *bb);
void halbb_fwofld_set_rxsc_rpl_comp_8852c(struct bb_info *bb, u8 central_ch, enum band_type band_type);
#endif
#endif
#endif
3rd/devourer/hal/halbb/g6/vendor/halbb_8852c/halbb_cr_info_8852c.h
Vendored
+18905
View File
File diff suppressed because it is too large Load Diff
3rd/devourer/hal/halbb/g6/vendor/halbb_8852c/halbb_hwimg_8852c.c
Vendored
+370
View File
@@ -0,0 +1,370 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "../halbb_precomp.h"
#include "halbb_hwimg_raw_data_8852c.h"
#include "halbb_hwimg_raw_data_8852d.h"
#include "halbb_hwimg_raw_data_8842a.h"
#ifdef BB_8852C_SUPPORT
#if 0
bool halbb_sel_headline_8852c(struct bb_info *bb, u32 *array, u32 array_len,
u8 *headline_size, u8 *headline_idx)
{
bool case_match = false;
u32 cut_drv = (u32)bb->hal_com->cv;
u32 rfe_drv = (u32)bb->phl_com->dev_cap.rfe_type;
u32 cut_para = 0, rfe_para = 0;
u32 compare_target = 0;
u32 cut_max = 0;
u32 i = 0;
*headline_idx = 0;
*headline_size = 0;
if (bb->bb_dbg_i.cr_dbg_mode_en) {
rfe_drv = bb->bb_dbg_i.rfe_type_curr_dbg;
cut_drv = bb->bb_dbg_i.cut_curr_dbg;
}
BB_DBG(bb, DBG_INIT, "{RFE, Cart}={%d, %d}, dbg_en=%d\n",
rfe_drv, cut_drv, bb->bb_dbg_i.cr_dbg_mode_en);
while ((i + 1) < array_len) {
if ((array[i] >> 28) != 0xf) {
*headline_size = (u8)i;
break;
}
BB_DBG(bb, DBG_INIT, "array[%02d]=0x%08x, array[%02d]=0x%08x\n",
i, array[i], i+1, array[i+1]);
i += 2;
}
BB_DBG(bb, DBG_INIT, "headline_size=%d\n", i);
if (i == 0)
return true;
/*case_idx:1 {RFE:Match, CUT:Match}*/
compare_target = ((rfe_drv & 0xff) << 16) | (cut_drv & 0xff);
BB_DBG(bb, DBG_INIT, "[1] CHK {RFE:Match, CUT:Match}\n");
for (i = 0; i < *headline_size; i += 2) {
if ((array[i] & 0x0fffffff) == compare_target) {
*headline_idx = (u8)(i >> 1);
return true;
}
}
BB_DBG(bb, DBG_INIT, "\t fail\n");
/*case_idx:2 {RFE:Match, CUT:Dont care}*/
compare_target = ((rfe_drv & 0xff) << 16) | (DONT_CARE_8852C & 0xff);
BB_DBG(bb, DBG_INIT, "[2] CHK {RFE:Match, CUT:Dont_Care}\n");
for (i = 0; i < *headline_size; i += 2) {
if ((array[i] & 0x0fffffff) == compare_target) {
*headline_idx = (u8)(i >> 1);
return true;
}
}
BB_DBG(bb, DBG_INIT, "\t fail\n");
/*case_idx:3 {RFE:Match, CUT:Max_in_table}*/
BB_DBG(bb, DBG_INIT, "[3] CHK {RFE:Match, CUT:Max_in_Table}\n");
for (i = 0; i < *headline_size; i += 2) {
rfe_para = (array[i] & 0x00ff0000) >> 16;
cut_para = array[i] & 0x0ff;
if (rfe_para == rfe_drv) {
if (cut_para >= cut_max) {
cut_max = cut_para;
*headline_idx = (u8)(i >> 1);
BB_DBG(bb, DBG_INIT, "cut_max:%d\n", cut_max);
case_match = true;
}
}
}
if (case_match) {
return true;
}
BB_DBG(bb, DBG_INIT, "\t fail\n");
/*case_idx:4 {RFE:Dont Care, CUT:Max_in_table}*/
BB_DBG(bb, DBG_INIT, "[4] CHK {RFE:Dont_Care, CUT:Max_in_Table}\n");
for (i = 0; i < *headline_size; i += 2) {
rfe_para = (array[i] & 0x00ff0000) >> 16;
cut_para = array[i] & 0x0ff;
if (rfe_para == DONT_CARE_8852C) {
if (cut_para >= cut_max) {
cut_max = cut_para;
*headline_idx = (u8)(i >> 1);
BB_DBG(bb, DBG_INIT, "cut_max:%d\n", cut_max);
case_match = true;
}
}
}
if (case_match) {
return true;
}
BB_DBG(bb, DBG_INIT, "\t fail\n");
/*case_idx:5 {RFE:Not_Match, CUT:Not_Match}*/
BB_DBG(bb, DBG_INIT, "[5] CHK {RFE:Not_Match, CUT:Not_Match}\n");
BB_DBG(bb, DBG_INIT, "\t all fail\n");
return false;
}
#endif
void halbb_flag_2_default_8852c(bool *is_matched, bool *find_target)
{
*is_matched = true;
*find_target = false;
}
bool halbb_cfg_bbcr_ax_8852c(struct bb_info *bb, bool is_form_folder,
u32 folder_len, u32 *folder_array,
enum phl_phy_idx phy_idx)
{
bool is_matched, find_target;
u32 cfg_target = 0, cfg_para = 0;
u32 i = 0;
u32 array_len = 0;
u32 *array = NULL;
u32 v1 = 0, v2 = 0;
u8 h_size = 0;
u8 h_idx = 0;
BB_DBG(bb, DBG_INIT, "===> %s\n", __func__);
if (is_form_folder) {
array_len = folder_len;
array = folder_array;
} else if (bb->ic_sub_type == BB_IC_SUB_TYPE_8852C_8852C) {
array_len = sizeof(array_mp_8852c_phy_reg) / sizeof(u32);
array = (u32 *)array_mp_8852c_phy_reg;
} else if (bb->ic_sub_type == BB_IC_SUB_TYPE_8852C_8852D) {
array_len = sizeof(array_mp_8852d_phy_reg) / sizeof(u32);
array = (u32 *)array_mp_8852d_phy_reg;
} else if ((bb->ic_sub_type == BB_IC_SUB_TYPE_8852C_8842A) ||
(bb->ic_sub_type == BB_IC_SUB_TYPE_8852C_8842A_6967A)) {
array_len = sizeof(array_mp_8842a_phy_reg) / sizeof(u32);
array = (u32 *)array_mp_8842a_phy_reg;
}
BB_DBG(bb, DBG_INIT, "form_folder=%d, len=%d, dbcc_en=%d, phy_idx=%d\n",
is_form_folder, array_len, bb->hal_com->dbcc_en, phy_idx);
if (!array) {
BB_WARNING("[%s]Invalid array\n", __func__);
return false;
}
if (!halbb_sel_headline(bb, array, array_len, &h_size, &h_idx)) {
BB_WARNING("[%s]Invalid BB CR Pkg\n", __func__);
return false;
}
BB_DBG(bb, DBG_INIT, "h_size = %d, h_idx = %d\n", h_size, h_idx);
if (h_size != 0) {
cfg_target = array[h_idx << 1] & 0x0fffffff;
}
i += h_size;
BB_DBG(bb, DBG_INIT, "cfg_target = 0x%x\n", cfg_target);
BB_DBG(bb, DBG_INIT, "array[i] = 0x%x, array[i+1] = 0x%x\n", array[i], array[i + 1]);
halbb_flag_2_default_8852c(&is_matched, &find_target);
#ifdef HALBB_FW_OFLD_SUPPORT
if (halbb_check_fw_ofld(bb))
BB_DBG(bb, DBG_FW_INFO, "Becareful it is fwofld mode in BB init !!\n");
#endif
while ((i + 1) < array_len) {
v1 = array[i];
v2 = array[i + 1];
i += 2;
switch (v1 >> 28) {
case IF_8852C:
case ELSE_IF_8852C:
cfg_para = v1 & 0x0fffffff;
BB_DBG(bb, DBG_INIT, "*if (rfe=%d, cart=%d)\n",
(cfg_para & 0xff0000) >> 16, cfg_para & 0xff);
break;
case ELSE_8852C:
BB_DBG(bb, DBG_INIT, "*else\n");
is_matched = false;
if (!find_target) {
BB_WARNING("Init BBCR Fail in Reg 0x%x\n", array[i]);
return false;
}
break;
case END_8852C:
BB_DBG(bb, DBG_INIT, "*endif\n");
halbb_flag_2_default_8852c(&is_matched, &find_target);
break;
case CHK_8852C:
/*Check this para meets driver's requirement or not*/
if (find_target) {
BB_DBG(bb, DBG_INIT, "\t skip\n");
is_matched = false;
break;
}
if (cfg_para == cfg_target) {
is_matched = true;
find_target = true;
} else {
is_matched = false;
find_target = false;
}
BB_DBG(bb, DBG_INIT, "\t match=%d\n", is_matched);
break;
default:
if (is_matched)
#if 0//def HALBB_FW_OFLD_SUPPORT
ret = halbb_fwcfg_bb_phy_8852c(bb, v1, v2, phy_idx);
#else
halbb_cfg_bb_phy_8852c(bb, v1, v2, phy_idx);
#endif
break;
}
}
BB_DBG(bb, DBG_INIT, "BBCR Init Success\n\n");
return true;
}
bool halbb_cfg_bb_gain_ax_8852c(struct bb_info *bb, bool is_form_folder,
u32 folder_len, u32 *folder_array)
{
bool is_matched, find_target;
u32 cfg_target = 0, cfg_para = 0;
u32 i = 0;
u32 array_len = 0;
u32 *array = NULL;
u32 v1 = 0, v2 = 0;
u8 h_size = 0;
u8 h_idx = 0;
BB_DBG(bb, DBG_INIT, "===> %s\n", __func__);
if (is_form_folder) {
array_len = folder_len;
array = folder_array;
} else {
array_len = sizeof(array_mp_8852c_phy_reg_gain) / sizeof(u32);
array = (u32 *)array_mp_8852c_phy_reg_gain;
}
if (is_form_folder) {
array_len = folder_len;
array = folder_array;
} else if (bb->ic_sub_type == BB_IC_SUB_TYPE_8852C_8852C) {
array_len = sizeof(array_mp_8852c_phy_reg_gain) / sizeof(u32);
array = (u32 *)array_mp_8852c_phy_reg_gain;
} else if (bb->ic_sub_type == BB_IC_SUB_TYPE_8852C_8852D) {
array_len = sizeof(array_mp_8852d_phy_reg_gain) / sizeof(u32);
array = (u32 *)array_mp_8852d_phy_reg_gain;
} else if ((bb->ic_sub_type == BB_IC_SUB_TYPE_8852C_8842A) ||
(bb->ic_sub_type == BB_IC_SUB_TYPE_8852C_8842A_6967A)) {
array_len = sizeof(array_mp_8842a_phy_reg_gain) / sizeof(u32);
array = (u32 *)array_mp_8842a_phy_reg_gain;
}
BB_DBG(bb, DBG_INIT, "GAIN_TABLE_form_folder=%d, len=%d\n",
is_form_folder, array_len);
if (!halbb_sel_headline(bb, array, array_len, &h_size, &h_idx)) {
BB_WARNING("[%s]Invalid BB CR Pkg\n", __func__);
return false;
}
BB_DBG(bb, DBG_INIT, "h_size = %d, h_idx = %d\n", h_size, h_idx);
if (h_size != 0) {
cfg_target = array[h_idx << 1] & 0x0fffffff;
}
i += h_size;
BB_DBG(bb, DBG_INIT, "cfg_target = 0x%x\n", cfg_target);
BB_DBG(bb, DBG_INIT, "array[i] = 0x%x, array[i+1] = 0x%x\n", array[i], array[i + 1]);
halbb_flag_2_default_8852c(&is_matched, &find_target);
while ((i + 1) < array_len) {
v1 = array[i];
v2 = array[i + 1];
i += 2;
switch (v1 >> 28) {
case IF_8852C:
case ELSE_IF_8852C:
cfg_para = v1 & 0x0fffffff;
BB_DBG(bb, DBG_INIT, "*if (rfe=%d, cart=%d)\n",
(cfg_para & 0xff0000) >> 16, cfg_para & 0xff);
break;
case ELSE_8852C:
BB_DBG(bb, DBG_INIT, "*else\n");
is_matched = false;
if (!find_target) {
BB_WARNING("Init BBCR Fail in Reg 0x%x\n", array[i]);
return false;
}
break;
case END_8852C:
BB_DBG(bb, DBG_INIT, "*endif\n");
halbb_flag_2_default_8852c(&is_matched, &find_target);
break;
case CHK_8852C:
/*Check this para meets driver's requirement or not*/
if (find_target) {
BB_DBG(bb, DBG_INIT, "\t skip\n");
is_matched = false;
break;
}
if (cfg_para == cfg_target) {
is_matched = true;
find_target = true;
} else {
is_matched = false;
find_target = false;
}
BB_DBG(bb, DBG_INIT, "\t match=%d\n", is_matched);
break;
default:
if (is_matched)
halbb_cfg_bb_gain_8852c(bb, v1, v2);
break;
}
}
BB_DBG(bb, DBG_INIT, "BBCR gain Init Success\n\n");
return true;
}
u32
halbb_get_8852c_phy_reg_ver(void)
{
return (u32)BB_REG_RELEASE_VERSION_8852C;
}
#endif /* end of HWIMG_SUPPORT*/
3rd/devourer/hal/halbb/g6/vendor/halbb_8852c/halbb_hwimg_8852c.h
Vendored
+50
View File
@@ -0,0 +1,50 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef _HALBB_HW_IMG_8852C_H_
#define _HALBB_HW_IMG_8852C_H_
/******************************************************************************
* phy_reg.TXT
******************************************************************************/
#define DONT_CARE_8852C 0xff
#define IF_8852C 0x8
#define ELSE_IF_8852C 0x9
#define ELSE_8852C 0xa
#define END_8852C 0xb
#define CHK_8852C 0x4
bool halbb_cfg_bbcr_ax_8852c(struct bb_info *bb, bool is_form_folder,
u32 folder_len, u32 *folder_array,
enum phl_phy_idx phy_idx);
bool halbb_cfg_bb_gain_ax_8852c(struct bb_info *bb, bool is_form_folder,
u32 folder_len, u32 *folder_array);
u32 halbb_get_8852c_phy_reg_ver(void);
#endif /* end of HWIMG_SUPPORT*/
3rd/devourer/hal/halbb/g6/vendor/halbb_8852c/halbb_hwimg_band_swh_8852d.h
Vendored
+116
View File
@@ -0,0 +1,116 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
/*Image2HeaderVersion: R3 2.0.2.0*/
#ifndef _HALBB_HWIMG_BAND_SWH_8852d_H
#define _HALBB_HWIMG_BAND_SWH_8852d_H
#ifdef HALBB_BAND_SWH_CR_SEQ_SUPPORT
const u32 array_mp_8852d_band_swh[] = {
0x8100724, 0x00111200,
0x81046AC, 0x60423537,
0x81046BC, 0x5107C252,
0x8104720, 0x3FFFFD63,
0x8104724, 0xB58D11FF,
0x8104730, 0xE0399201,
0x8104738, 0x8325C500,
0x8104798, 0x000001D3,
0x81047C8, 0x56767578,
0x810481C, 0x576DF814,
0x810484C, 0x0000CA62,
0x81048D4, 0x576DF814,
0x8104A60, 0x60423537,
0x8104A70, 0x5107C252,
0x8104A74, 0x3FFFFD63,
0x8104A78, 0xB58D11FF,
0x8104A9C, 0xE0399201,
0x8104AA4, 0x8325C500,
0x8104BE4, 0xBAAC8000,
0x8104CA8, 0xBAAC8000,
0x8104D2C, 0x0008C0C1,
0x8104D34, 0x7BB167AB,
0x81058B0, 0x00000800,
0x8105A24, 0x00050000,
0x8105A44, 0x00000005,
0x8105A60, 0x00050000,
0x8105AB0, 0x00050005,
0x8105AB4, 0x00050005,
0x8105AB8, 0x00050005,
0x8105ABC, 0x00050005,
0x8105AC0, 0x00000005,
0x81078B0, 0x00000800,
0x8107A24, 0x00050000,
0x8107A44, 0x00000005,
0x8107A60, 0x00050000,
0x8107AB0, 0x00050005,
0x8107AB4, 0x00050005,
0x8107AB8, 0x00050005,
0x8107ABC, 0x00050005,
0x8107AC0, 0x00000005,
0x8600724, 0x01100100,
0x86046AC, 0xA0423537,
0x86046BC, 0x510FC252,
0x8604720, 0x7FFFFD63,
0x8604724, 0x758D11FF,
0x8604730, 0xE0389201,
0x8604738, 0x8F25C500,
0x8604798, 0x000000D3,
0x86047C8, 0x55757478,
0x860481C, 0x5765F814,
0x860484C, 0x00008A62,
0x86048D4, 0x576BF814,
0x8604A60, 0xA0423537,
0x8604A70, 0x510FC252,
0x8604A74, 0x7FFFFD63,
0x8604A78, 0x758D11FF,
0x8604A9C, 0xE0389201,
0x8604AA4, 0x8F25C500,
0x8604BE4, 0xD5640000,
0x8604CA8, 0xD5640000,
0x8604D2C, 0x0008C8C1,
0x8604D34, 0x7BB1579A,
0x86058B0, 0x00000000,
0x8605A24, 0x00000000,
0x8605A44, 0x00000000,
0x8605A60, 0x00000000,
0x8605AB0, 0x00000000,
0x8605AB4, 0x00000000,
0x8605AB8, 0x00000000,
0x8605ABC, 0x00000000,
0x8605AC0, 0x00000000,
0x86078B0, 0x00000000,
0x8607A24, 0x00000000,
0x8607A44, 0x00000000,
0x8607A60, 0x00000000,
0x8607AB0, 0x00000000,
0x8607AB4, 0x00000000,
0x8607AB8, 0x00000000,
0x8607ABC, 0x00000000,
0x8607AC0, 0x00000000
};
#endif
#endif /* _HALBB_HWIMG_BAND_SWH_8852d_H */
3rd/devourer/hal/halbb/g6/vendor/halbb_8852c/halbb_hwimg_raw_data_8842a.h
Vendored
+1896
View File
File diff suppressed because it is too large Load Diff
3rd/devourer/hal/halbb/g6/vendor/halbb_8852c/halbb_hwimg_raw_data_8852c.h
Vendored
+6547
View File
File diff suppressed because it is too large Load Diff
3rd/devourer/hal/halbb/g6/vendor/halbb_8852c/halbb_hwimg_raw_data_8852d.h
Vendored
+9524
View File
File diff suppressed because it is too large Load Diff
3rd/devourer/hal/halbb/g6/vendor/halbb_8852c/halbb_reg_cfg_8852c.c
Vendored
+240
View File
@@ -0,0 +1,240 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "../halbb_precomp.h"
#ifdef BB_8852C_SUPPORT
void halbb_cfg_rf_reg_8852c(struct bb_info *bb, u32 addr, u32 data,
enum rf_path rf_path, u32 reg_addr)
{
}
void halbb_cfg_rf_radio_a_8852c(struct bb_info *bb, u32 addr, u32 data)
{
}
void halbb_cfg_rf_radio_b_8852c(struct bb_info *bb, u32 addr, u32 data)
{
}
void halbb_cfg_bb_phy_8852c(struct bb_info *bb, u32 addr, u32 data,
enum phl_phy_idx phy_idx)
{
#ifdef HALBB_DBCC_SUPPORT
u32 ofst = 0;
#endif
if (addr == 0xfe) {
halbb_delay_ms(bb, 50);
BB_DBG(bb, DBG_INIT, "Delay 50 ms\n");
} else if (addr == 0xfd) {
halbb_delay_ms(bb, 5);
BB_DBG(bb, DBG_INIT, "Delay 5 ms\n");
} else if (addr == 0xfc) {
halbb_delay_ms(bb, 1);
BB_DBG(bb, DBG_INIT, "Delay 1 ms\n");
} else if (addr == 0xfb) {
halbb_delay_us(bb, 50);
BB_DBG(bb, DBG_INIT, "Delay 50 us\n");
} else if (addr == 0xfa) {
halbb_delay_us(bb, 5);
BB_DBG(bb, DBG_INIT, "Delay 5 us\n");
} else if (addr == 0xf9) {
halbb_delay_us(bb, 1);
BB_DBG(bb, DBG_INIT, "Delay 1 us\n");
} else {
#ifdef HALBB_DBCC_SUPPORT
if ((bb->hal_com->dbcc_en || bb->bb_dbg_i.cr_dbg_mode_en) &&
phy_idx == HW_PHY_1) {
ofst = halbb_phy0_to_phy1_ofst(bb, addr, phy_idx);
if (ofst == 0)
return;
addr += ofst;
} else {
phy_idx = HW_PHY_0;
}
//if (phy_idx == HW_PHY_1)
// BB_DBG(bb, DBG_DBCC, "[REG][%d]0x%04X = 0x%08X\n", phy_idx, addr, data);
#else
BB_DBG(bb, DBG_INIT, "[REG]0x%04X = 0x%08X\n", addr, data);
#endif
halbb_set_reg(bb, addr, MASKDWORD, data);
}
}
void halbb_cfg_bb_gain_8852c(struct bb_info *bb, u32 addr, u32 data)
{
struct bb_gain_info *gain = &bb->bb_gain_i;
u8 cfg_type = (u8)((addr & 0xff000000) >> 24);
enum bb_band_t band_idx = (enum bb_band_t)((addr & 0xff0000) >> 16);
u8 path = (u8)((addr & 0xff00) >> 8);
u8 type;
u8 i = 0;
if (band_idx >= BB_GAIN_BAND_NUM)
return;
if (path >= HALBB_MAX_PATH)
return;
if (addr == 0xfe) {
halbb_delay_ms(bb, 50);
BB_DBG(bb, DBG_INIT, "Delay 50 ms\n");
} else if (addr == 0xfd) {
halbb_delay_ms(bb, 5);
BB_DBG(bb, DBG_INIT, "Delay 5 ms\n");
} else if (addr == 0xfc) {
halbb_delay_ms(bb, 1);
BB_DBG(bb, DBG_INIT, "Delay 1 ms\n");
} else if (addr == 0xfb) {
halbb_delay_us(bb, 50);
BB_DBG(bb, DBG_INIT, "Delay 50 us\n");
} else if (addr == 0xfa) {
halbb_delay_us(bb, 5);
BB_DBG(bb, DBG_INIT, "Delay 5 us\n");
} else if (addr == 0xf9) {
halbb_delay_us(bb, 1);
BB_DBG(bb, DBG_INIT, "Delay 1 us\n");
} else if (cfg_type == 0) { /*GAIN ERROR*/
type = (u8)(addr & 0xff);
if (type == 0) {
for (i = 0; i < 4; i++)
gain->lna_gain[band_idx][path][i] = (data >> (8 * i)) & 0xff;
} else if (type == 1) {
for (i = 0; i < 3; i++)
gain->lna_gain[band_idx][path][4 + i] = (data >> (8 * i)) & 0xff;
} else if (type == 2) {
for (i = 0; i < 2; i++)
gain->tia_gain[band_idx][path][i] = (data >> (8 * i)) & 0xff;
}
if ((band_idx >= 4) && (band_idx <= 7)) { /*Avoid phy_reg_gain does not support band_idx 8~11*/
if (type == 0) {
for (i = 0; i < 4; i++)
gain->lna_gain[band_idx + 4][path][i] = (data >> (8 * i)) & 0xff;
} else if (type == 1) {
for (i = 0; i < 3; i++)
gain->lna_gain[band_idx + 4][path][4 + i] = (data >> (8 * i)) & 0xff;
} else if (type == 2) {
for (i = 0; i < 2; i++)
gain->tia_gain[band_idx + 4][path][i] = (data >> (8 * i)) & 0xff;
}
}
} else if (cfg_type == 1) { /*RPL Offset*/
halbb_cfg_bb_rpl_ofst(bb, band_idx, path, addr, data);
if ((band_idx >= 4) && (band_idx <= 7)) /*Avoid phy_reg_gain does not support band_idx 8~11*/
halbb_cfg_bb_rpl_ofst(bb, band_idx + 4, path, addr, data);
} else if (cfg_type == 2) { /*Bypass Mode GAIN ERROR*/
type = (u8)(addr & 0xff);
if (type == 0) {
for (i = 0; i < 4; i++)
gain->lna_gain_bypass[band_idx][path][i] = (data >> (8 * i)) & 0xff;
} else if (type == 1) {
for (i = 0; i < 3; i++)
gain->lna_gain_bypass[band_idx][path][4 + i] = (data >> (8 * i)) & 0xff;
}
if ((band_idx >= 4) && (band_idx <= 7)) { /*Avoid phy_reg_gain does not support band_idx 8~11*/
if (type == 0) {
for (i = 0; i < 4; i++)
gain->lna_gain_bypass[band_idx + 4][path][i] = (data >> (8 * i)) & 0xff;
} else if (type == 1) {
for (i = 0; i < 3; i++)
gain->lna_gain_bypass[band_idx + 4][path][4 + i] = (data >> (8 * i)) & 0xff;
}
}
} else if (cfg_type == 3) { /*op1dB values*/
type = (u8)(addr & 0xff);
if (type == 0) {
for (i = 0; i < 4; i++)
gain->lna_op1db[band_idx][path][i] = (data >> (8 * i)) & 0xff;
} else if (type == 1) {
for (i = 0; i < 3; i++)
gain->lna_op1db[band_idx][path][4 + i] = (data >> (8 * i)) & 0xff;
} else if (type == 2) {
for (i = 0; i < 4; i++)
gain->tia_lna_op1db[band_idx][path][i] = (data >> (8 * i)) & 0xff;
} else if (type == 3) {
for (i = 0; i < 4; i++)
gain->tia_lna_op1db[band_idx][path][4 + i] = (data >> (8 * i)) & 0xff;
}
if ((band_idx >= 4) && (band_idx <= 7)) { /*Avoid phy_reg_gain does not support band_idx 8~11*/
if (type == 0) {
for (i = 0; i < 4; i++)
gain->lna_op1db[band_idx + 4][path][i] = (data >> (8 * i)) & 0xff;
} else if (type == 1) {
for (i = 0; i < 3; i++)
gain->lna_op1db[band_idx + 4][path][4 + i] = (data >> (8 * i)) & 0xff;
} else if (type == 2) {
for (i = 0; i < 4; i++)
gain->tia_lna_op1db[band_idx + 4][path][i] = (data >> (8 * i)) & 0xff;
} else if (type == 3) {
for (i = 0; i < 4; i++)
gain->tia_lna_op1db[band_idx + 4][path][4 + i] = (data >> (8 * i)) & 0xff;
}
}
} else if (cfg_type == 4) { /*WB_GIDX & GS IDX*/
type = (u8)(addr & 0xff);
if (type == 0)
gain->wb_gidx_elna[band_idx][path] = data;
else if (type == 1)
for (i = 0; i < 8; i++)
gain->wb_gidx_lna_tia[band_idx][path][i] = (data >> (4 * i)) & 0x7;
else if (type == 2)
for (i = 0; i < 8; i++)
gain->wb_gidx_lna_tia[band_idx][path][i + 8] = (data >> (4 * i)) & 0x7;
else if (type == 3)
gain->gs_idx[band_idx][path][0] = data;
else if (type == 4)
gain->gs_idx[band_idx][path][1] = data;
else if (type == 5)
for (i = 0; i < 2; i++)
gain->g_elna[band_idx][path][i] = (data >> (8 * i)) & 0xff;
if ((band_idx >= 4) && (band_idx <= 7)) { /*Avoid phy_reg_gain does not support band_idx 8~11*/
if (type == 0)
gain->wb_gidx_elna[band_idx + 4][path] = data;
else if (type == 1)
for (i = 0; i < 8; i++)
gain->wb_gidx_lna_tia[band_idx + 4][path][i] = (data >> (4 * i)) & 0x7;
else if (type == 2)
for (i = 0; i < 8; i++)
gain->wb_gidx_lna_tia[band_idx + 4][path][i + 8] = (data >> (4 * i)) & 0x7;
else if (type == 3)
gain->gs_idx[band_idx + 4][path][0] = data;
else if (type == 4)
gain->gs_idx[band_idx + 4][path][1] = data;
else if (type == 5)
for (i = 0; i < 2; i++)
gain->g_elna[band_idx + 4][path][i] = (data >> (8 * i)) & 0xff;
}
} else {
BB_WARNING("cfg_type=%d\n", cfg_type);
}
}
#endif
3rd/devourer/hal/halbb/g6/vendor/halbb_8852c/halbb_reg_cfg_8852c.h
Vendored
+36
View File
@@ -0,0 +1,36 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef _HALBB_REG_CFG_8852C_H_
#define _HALBB_REG_CFG_8852C_H_
#ifdef BB_8852C_SUPPORT
void halbb_cfg_bb_phy_8852c(struct bb_info *bb, u32 addr, u32 data,
enum phl_phy_idx phy_idx);
void halbb_cfg_bb_gain_8852c(struct bb_info *bb, u32 addr, u32 data);
#endif
#endif /* RTL8822C_SUPPORT*/
3rd/devourer/hal/halbb/g6/vendor/halbb_8852c/halbb_version_rtl8842a.h
Vendored
+30
View File
@@ -0,0 +1,30 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
/*RTL8842A BB Parameters*/
#ifndef _HALBB_VERSION_8842A_H_
#define _HALBB_VERSION_8842A_H_
#define BB_REG_RELEASE_DATE_8842A 20240201
#define BB_REG_RELEASE_VERSION_8842A 01
#endif
3rd/devourer/hal/halbb/g6/vendor/halbb_8852c/halbb_version_rtl8852c.h
Vendored
+30
View File
@@ -0,0 +1,30 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
/*RTL8852C BB Parameters*/
#ifndef _HALBB_VERSION_8852C_H_
#define _HALBB_VERSION_8852C_H_
#define BB_REG_RELEASE_DATE_8852C 20241113
#define BB_REG_RELEASE_VERSION_8852C 62
#endif
3rd/devourer/hal/halbb/g6/vendor/halbb_8852c/halbb_version_rtl8852d.h
Vendored
+30
View File
@@ -0,0 +1,30 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
/*RTL8852D BB Parameters*/
#ifndef _HALBB_VERSION_8852D_H_
#define _HALBB_VERSION_8852D_H_
#define BB_REG_RELEASE_DATE_8852D 20250424
#define BB_REG_RELEASE_VERSION_8852D 28
#endif
3rd/devourer/hal/halbb/g6/vendor/halbb_ant_div.h
Vendored
+402
View File
@@ -0,0 +1,402 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_ANT_DIV_H__
#define __HALBB_ANT_DIV_H__
/*@--------------------------[Define] ---------------------------------------*/
#define EVM_BASED_ANTDIV 0
#define CN_BASED_ANTDIV 1
#define TP_MAX_DOMINATION 0
#define TP_HIGHEST_DOMINATION 1
#define TP_AVG_DOMINATION 2
#define ANTDIV_INIT 0xff
#define MAIN_ANT 1 /*@ant A or ant Main or S1*/
#define AUX_ANT 2 /*@AntB or ant Aux or S0*/
#define MAX_ANT 3 /* @3 for AP using*/
#define ANT1_2G 0
/* @= ANT2_5G for 8723D BTG S1 RX S0S1 diversity for 8723D, TX fixed at S1 */
#define ANT2_2G 1
/* @= ANT1_5G for 8723D BTG S0 RX S0S1 diversity for 8723D, TX fixed at S1 */
#define ANTDIV_MAX_STA_NUM PHL_MAX_STA_NUM
#define ANTDIV_RSSI_TH_HIGH 30
#define ANTDIV_RSSI_TH_LOW 20
#define ANTDIV_PERIOD 1
#define ANTDIV_TRAINING_NUM 2
#define ANTDIV_NOTRAINING_NUM 3
#define FORCE_RSSI_DIFF 10
#define ANTDIV_DELAY 110
#define ANTDIV_INTVL 30
#define ANTDIV_DEC_TP_HIGH 100
#define ANTDIV_DEC_TP_LOW 5
#define ANTDIV_DEC_EVM 8
#define ANTDIV_DEC_EVM_1SS 8
#define TP_LOWER_BOUND 1
/*parameter for 1ss rssi-based antdiv*/
#define ANTDIV_PERIOD_1SS 1
#define ANTDIV_TRAINING_NUM_1SS 2
#define ANTDIV_DELAY_1SS 1
#define ANTDIV_INTVL_1SS 10
#define ANTDIV_DEC_RSSI 3
#define ANTDIV_FIXANT_RSSI 2
/* @Antenna Diversty Control type */
#define ODM_AUTO_ANT 0
#define ODM_FIX_MAIN_ANT 1
#define ODM_FIX_AUX_ANT 2
#define ANTDIV_ON 1
#define ANTDIV_OFF 0
#define ANT_PATH_A 0
#define ANT_PATH_B 1
#define ANT_PATH_AB 2
/*@--------------------------[Enum]------------------------------------------*/
enum bb_antdiv_mode_t {
AUTO_ANT = 0,
FIX_MAIN_ANT = 1,
FIX_AUX_ANT = 2,
};
enum bb_tp_method_t {
TP_MAX = 0,
TP_HIGHEST = 1,
TP_AVG = 2,
};
enum bb_evm_method_t {
EVM_LINEAR_AVG = 0,
EVM_DB_AVG = 1,
};
enum bb_antdiv_method_t {
EVM_BASED = 0,
CN_BASED = 1,
};
/*@--------------------------[Structure]-------------------------------------*/
struct bb_antdiv_rssi_info { /*all in U(8,1)*/
/*acc value*/
u32 rssi_cck_avg_acc;
u32 rssi_ofdm_avg_acc;
u32 rssi_t_avg_acc;
u8 rssi_cck_avg;
u8 rssi_ofdm_avg;
u8 rssi_t_avg;
u8 rssi_final;
u16 pkt_cnt_t;
u16 pkt_cnt_cck;
u16 pkt_cnt_ofdm;
u32 main_rssi_cck_avg_acc;
u32 main_rssi_ofdm_avg_acc;
u32 main_rssi_t_avg_acc;
u8 main_rssi_cck_avg;
u8 main_rssi_ofdm_avg;
u8 main_rssi_t_avg;
u8 main_rssi_final;
u16 main_pkt_cnt_t;
u16 main_pkt_cnt_cck;
u16 main_pkt_cnt_ofdm;
u32 aux_rssi_cck_avg_acc;
u32 aux_rssi_ofdm_avg_acc;
u32 aux_rssi_t_avg_acc;
u8 aux_rssi_cck_avg;
u8 aux_rssi_ofdm_avg;
u8 aux_rssi_t_avg;
u8 aux_rssi_final;
u16 aux_pkt_cnt_t;
u16 aux_pkt_cnt_cck;
u16 aux_pkt_cnt_ofdm;
u8 rssi_diff;
bool no_change_flag;
};
struct bb_antdiv_cn_info {
u32 main_cn_avg_acc; /*U(7,1)*/
u32 aux_cn_avg_acc; /*U(7,1)*/
};
struct bb_antdiv_evm_info {
u32 main_evm_1ss;/*U(8,2)*/ /*only for 1SS & L-OFDM*/
u32 main_evm_min_acc; /*U(8,2)*/ /*only for >= 2SS*/
u32 main_evm_max_acc; /*U(8,2)*/ /*only for >= 2SS*/
u32 aux_evm_1ss;/*U(8,2)*/ /*only for 1SS & L-OFDM*/
u32 aux_evm_min_acc; /*U(8,2)*/ /*only for >= 2SS*/
u32 aux_evm_max_acc; /*U(8,2)*/ /*only for >= 2SS*/
u8 evm_diff;
bool no_change_flag;
};
struct bb_antdiv_rate_info {
/*====[Phy rate counter main ant]=============================================*/
u16 main_pkt_cnt_cck;
u16 main_pkt_cnt_ofdm; /*L-OFDM*/
u16 main_pkt_cnt_t; /*HT, VHT, HE = pkt_cnt_1ss + pkt_cnt_2ss*/
u16 main_pkt_cnt_1ss; /*HT, VHT, HE*/
u16 main_pkt_cnt_2ss; /*HT, VHT, HE*/
/*Legacy*/
u16 main_pkt_cnt_legacy[LEGACY_RATE_NUM];
/*HT*/
u16 main_pkt_cnt_ht[HT_RATE_NUM];
/*VHT*/
u16 main_pkt_cnt_vht[VHT_RATE_NUM];
/*HE*/
u16 main_pkt_cnt_he[HE_RATE_NUM];
/*Rxsc case*/
u16 main_pkt_cnt_ht_sc20[HT_RATE_NUM];
u16 main_pkt_cnt_vht_sc20[VHT_RATE_NUM];
u16 main_pkt_cnt_vht_sc40[VHT_RATE_NUM];
u16 main_pkt_cnt_vht_sc80[VHT_RATE_NUM];
u16 main_pkt_cnt_he_sc20[HE_RATE_NUM];
u16 main_pkt_cnt_he_sc40[HE_RATE_NUM];
u16 main_pkt_cnt_he_sc80[HE_RATE_NUM];
u16 main_max_cnt;
u16 main_max_idx;
/*====[Phy rate counter] aux ant=============================================*/
u16 aux_pkt_cnt_cck;
u16 aux_pkt_cnt_ofdm; /*L-OFDM*/
u16 aux_pkt_cnt_t; /*HT, VHT, HE = pkt_cnt_1ss + pkt_cnt_2ss*/
u16 aux_pkt_cnt_1ss; /*HT, VHT, HE*/
u16 aux_pkt_cnt_2ss; /*HT, VHT, HE*/
/*Legacy*/
u16 aux_pkt_cnt_legacy[LEGACY_RATE_NUM];
/*HT*/
u16 aux_pkt_cnt_ht[HT_RATE_NUM];
/*VHT*/
u16 aux_pkt_cnt_vht[VHT_RATE_NUM];
/*HE*/
u16 aux_pkt_cnt_he[HE_RATE_NUM];
/*Rxsc case*/
u16 aux_pkt_cnt_ht_sc20[HT_RATE_NUM];
u16 aux_pkt_cnt_vht_sc20[VHT_RATE_NUM];
u16 aux_pkt_cnt_vht_sc40[VHT_RATE_NUM];
u16 aux_pkt_cnt_vht_sc80[VHT_RATE_NUM];
u16 aux_pkt_cnt_he_sc20[HE_RATE_NUM];
u16 aux_pkt_cnt_he_sc40[HE_RATE_NUM];
u16 aux_pkt_cnt_he_sc80[HE_RATE_NUM];
u16 aux_max_cnt;
u16 aux_max_idx;
u16 main_cnt_all;
u16 aux_cnt_all;
u32 main_tp;
u32 aux_tp;
u32 tp_diff;
bool no_change_flag;
bool main_ht_pkt_not_zero;
bool main_vht_pkt_not_zero;
bool main_he_pkt_not_zero;
bool aux_ht_pkt_not_zero;
bool aux_vht_pkt_not_zero;
bool aux_he_pkt_not_zero;
bool main_sc20_occur;
bool main_sc40_occur;
bool main_sc80_occur;
bool aux_sc20_occur;
bool aux_sc40_occur;
bool aux_sc80_occur;
};
struct bb_antdiv_cr_info {
u32 path0_r_ant_train_en;
u32 path0_r_ant_train_en_m;
u32 path0_r_tx_ant_sel;
u32 path0_r_tx_ant_sel_m;
u32 path0_r_rfe_buf_en;
u32 path0_r_rfe_buf_en_m;
u32 path0_r_lnaon_agc;
u32 path0_r_lnaon_agc_m;
u32 path0_r_trsw_bit_bt;
u32 path0_r_trsw_bit_bt_m;
u32 path0_r_trsw_s;
u32 path0_r_trsw_s_m;
u32 path0_r_trsw_o;
u32 path0_r_trsw_o_m;
u32 path0_r_trswb_o;
u32 path0_r_trswb_o_m;
u32 path0_r_bt_force_antidx;
u32 path0_r_bt_force_antidx_m;
u32 path0_r_bt_force_antidx_en;
u32 path0_r_bt_force_antidx_en_m;
u32 path0_r_ant_module_rfe_opt;
u32 path0_r_ant_module_rfe_opt_m;
u32 path0_r_rfsw_tr;
u32 path0_r_rfsw_tr_m;
u32 path0_r_antsel;
u32 path0_r_antsel_m;
u32 path0_r_rfsw_ant_31_0;
u32 path0_r_rfsw_ant_31_0_m;
u32 path0_r_rfsw_ant_63_32;
u32 path0_r_rfsw_ant_63_32_m;
u32 path0_r_rfsw_ant_95_64;
u32 path0_r_rfsw_ant_95_64_m;
u32 path0_r_rfsw_ant_127_96;
u32 path0_r_rfsw_ant_127_96_m;
};
struct bb_sub_bw_tp_info {
u32 main_max_tp_160;
u32 main_max_tp_80;
u32 main_max_tp_40;
u32 main_max_tp_20;
u32 aux_max_tp_160;
u32 aux_max_tp_80;
u32 aux_max_tp_40;
u32 aux_max_tp_20;
u16 main_max_cnt_160;
u16 main_max_cnt_80;
u16 main_max_cnt_40;
u16 main_max_cnt_20;
u16 aux_max_cnt_160;
u16 aux_max_cnt_80;
u16 aux_max_cnt_40;
u16 aux_max_cnt_20;
u16 main_max_idx_160;
u16 main_max_idx_80;
u16 main_max_idx_40;
u16 main_max_idx_20;
u16 aux_max_idx_160;
u16 aux_max_idx_80;
u16 aux_max_idx_40;
u16 aux_max_idx_20;
u16 COUNT_MAIN_HE[4][HE_RATE_NUM];
u16 COUNT_AUX_HE[4][HE_RATE_NUM];
u16 COUNT_MAIN_VHT[4][VHT_RATE_NUM];
u16 COUNT_AUX_VHT[4][VHT_RATE_NUM];
u16 COUNT_MAIN_HT[2][HT_RATE_NUM];
u16 COUNT_AUX_HT[2][HT_RATE_NUM];
};
struct bb_antdiv_info {
/* For CN cacluation */
struct bb_antdiv_cn_info bb_cn_i;
/* For EVM cacluation */
struct bb_antdiv_evm_info bb_evm_i;
/* For MCS cacluation */
struct bb_antdiv_rate_info bb_rate_i;
/* For RSSI */
struct bb_antdiv_rssi_info bb_rssi_i;
/* For sub BW TP */
struct bb_sub_bw_tp_info bb_sub_bw_tp_i;
enum bb_antdiv_mode_t antdiv_mode;
enum bb_antdiv_method_t antdiv_method;
enum bb_antdiv_mode_t pre_antdiv_mode;
enum bb_tp_method_t tp_decision_method;
enum bb_evm_method_t evm_decision_method;
bool tx_by_ext_pwr_lmt;
/* Training state & period related*/
u8 antdiv_wd_cnt;
u8 antdiv_training_state_cnt;
u32 antdiv_intvl;
u32 antdiv_delay;
u32 antdiv_train_num;
u8 antdiv_period;
u8 tp_lb;
u8 rssi_pre;
u8 antdiv_notrain_cnt;
u8 antdiv_notrain_num;
u8 fixant_rssi_diff;
/* antenna setting */
u8 pre_target_ant;
u8 training_ant;
u8 target_ant;
u8 target_ant_cn;
u8 target_ant_evm;
u8 target_ant_tp;
u8 target_ant_rssi;
/* Decision*/
u16 tp_diff_th_high;
u16 tp_diff_th_low;
u8 evm_diff_th;
u8 rssi_diff_th;
/*Phy-sts related */
bool get_stats;
bool antdiv_use_ctrl_frame;
struct halbb_timer_info antdiv_timer_i;
u32 rvrt_val; /*all rvrt_val for pause API must set to u32*/
/* ant_div new code : extend to sub BW */
bool ant_div_new;
};
typedef struct {
u32* sub_main_max_tp;
u32* sub_aux_max_tp;
u16* sub_main_max_cnt;
u16* sub_aux_max_cnt;
u16* sub_main_max_idx;
u16* sub_aux_max_idx;
} Cnt_info;
struct bb_info;
/*@--------------------------[Prptotype]-------------------------------------*/
void halbb_antdiv_io_en(struct bb_info *bb);
void halbb_antdiv_timer_init(struct bb_info *bb);
void halbb_cr_cfg_antdiv_init(struct bb_info *bb);
void halbb_antdiv_reg_init(struct bb_info *bb);
void halbb_antdiv_init(struct bb_info *bb);
void halbb_antdiv_reset(struct bb_info *bb);
void halbb_antdiv_reset_training_stat(struct bb_info *bb);
void halbb_antdiv_set_ant(struct bb_info *bb, u8 ant);
void halbb_antdiv_get_highest_mcs(struct bb_info *bb);
void halbb_antdiv_get_evm_target_ant(struct bb_info *bb);
void halbb_antdiv_training_state(struct bb_info *bb);
void halbb_antdiv_decision_state(struct bb_info *bb);
void halbb_antdiv_1ss_decision_state(struct bb_info *bb);
void halbb_evm_based_antdiv(struct bb_info *bb);
void halbb_antenna_diversity(struct bb_info *bb);
void halbb_antdiv_phy_sts(struct bb_info *bb, u32 physts_bitmap,
struct physts_rxd *desc);
void halbb_antdiv_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len);
void halbb_set_antdiv_pause_val(struct bb_info *bb, u32 *val_buf, u8 val_len);
#endif
3rd/devourer/hal/halbb/g6/vendor/halbb_ant_div_ex.h
Vendored
+34
View File
@@ -0,0 +1,34 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_ANT_DIV_EX_H__
#define __HALBB_ANT_DIV_EX_H__
/*@--------------------------[Define] ---------------------------------------*/
/*@--------------------------[Enum]------------------------------------------*/
/*@--------------------------[Structure]-------------------------------------*/
struct bb_info;
/*@--------------------------[Prptotype]-------------------------------------*/
u8 halbb_antdiv_get_targetant(struct bb_info *bb);
void halbb_antdiv_fix_ant(struct bb_info *bb, u8 ant);
#endif
3rd/devourer/hal/halbb/g6/vendor/halbb_api.c
Vendored
+5323
View File
File diff suppressed because it is too large Load Diff
3rd/devourer/hal/halbb/g6/vendor/halbb_api.h
Vendored
+111
View File
@@ -0,0 +1,111 @@
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HALBB_API_H_
#define _HALBB_API_H_
#include "halbb_ic_hw_info.h"
#include "halbb_dbcc_ex.h"
/*@--------------------------[Define] ---------------------------------------*/
#define IGI_2_RSSI(igi) (igi - 10)
#define FUNC_ENABLE 1
#define FUNC_DISABLE 2
#define BB_CH_SWH_HISTORY_SIZE 50
/*@--------------------------[Enum]------------------------------------------*/
enum bb_rfe_src_sel {
PAPE_RFM = 0,
GNT_BT_INV = 1,
LNA0N = 2,
LNAON_RFM = 3,
TRSW_RFM = 4,
TRSW_RFM_B = 5,
GNT_BT = 6,
ZERO = 7,
ANTSEL_0 = 8,
ANTSEL_1 = 9,
ANTSEL_2 = 0xa,
ANTSEL_3 = 0xb,
ANTSEL_4 = 0xc,
ANTSEL_5 = 0xd,
ANTSEL_6 = 0xe,
ANTSEL_7 = 0xf
};
enum bb_mlo {
MLO_OFF_BB0,
MLO_OFF_BB1,
MLO_ON
};
enum bb_scan_mode{
BB_SCAN_DISABLE = 0,
BB_DRV_SCAN = 1,
BB_P2P_SCAN = 2,
BB_MRDM_SCAN = 3,
BB_MAX_SCAN
};
/*@--------------------------[Structure]-------------------------------------*/
struct bb_api_info {
u32 rxiqc_reg1; /*N-mode: for pathA REG0xc14*/
u32 rxiqc_reg2; /*N-mode: for pathB REG0xc1c*/
u8 tx_queue_bitmap; /*REG0x520[23:16]*/
u8 ccktx_path;
u8 pri_ch_idx;
u8 central_ch;
u8 bw;
u16 ch_switch_cnt;
u8 ch_switch_history[BB_CH_SWH_HISTORY_SIZE]; /*fc CH*/
u8 ch_switch_ptr;
enum band_type band;
};
/*@--------------------------[Prptotype]-------------------------------------*/
struct bb_info;
enum bb_band_gt2_t halbb_get_band_gen2(struct bb_info *bb, u8 fc_ch,
enum band_type band_in);
enum bb_bw_type halbb_phl_2_bb_bw(struct bb_info *bb, enum channel_width phl_bw);
u8 halbb_dbcc_get_valid_rf_path_mask(struct bb_info *bb);
u8 halbb_ch_2_band(struct bb_info *bb, u8 fc_ch);
u16 halbb_get_csi_buf_idx(struct bb_info *bb, u8 buf_idx, u8 txsc_idx);
void halbb_reset_bb_phy(struct bb_info *bb, enum phl_phy_idx phy_idx);
void halbb_gpio_setting_init(struct bb_info *bb);
void halbb_pre_agc_en(struct bb_info *bb, bool enable);
void halbb_set_gain_error(struct bb_info *bb, u8 central_ch, enum band_type band, enum rf_path path);
u8 halbb_stop_ic_trx(struct bb_info *bb, u8 set_type);
void halbb_ic_api_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len);
u16 halbb_fc_mapping(struct bb_info *bb, enum band_type band, u8 central_ch);
u8 halbb_gain_band_determine(struct bb_info *bb, u8 central_ch,
enum band_type band_type);
void halbb_ic_hw_setting_non_io(struct bb_info *bb);
void halbb_ic_hw_setting_low_io(struct bb_info *bb);
void halbb_ic_hw_setting_dbcc(struct bb_info *bb);
void halbb_ic_hw_setting(struct bb_info *bb);
void halbb_ic_hw_setting_dbg(struct bb_info *bb, char input[][16],
u32 *_used, char *output, u32 *_out_len);
#ifdef HALBB_PATH_DIV_SUPPORT
void halbb_ctrl_tx_path_div(struct bb_info * bb, enum bb_path tx_path_1ss);
void halbb_ctrl_path_div_6g(struct bb_info *bb, bool is_disable_6g);
#endif
void halbb_pwr_diff_wa_enable(struct bb_info *bb, enum phl_phy_idx phy_idx);
void halbb_pwr_diff_wa_disable(struct bb_info *bb, enum phl_phy_idx phy_idx);
void halbb_per_macid_tx_path_init(struct bb_info *bb, u16 macid);
void halbb_set_cctrl_tbl(struct bb_info *bb, u16 macid, u16 cfg);
enum rf_path halbb_bb_path_2_rf_path(struct bb_info *bb, enum bb_path path_in);
void halbb_api_init(struct bb_info *bb);
void halbb_cfg_scan_mode(struct bb_info *bb, enum phl_msg_evt_id event, bool is_start, enum phl_phy_idx phy_idx);
#endif
3rd/devourer/hal/halbb/g6/vendor/halbb_api_be.h
Vendored
+30
View File
@@ -0,0 +1,30 @@
/******************************************************************************
*
* Copyright(c) 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HALBB_API_BE_H_
#define _HALBB_API_BE_H_
/*@--------------------------[Define] ---------------------------------------*/
/*@--------------------------[Enum]------------------------------------------*/
/*@--------------------------[Structure]-------------------------------------*/
/*@--------------------------[Prptotype]-------------------------------------*/
struct bb_info;
u8 halbb_get_prim_sb(struct bb_info *bb, u8 central_ch, u8 pri_ch,
enum channel_width bw);
#endif
3rd/devourer/hal/halbb/g6/vendor/halbb_api_be_ex.h
Vendored
+34
View File
@@ -0,0 +1,34 @@
/******************************************************************************
*
* Copyright(c) 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HALBB_API_BE_EX_H_
#define _HALBB_API_BE_EX_H_
/*@--------------------------[Define] ---------------------------------------*/
/*@--------------------------[Enum]------------------------------------------*/
/*@--------------------------[Structure]-------------------------------------*/
/*@--------------------------[Prptotype]-------------------------------------*/
struct bb_info;
u16 halbb_pri20_bitmap(struct bb_info *bb, u8 central_ch, u8 pri_ch,
enum channel_width bw);
u16 halbb_preamble_puncture(struct bb_info *bb, u8 central_ch, u8 pri_ch,
enum channel_width cbw, enum channel_width dbw,
u8 punc_ch_info);
#endif
3rd/devourer/hal/halbb/g6/vendor/halbb_api_be_hw.h
Vendored
+39
View File
@@ -0,0 +1,39 @@
/******************************************************************************
*
* Copyright(c) 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HALBB_API_BE_HW_H_
#define _HALBB_API_BE_HW_H_
/*@--------------------------[Define] ---------------------------------------*/
/*@--------------------------[Enum]------------------------------------------*/
/*@--------------------------[Structure]-------------------------------------*/
/*@--------------------------[Prptotype]-------------------------------------*/
struct bb_info;
u8 halbb_get_prim_sb_be(struct bb_info *bb, u8 central_ch, u8 pri_ch,
enum channel_width bw);
u16 halbb_pri20_bitmap_be(struct bb_info *bb, u8 central_ch, u8 pri_ch,
enum channel_width bw);
u16 halbb_ch20_with_data_lut_be(struct bb_info *bb, enum channel_width dbw,
u8 punc_ch_info);
u16 halbb_preamble_puncture_be(struct bb_info *bb, u8 central_ch, u8 pri_ch,
enum channel_width cbw, enum channel_width dbw,
u8 punc_ch_info);
#endif
3rd/devourer/hal/halbb/g6/vendor/halbb_api_be_intg.h
Vendored
+27
View File
@@ -0,0 +1,27 @@
/******************************************************************************
*
* Copyright(c) 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HALBB_API_BE_INTG_H_
#define _HALBB_API_BE_INTG_H_
/*@--------------------------[Define] ---------------------------------------*/
/*@--------------------------[Enum]------------------------------------------*/
/*@--------------------------[Structure]-------------------------------------*/
/*@--------------------------[Prptotype]-------------------------------------*/
struct bb_info;
#endif
3rd/devourer/hal/halbb/g6/vendor/halbb_api_be_sw.h
Vendored
+27
View File
@@ -0,0 +1,27 @@
/******************************************************************************
*
* Copyright(c) 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HALBB_API_BE_SW_H_
#define _HALBB_API_BE_SW_H_
/*@--------------------------[Define] ---------------------------------------*/
/*@--------------------------[Enum]------------------------------------------*/
/*@--------------------------[Structure]-------------------------------------*/
/*@--------------------------[Prptotype]-------------------------------------*/
struct bb_info;
#endif
3rd/devourer/hal/halbb/g6/vendor/halbb_api_ex.h
Vendored
+232
View File
@@ -0,0 +1,232 @@
/******************************************************************************
*
* Copyright(c) 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HALBB_API_EX_H_
#define _HALBB_API_EX_H_
#include "halbb_ic_hw_info.h"
#include "halbb_api.h"
/*@--------------------------[Prptotype]-------------------------------------*/
struct bb_info;
#define MAX_MR_NUM 3
struct bb_mcc_i {
enum role_type type;
struct rtw_chan_def *chandef;
u32 *macid_bitmap;
u8 macid_map_len;
u8 self_macid;
};
struct bb_mr_i {
struct rtw_chan_def chandef;
u8 *all_macid; /* all used macid bitmap */
u8 all_macid_len;
};
struct bb_mrdm_i {
enum phl_phy_idx phy_idx;
struct bb_mr_i mr_info[MAX_MR_NUM];
u8 mr_num;
};
u8 halbb_ex_cn_report(struct bb_info * bb);
u8 halbb_ex_evm_1ss_report(struct bb_info *bb);
u8 halbb_ex_evm_max_report(struct bb_info *bb);
u8 halbb_ex_evm_min_report(struct bb_info *bb);
bool halbb_tx_cfr_byrate_sup(struct bb_info *bb);
u16 halbb_cfg_cmac_tx_ant(struct bb_info *bb, enum rf_path tx_path);
void halbb_gpio_setting_all(struct bb_info *bb, u8 rfe_idx);
void halbb_gpio_setting(struct bb_info *bb, u8 gpio_idx, enum bb_path path,
bool inv, enum bb_rfe_src_sel src);
u8 halbb_get_txsc(struct bb_info *bb, u8 pri_ch, u8 central_ch,
enum channel_width cbw, enum channel_width dbw);
u8 halbb_get_txsb(struct bb_info *bb, u8 pri_ch, u8 central_ch,
enum channel_width cbw, enum channel_width dbw);
void halbb_bb_reset_all(struct bb_info *bb, enum phl_phy_idx phy_idx);
bool halbb_bb_reset_cmn(struct bb_info *bb, bool en, enum phl_phy_idx phy_idx);
void halbb_reset_bb(struct bb_info *bb);
u32 halbb_read_rf_reg_dbg(struct bb_info *bb, enum rf_path path, u32 addr);
u32 halbb_read_rf_reg(struct bb_info *bb, enum rf_path path, u32 addr, u32 mask);
bool halbb_write_rf_reg(struct bb_info *bb, enum rf_path path, u32 addr, u32 mask,
u32 data);
bool halbb_rf_set_bb_reg(struct bb_info *bb, u32 addr, u32 bit_mask, u32 data);
u32 halbb_rf_get_bb_reg(struct bb_info *bb, u32 addr, u32 mask);
void halbb_ctrl_rf_mode(struct bb_info *bb, enum phl_rf_mode mode);
void halbb_ctrl_rf_mode_rx_path(struct bb_info *bb, enum rf_path rx_path);
bool halbb_ctrl_tx_path_bb_afe_map(struct bb_info *bb, u8 mapping_idx);
bool halbb_ctrl_rx_path(struct bb_info *bb, enum rf_path rx_path,
enum phl_phy_idx phy_idx);
bool halbb_ctrl_tx_path_pmac(struct bb_info *bb, enum rf_path tx_path,
enum phl_phy_idx phy_idx);
bool halbb_cfg_rx_path(struct bb_info *bb, enum bb_path rx_path,
enum phl_phy_idx phy_idx);
bool halbb_cfg_tx_path_pmac(struct bb_info *bb, enum bb_path tx_path,
enum phl_phy_idx phy_idx);
bool halbb_cfg_tx_path(struct bb_info *bb, enum bb_path tx_path,
enum phl_phy_idx phy_idx);
void halbb_ctrl_trx_path(struct bb_info *bb, enum rf_path tx_path, u8 tx_nss,
enum rf_path rx_path, u8 rx_nss);
void halbb_cfg_trx_path(struct bb_info *bb, struct bb_tx_path_en_info tx_path_i,
struct bb_rx_path_en_info rx_path_i, enum mlo_dbcc_mode_type mode);
void halbb_tssi_bb_reset(struct bb_info *bb);
void halbb_dfs_en(struct bb_info *bb, bool en);
void halbb_adc_ctrl_en(struct bb_info *bb, bool en, enum phl_phy_idx phy_idx);
void halbb_adc_en(struct bb_info *bb, bool en);
bool halbb_adc_cfg(struct bb_info *bb, enum channel_width bw, enum rf_path path,
enum phl_phy_idx phy_idx);
void halbb_tssi_cont_en(struct bb_info *bb, bool en, enum rf_path path);
void halbb_bb_reset_en(struct bb_info *bb, bool en, enum phl_phy_idx phy_idx);
bool halbb_ctrl_bw(struct bb_info *bb, u8 pri_ch, enum band_type band, enum channel_width bw,
enum phl_phy_idx phy_idx);
bool halbb_ctrl_bw_ch(struct bb_info *bb, u8 pri_ch, u8 central_ch_seg0,
u8 central_ch_seg1, enum band_type band,
enum channel_width bw, enum phl_phy_idx phy_idx);
bool halbb_ctrl_op_ch_pd(struct bb_info *bb_0, bool is_op_ch, u8 central_ch,
enum band_type band, enum channel_width bw,
enum phl_phy_idx phy_idx);
void halbb_op_ch_info_update(struct bb_info *bb, bool enable,
enum phl_phy_idx phy_idx);
#if (HLABB_CODE_BASE_NUM >= 32)
bool halbb_pre_ctrl_bw_ch(struct bb_info *bb, enum phl_phy_idx phy_idx);
bool halbb_post_ctrl_bw_ch(struct bb_info *bb, enum phl_phy_idx phy_idx);
#endif
void halbb_ctrl_rx_cca(struct bb_info *bb, bool cca_en, enum phl_phy_idx phy_idx);
bool halbb_query_cck_en(struct bb_info *bb, enum phl_phy_idx phy_idx);
void halbb_ctrl_cck_en(struct bb_info *bb, bool cck_enable,
enum phl_phy_idx phy_idx);
void halbb_ctrl_ofdm_en(struct bb_info *bb, bool ofdm_enable,
enum phl_phy_idx phy_idx);
void halbb_ctrl_btg(struct bb_info *bb, bool btg);
void halbb_ctrl_btc_preagc(struct bb_info *bb, bool bt_en);
void halbb_btg_bt_rx(struct bb_info *bb, bool en, enum phl_phy_idx phy_idx);
void halbb_nbtg_bt_tx(struct bb_info *bb, bool en, enum phl_phy_idx phy_idx);
void halbb_bt_btg_trx_cmn(struct bb_info *bb, bool btg, bool bt_en, bool is_2g,
enum phl_phy_idx phy_idx);
void halbb_pop_en(struct bb_info *bb, bool en, enum phl_phy_idx phy_idx);
bool halbb_querry_pop_en(struct bb_info *bb, enum phl_phy_idx phy_idx);
bool halbb_set_pd_lower_bound(struct bb_info *bb, u8 bound,
enum channel_width bw, enum phl_phy_idx phy_idx);
bool halbb_set_pd_lower_bound_cck(struct bb_info *bb, u8 bound,
enum channel_width bw, enum phl_phy_idx phy_idx);
u8 halbb_querry_pd_lower_bound(struct bb_info *bb, bool get_en_info,
enum phl_phy_idx phy_idx);
u8 halbb_get_losel(struct bb_info *bb);
void halbb_set_ant(struct bb_info *bb, u8 ant);
void halbb_syn_sel(struct bb_info *bb, enum rf_path path, bool val,
enum phl_phy_idx phy_idx);
void halbb_bb_wrap_set_pow_by_rate_all(struct bb_info *bb, enum phl_phy_idx phy_idx);
void halbb_bb_wrap_set_pwr_limit_rua_all(struct bb_info *bb, enum phl_phy_idx phy_idx);
void halbb_bb_wrap_set_pwr_limit_all(struct bb_info *bb, enum phl_phy_idx phy_idx);
void halbb_bb_wrap_set_pwr_ofst_mode_all(struct bb_info *bb, enum phl_phy_idx phy_idx);
void halbb_bb_wrap_set_pwr_ofst_bw_all(struct bb_info *bb, enum phl_phy_idx phy_idx);
void halbb_bb_wrap_set_pwr_limit_en(struct bb_info *bb, enum phl_phy_idx phy_idx);
void halbb_bb_wrap_set_max_pwr_limit(struct bb_info *bb, enum phl_phy_idx phy_idx, s16 max_limit);
enum rtw_hal_status halbb_emlsr_en(struct bb_info *bb, bool en);
#if (HLABB_CODE_BASE_NUM >= 32)
bool halbb_ctrl_mlo(struct bb_info *bb, enum mlo_dbcc_mode_type mode);
#endif
void halbb_set_igi(struct bb_info *bb, u8 lna_idx, bool tia_idx, u8 rxbb_idx,
enum rf_path path);
void halbb_set_tx_pow_pattern_shap(struct bb_info *bb, u8 ch,
bool is_ofdm, enum phl_phy_idx phy_idx);
void halbb_set_tx_pow_per_path_lmt(struct bb_info *bb, s16 pwr_lmt_a, s16 pwr_lmt_b);
void halbb_set_tx_pow_ref(struct bb_info *bb, enum phl_phy_idx phy_idx);
void halbb_normal_efuse_verify(struct bb_info *bb, s8 rx_gain_offset,
enum rf_path rx_path, enum phl_phy_idx phy_idx);
u8 halbb_upd_mcc_macid(struct bb_info *bb, struct bb_mcc_i *mi);
void halbb_mcc_stop(struct bb_info *bb);
u8 halbb_mcc_start(struct bb_info *bb, struct bb_mcc_i *mi_1,
struct bb_mcc_i *mi_2);
u8 halbb_mrdm_start(struct bb_info *bb, u8 phy_type, struct bb_mrdm_i *mrdm);
void halbb_mrdm_stop(struct bb_info *bb, u8 phy_type);
u8 halbb_upd_mrdm_macid(struct bb_info *bb, struct bb_mrdm_i *mrdm);
void halbb_normal_efuse_verify_cck(struct bb_info *bb, s8 rx_gain_offset,
enum rf_path rx_path,
enum phl_phy_idx phy_idx);
enum rtw_hal_status halbb_config_cmac_tbl(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i,
void *cctrl,
void *cctl_info_mask);
extern bool halbb_lps_info(struct bb_info *bb, u16 mac_id);
extern bool halbb_lps_save_ch_info(struct bb_info *bb);
extern bool halbb_lps_info_status_chk(struct bb_info *bb);
void halbb_agc_fix_gain(struct bb_info *bb, bool enable, enum rf_path path,
enum phl_phy_idx phy_idx);
void halbb_agc_elna_idx(struct bb_info *bb, bool elna_idx, enum rf_path path,
enum phl_phy_idx phy_idx);
void halbb_agc_tia_shrink(struct bb_info *bb, bool shrink_en, bool shrink_init,
enum rf_path path, enum phl_phy_idx phy_idx);
void halbb_npath_en_update(struct bb_info *bb, bool npath_en);
void halbb_update_tx_path_div(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i);
void halbb_nvar_src_sel(struct bb_info *bb, bool is_BF);
void halbb_1ss_4tx_csd_set(struct bb_info *bb, bool is_no_csd, enum phl_phy_idx phy_idx);
void halbb_force_cfo_one_shot_comp_en(struct bb_info *bb, bool en, enum phl_phy_idx phy_idx);
void halbb_extra_rx_path(struct bb_info *bb, bool en, enum bb_path rx_path, enum phl_phy_idx phy_idx);
#endif
3rd/devourer/hal/halbb/g6/vendor/halbb_auto_dbg.h
Vendored
+60
View File
@@ -0,0 +1,60 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_AUTO_DBG_H__
#define __HALBB_AUTO_DBG_H__
#ifdef HALBB_AUTO_DBG_SUPPORT
/*@--------------------------[Define] ---------------------------------------*/
/*@--------------------------[Enum]------------------------------------------*/
/*@--------------------------[Structure]-------------------------------------*/
struct bb_chk_hang_info {
u32 table_size;
u32 *dbg_port_table;
u32 *dbg_port_val;
};
struct bb_auto_dbg_info {
u32 auto_dbg_type; /*enum bb_auto_dbg_t*/
struct bb_chk_hang_info bb_chk_hang_i;
struct bb_bkp_pmac_info bb_bkp_pmac_i;
struct bb_bkp_phy_utility_info bb_bkp_phy_utility_i;
struct bb_stat_hang_info bb_bkp_stat_hang_i;
};
struct bb_info;
/*@--------------------------[Prptotype]-------------------------------------*/
void halbb_auto_debug_watchdog(struct bb_info *bb);
void halbb_auto_debug_init(struct bb_info *bb);
void halbb_auto_debug_dbg(struct bb_info *bb, char input[][16],
u32 *_used, char *output, u32 *_out_len);
#ifdef HALBB_SELF_DIAG_SUPPORT
void halbb_diagnostic_event_notify(struct bb_info *bb, enum habb_fun_t type, u8 sub_type);
#endif
#endif
#endif
3rd/devourer/hal/halbb/g6/vendor/halbb_auto_dbg_ex.h
Vendored
+82
View File
@@ -0,0 +1,82 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_AUTO_DBG_EX_H__
#define __HALBB_AUTO_DBG_EX_H__
#ifdef HALBB_AUTO_DBG_SUPPORT
#include "halbb_statistics.h"
/*@--------------------------[Define] ---------------------------------------*/
/*@--------------------------[Enum]------------------------------------------*/
enum bb_auto_dbg_t {
AUTO_DBG_CHECK_HANG = 0,
AUTO_DBG_CHECK_TX = 1,
AUTO_DBG_STORE_PMAC = 2,
AUTO_DBG_PHY_UTILITY = 3
};
enum bb_dig_sub_t {
MAX_DYN_PD = 0,
MAX_PD_SUB_TYPE =1
};
enum bb_fa_cnt_sub_t {
RX_HANG = 0,
HIGH_FA_RATIO = 1,
MAX_FA_CNT_SUB_TYPE =2
};
enum bb_edcca_sub_t{
TX_HANG = 0
};
/*@--------------------------[Structure]-------------------------------------*/
struct bb_bkp_phy_utility_info {
u16 rx_utility;
u16 avg_phy_rate;
u16 rx_rate_plurality;
u16 tx_rate;
struct bb_physts_avg_info bb_physts_avg_i;
};
struct bb_bkp_pmac_info {
struct bb_tx_cnt_info bb_tx_cnt_i;
struct bb_cca_info bb_cca_i;
struct bb_crc_info bb_crc_i;
struct bb_crc2_info bb_crc2_i;
struct bb_fa_info bb_fa_i;
struct bb_usr_set_info bb_usr_set_i;
};
struct bb_info;
/*@--------------------------[Prptotype]-------------------------------------*/
void halbb_query_hang_info(struct bb_info *bb, struct bb_stat_hang_info *rpt, enum phl_phy_idx phy_idx);
void halbb_query_pmac_info(struct bb_info *bb, struct bb_bkp_pmac_info *rpt, enum phl_phy_idx phy_idx);
void halbb_direct_query_pmac_cr_info(struct bb_info *bb_0, struct bb_bkp_pmac_info *rpt, enum phl_phy_idx phy_idx);
void halbb_query_phy_utility_info(struct bb_info *bb, struct bb_bkp_phy_utility_info *rpt, enum phl_phy_idx phy_idx);
void halbb_auto_debug_en(struct bb_info *bb, enum bb_auto_dbg_t dbg_type, bool en);
#endif
#endif
3rd/devourer/hal/halbb/g6/vendor/halbb_bb_wrapper.h
Vendored
+33
View File
@@ -0,0 +1,33 @@
/******************************************************************************
*
* Copyright(c) 2019 - 2021 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef __HALBB_BB_WRAPPER_H__
#define __HALBB_BB_WRAPPER_H__
/*@--------------------------[Define] ---------------------------------------*/
#define ANT_GAIN_2P4G 14 // 3.5 dbi, ant gain divided by 4
#define ANT_GAIN_56G 20 // 5 dbi, ant gain divided by 4
struct bb_info;
/*@--------------------------[Prptotype]-------------------------------------*/
//void halbb_tmac_force_tx_pwr(struct bb_info *bb, s8 pw_val, u8 n_path, u8 dbw_idx, enum phl_phy_idx phy_idx);
void halbb_bb_wrap_tpu_set_all(struct bb_info* bb, enum phl_phy_idx phy_idx);
void halbb_bb_wrap_init(struct bb_info *bb_0, enum phl_phy_idx phy_idx);
void halbb_bb_wrap_dbg_be(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len);
void halbb_bb_wrap_be_set_pwr_ref_all(struct bb_info *bb, enum phl_phy_idx phy_idx);
//void halbb_bb_wrap_set_tx_src(struct bb_info *bb, u8 option, s8 pw_val, u8 n_path, u8 dbw_idx, enum phl_phy_idx phy_idx);
#endif
3rd/devourer/hal/halbb/g6/vendor/halbb_bb_wrapper_outsrc.h
Vendored
+228
View File
@@ -0,0 +1,228 @@
/******************************************************************************
*
* Copyright(c) 2019 - 2021 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef __HALBB_BB_WRAPPER_OUTSRC_H__
#define __HALBB_BB_WRAPPER_OUTSRC_H__
#include "halbb_ic_hw_info.h"
/*--------------------------------------------------------------------------*/
/*[TX Power Unit(TPU) array size]*/
#define TPU_SIZE_PWR_TAB 16 /*MCS0~MCS11(12) + {dcm_0,1,3,4}4 = 16*/
#define TPU_SIZE_PWR_TAB_BE 18 /*MCS0~MCS13(14) + {dcm_0,1,3,4}4 = 18*/
#define TPU_SIZE_PWR_TAB_CCK 4 /*1M, 2M, 5p5M, 11M*/
#define TPU_SIZE_PWR_TAB_OFDM 8 /*6M, 9M, 12M, 18M, 24M, 36M, 48M, 54M*/
#define TPU_SIZE_PWR_TAB_lGCY 12 /*cck(4) + ofdm(8) = 12*/
#define TPU_SIZE_PWR_TAB_EHT_BE 4 /*MCS14, MCS15, dlru_MCS14, dlru_MCS15*/
#define TPU_SIZE_PWR_TAB_DBW 5 /*DBW20, 40, 80, 160, 320*/
#define TPU_SIZE_PWR_TAB_DBW_CCK 2 /*DBW20, 40*/
#define TPU_SIZE_MODE 5 /*0~4: HE, VHT, HT, Legacy, CCK, */
#define TPU_SIZE_MODE_BE 8 /*0~7: CCK, Legacy, HT, VHT, HE, EHT, dlru_HE, dlru_EHT*/
#define TPU_SIZE_BW 5 /*0~4: 80_80, 160, 80, 40, 20*/
#define TPU_SIZE_BW_BE 10 /*0~9: 20, 40, 80, 160, 320, dlru_20, dlru_40, dlru_80, dlru_160, dlru_320*/
#define TPU_SIZE_RUA 3 /* {26, 52, 106} */
#define TPU_SIZE_BW20_SC 8 /* 8 * 20M = 160M */
#define TPU_SIZE_BW40_SC 4 /* 4 * 40M = 160M */
#define TPU_SIZE_BW80_SC 2 /* 2 * 80M = 160M */
#define TPU_SIZE_BW20_SC_BE 16 /* 16 * 20M = 320M */
#define TPU_SIZE_BW40_SC_BE 8 /* 8 * 40M = 320M */
#define TPU_SIZE_BW80_SC_BE 4 /* 4 * 80M = 320M */
#define TPU_SIZE_BW160_SC_BE 2 /* 2 * 160M = 320M */
#define TPU_SIZE_BF 2 /*{NON_BF, BF}*/
#define TPU_SIZE_0P5_6P5 4 /* BW40_0p5, BW40_2p5, BW40_4p5, BW40_6p5 */
#define TPU_SIZE_CCK_LMT_BW 2 /* 20M, 40M */
/*--------------------------[Structure]-------------------------------------*/
enum rtw_tpu_op_mode {
TPU_NORMAL_MODE = 0,
TPU_DBG_MODE = 1
};
/*===== [AX] ===============================================================*/
#define AX_IC_TPU
#ifdef AX_IC_TPU
struct rtw_ext_pwr_lmt_info { /* external tx power limit information */
s8 ext_pwr_lmt_2_4g[RTW_PHL_MAX_RF_PATH];
s8 ext_pwr_lmt_5g_band1[RTW_PHL_MAX_RF_PATH]; /*CH36 ~ CH48*/
s8 ext_pwr_lmt_5g_band2[RTW_PHL_MAX_RF_PATH]; /*CH52 ~ CH64*/
s8 ext_pwr_lmt_5g_band3[RTW_PHL_MAX_RF_PATH]; /*CH100 ~ CH144*/
s8 ext_pwr_lmt_5g_band4[RTW_PHL_MAX_RF_PATH]; /*CH149 ~ CH165*/
s8 ext_pwr_lmt_6g[RTW_PHL_MAX_RF_PATH];
};
struct rtw_tpu_pwr_by_rate_info { /*TX Power Unit (TPU)*/
s8 pwr_by_rate_lgcy[TPU_SIZE_PWR_TAB_lGCY];
s8 pwr_by_rate[HALBB_MAX_PATH][TPU_SIZE_PWR_TAB];
};
struct rtw_tpu_pwr_imt_info { /*TX Power Unit (TPU)*/
s8 pwr_lmt_cck_20m[HALBB_MAX_PATH][TPU_SIZE_BF];
s8 pwr_lmt_cck_40m[HALBB_MAX_PATH][TPU_SIZE_BF];
s8 pwr_lmt_lgcy_20m[HALBB_MAX_PATH][TPU_SIZE_BF]; /*ofdm*/
s8 pwr_lmt_20m[HALBB_MAX_PATH][TPU_SIZE_BW20_SC][TPU_SIZE_BF];
s8 pwr_lmt_40m[HALBB_MAX_PATH][TPU_SIZE_BW40_SC][TPU_SIZE_BF];
s8 pwr_lmt_80m[HALBB_MAX_PATH][TPU_SIZE_BW80_SC][TPU_SIZE_BF];
s8 pwr_lmt_160m[HALBB_MAX_PATH][TPU_SIZE_BF];
s8 pwr_lmt_40m_0p5[HALBB_MAX_PATH][TPU_SIZE_BF];
s8 pwr_lmt_40m_2p5[HALBB_MAX_PATH][TPU_SIZE_BF];
};
struct rtw_tpu_info { /*TX Power Unit (TPU)*/
enum rtw_tpu_op_mode op_mode; /*In debug mode, only debug tool control TPU APIs*/
bool normal_mode_lock_en;
s8 ofst_int; /* Select the path with lower pow and subtract pow_path_ofst_decrease from path_ref*/
u8 ofst_fraction; /*[0:3] * 0.125(dBm)*/
enum bb_path ref_pow_path; /*Select the path with larger pow as the re_ path*/
u8 path_pow_ofst_decrease; /* Select the path with lower pow and subtract pow_path_ofst_decrease from path_ref*/
u8 base_cw_0db; /*[63~39~15]: [+24~0~-24 dBm]*/
u16 tssi_16dBm_cw;
/*[Ref Pwr]*/
s16 ref_pow_ofdm; /*-> HW: s(9,2)*/
s16 ref_pow_cck; /*-> HW: s(9,2)*/
u16 ref_pow_ofdm_cw; /*BBCR 0x58E0[9:0]*/
u16 ref_pow_cck_cw; /*BBCR 0x58E0[21:12]*/
/*[Pwr Ofsset]*/ /*-> HW: s(7,1)*/
s8 pwr_ofst_mode[TPU_SIZE_MODE]; /*0~4: HE, VHT, HT, Legacy, CCK, */
s8 pwr_ofst_bw[TPU_SIZE_BW]; /*0~4: 80_80, 160, 80, 40, 20*/
/*[Pwr By rate]*/ /*-> HW: s(7,1)*/
struct rtw_tpu_pwr_by_rate_info rtw_tpu_pwr_by_rate_i;
/*[Pwr Limit]*/ /*-> HW: s(7,1)*/
struct rtw_tpu_pwr_imt_info rtw_tpu_pwr_imt_i;
/*[Pwr Limit RUA]*/ /*-> HW: s(7,1)*/
s8 pwr_lmt_ru[HALBB_MAX_PATH][TPU_SIZE_RUA][TPU_SIZE_BW20_SC];
u16 pwr_lmt_ru_mem_size;
bool pwr_lmt_en;
bool ext_pwr_lmt_en;
struct rtw_phl_ext_pwr_lmt_info ext_pwr_lmt_i;
u8 tx_ptrn_shap_idx;
u8 tx_ptrn_shap_idx_cck;
u16 pwr_constraint_mb;
};
#endif
/*===== [BE] ===============================================================*/
#define BE_IC_TPU
#if defined(BB_8952A_SUPPORT)
#define HALBB_TX_RFSI_CTRL_SUPPORT
#endif
#ifdef BE_IC_TPU
struct bb_tpu_pwr_by_rate_info_be { /*TX Power Unit (TPU)*/
s8 pwr_by_rate_cck[TPU_SIZE_PWR_TAB_DBW_CCK][TPU_SIZE_PWR_TAB_CCK]; /* {DBW20, DBW40} x {1M, 2M, 5p5M, 11M}*/
s8 pwr_by_rate_ofdm[TPU_SIZE_PWR_TAB_DBW][TPU_SIZE_PWR_TAB_OFDM]; /* {DBW20~DBW320} x {6M, 9M, 12M, 18M, 24M, 36M, 48M, 54M}*/
s8 pwr_by_rate_mcs[TPU_SIZE_PWR_TAB_DBW][HALBB_MAX_PATH][TPU_SIZE_PWR_TAB_BE]; /* {DBW20~DBW320} x {{path_i}_{i is enable}} x {MCS_idx:0~13, dcm_0,1,3,4} */
s8 pwr_by_rate_eht[TPU_SIZE_PWR_TAB_DBW][TPU_SIZE_PWR_TAB_EHT_BE]; /* {DBW20~DBW320} x {MCS14, MCS15, dlru_MCS14, dlru_MCS15} */
s8 pwr_by_rate_dlru[TPU_SIZE_PWR_TAB_DBW][HALBB_MAX_PATH][TPU_SIZE_PWR_TAB_BE]; /* {DBW20~DBW320} x {{path_i}_{i is enable}} x {MCS_idx:0~13, dcm_0,1,3,4} */
};
struct bb_tpu_pwr_lmt_info_be { /*TX Power Unit (TPU)*/
s8 pwr_lmt_cck[HALBB_MAX_PATH][TPU_SIZE_CCK_LMT_BW][TPU_SIZE_BF]; /* {{path_i}_{i is enable}} x {BW20, BW40} x {non-BF/BF} */
s8 pwr_lmt_lgcy_non_dup[HALBB_MAX_PATH][TPU_SIZE_BF]; /* {{path_i}_{i is enable}} x {non-BF/BF} */
s8 pwr_lmt_20m[HALBB_MAX_PATH][TPU_SIZE_BW20_SC_BE][TPU_SIZE_BF]; /* {{path_i}_{i is enable}} x {1,2,...,16} x {non-BF/BF} */
s8 pwr_lmt_40m[HALBB_MAX_PATH][TPU_SIZE_BW40_SC_BE][TPU_SIZE_BF]; /* {{path_i}_{i is enable}} x {1,2,...,8} x {non-BF/BF} */
s8 pwr_lmt_80m[HALBB_MAX_PATH][TPU_SIZE_BW80_SC_BE][TPU_SIZE_BF]; /* {{path_i}_{i is enable}} x {1,2,3,4} x {non-BF/BF} */
s8 pwr_lmt_160m[HALBB_MAX_PATH][TPU_SIZE_BW160_SC_BE][TPU_SIZE_BF]; /* {{path_i}_{i is enable}} x {1,2} x {non-BF/BF} */
s8 pwr_lmt_320m[HALBB_MAX_PATH][TPU_SIZE_BF]; /* {{path_i}_{i is enable}} x {non-BF/BF} */
s8 pwr_lmt_40m_0p5[HALBB_MAX_PATH][TPU_SIZE_BF]; /* {{path_i}_{i is enable}} x {non-BF/BF} */
s8 pwr_lmt_40m_2p5[HALBB_MAX_PATH][TPU_SIZE_BF]; /* {{path_i}_{i is enable}} x {non-BF/BF} */
s8 pwr_lmt_40m_4p5[HALBB_MAX_PATH][TPU_SIZE_BF]; /* {{path_i}_{i is enable}} x {non-BF/BF} */
s8 pwr_lmt_40m_6p5[HALBB_MAX_PATH][TPU_SIZE_BF]; /* {{path_i}_{i is enable}} x {non-BF/BF} */
};
struct bb_tpu_pwr_lmt_ru_info_be { /*TX Power Unit (TPU)*/
s8 pwr_lmt_ru_be[HALBB_MAX_PATH][TPU_SIZE_RUA][TPU_SIZE_BW20_SC_BE]; /* {{path_i}_{i is enable}} x {26, 52, 106} x {0~15: 16 * 20M = 320M } */
s8 pwr_lmt_ru52_26_be[HALBB_MAX_PATH][TPU_SIZE_BW20_SC_BE]; /* {{path_i}_{i is enable}} x {0~15: 16 * 20M = 320M } */
s8 pwr_lmt_ru106_26_be[HALBB_MAX_PATH][TPU_SIZE_BW20_SC_BE]; /* {{path_i}_{i is enable}} x {0~15: 16 * 20M = 320M } */
};
#ifdef HALBB_TX_RFSI_CTRL_SUPPORT
struct bb_cfr_ofst_info_be {
u8 cfr_ofst_cck[HALBB_MAX_PATH];
u8 cfr_ofst_cck_dup[HALBB_MAX_PATH];
u8 cfr_ofst_lgcy_non_dup[HALBB_MAX_PATH];
u8 cfr_ofst_20m[HALBB_MAX_PATH];
u8 cfr_ofst_40m[HALBB_MAX_PATH];
u8 cfr_ofst_80m[HALBB_MAX_PATH];
u8 cfr_ofst_160m[HALBB_MAX_PATH];
u8 cfr_ofst_320m[HALBB_MAX_PATH];
};
struct bb_cfr_pwr_th_info_be {
s16 cfr_pwr_th[TPU_SIZE_PWR_TAB_DBW];
};
#endif
struct bb_tpu_be_info { /*TX Power Unit (TPU)*/
/*[Pwr By rate for BE]*/ /*-> HW: s(7,1)*/
struct bb_tpu_pwr_by_rate_info_be rtw_tpu_pwr_by_rate_be_i;
/*[Pwr Limit for BE]*/ /*-> HW: s(7,1)*/
struct bb_tpu_pwr_lmt_info_be rtw_tpu_pwr_lmt_be_i;
/*[Pwr Limit By RU for BE]*/ /*-> HW: s(7,1)*/
struct bb_tpu_pwr_lmt_ru_info_be rtw_tpu_pwr_lmt_ru_be_i;
s8 pwr_cck_dup_patha_l_pathb_h_2tx; /*-> HW: s(7.1)*/
s8 pwr_cck_dup_patha_h_pathb_l_2tx; /*-> HW: s(7.1)*/
/*[Ref Pwr]*/
enum bb_path ref_pow_path; /*Select the path with larger pow as the re_ path*/
u8 path_pow_ofst_decrease; /* Select the path with lower pow and subtract pow_path_ofst_decrease from path_ref*/
s16 ref_pow_ofdm; /*-> HW: s(9,2)*/
s16 ref_pow_cck; /*-> HW: s(9,2)*/
u16 ref_pow_ofdm_cw; /*BBCR 0x58E0[9:0]*/
u16 ref_pow_cck_cw; /*BBCR 0x58E0[21:12]*/
/*[Pwr Ofsset]*/ /*-> HW: s(7,1)*/
s8 pwr_ofst_mode[TPU_SIZE_MODE_BE]; /*0~7: CCK, Legacy, HT, VHT, HE, EHT, DLRU_HE, DLRU_EHT*/
s8 pwr_ofst_bw[TPU_SIZE_BW_BE]; /*0~9: 20, 40, 80, 160, 320, dlru_20, dlru_40, dlru_80, dlru_160, dlru_320*/
s8 ofst_int; /*SW: S(8,3) -16 ~ +15.875 (dB)*/
u8 ofst_fraction; /*[0:3] * 0.125(dBm)*/
u8 base_cw_0db; /*[63~39~15]: [+24~0~-24 dBm]*/
u16 tssi_16dBm_cw;
/*[Pwr Cusoft]*/
s16 pwr_cusofst_bylim; /*-> HW: s(9,2)*/
s16 pwr_cusofst_bylimbf; /*-> HW: s(9,2)*/
s16 pwr_cusofst_byrate; /*-> HW: s(9,2)*/
s16 pwr_cusofst_byrulim; /*-> HW: s(9,2)*/
u8 pwr_cusofst_sw; /*-> HW: u(4,0)*/
/*[Pwr Limit Enable]*/
bool pwr_lmt_en;
#ifdef HALBB_TX_RFSI_CTRL_SUPPORT
struct bb_cfr_ofst_info_be rtw_cfr_ofst_be_i; /*-> HW: u(6,1)*/
struct bb_cfr_pwr_th_info_be rtw_cfr_pwr_th_be_i; /*-> HW: s(9,2)*/
u8 cfr_lmt_th; /*-> HW: u(3,0)*/
#endif
/*[Misc]*/
enum rtw_tpu_op_mode op_mode; /*In debug mode, only debug tool control TPU APIs*/
bool normal_mode_lock_en;
u16 pwr_lmt_ru_mem_size;
bool ext_pwr_lmt_en;
struct rtw_ext_pwr_lmt_info ext_pwr_lmt_i;
u8 tx_ptrn_shap_idx;
u8 tx_ptrn_shap_idx_cck;
u16 pwr_constraint_mb;
};
#endif
/*==========================================================================*/
union bb_tpu_all_info {
struct rtw_tpu_info bb_tpu_i;
struct bb_tpu_be_info bb_tpu_be_i;
};
#endif
3rd/devourer/hal/halbb/g6/vendor/halbb_cfg_ic.h
Vendored
+77
View File
@@ -0,0 +1,77 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_CFG_IC_H__
#define __HALBB_CFG_IC_H__
#include "halbb_ic_sw_info.h"
#ifdef CONFIG_RTL8852A
//#define BB_8852A_CAV_SUPPORT /*CAV*/
#define BB_8852A_2_SUPPORT /*> CBV*/
#endif
#if defined(CONFIG_RTL8852B) || defined(CONFIG_RTL8852BP) || defined(CONFIG_RTL8852BT) || defined(CONFIG_RTL8852BPT)
#define BB_8852B_SUPPORT
#endif
#if defined(CONFIG_RTL8852C) || defined(CONFIG_RTL8852D) || defined(CONFIG_RTL8842A)
#define BB_8852C_SUPPORT
#ifdef CONFIG_RTL8852D
#define BB_8852D_SUPPORT
#endif
#ifdef CONFIG_RTL8842A
#define BB_8842A_SUPPORT
#endif
#endif
#if defined(CONFIG_RTL8192XB) || defined(CONFIG_RTL8832BR)
#define BB_8192XB_SUPPORT
#endif
#ifdef CONFIG_RTL8851B
#define BB_8851B_SUPPORT
#define HALBB_DUAL_SAR_LMT_TB_8851B
#endif
#if (HLABB_CODE_BASE_NUM == 32) //will be removed when (022+032) branch phase out
#ifdef CONFIG_RTL8922A
#define BB_1115_SUPPORT
#define BB_1115_DVLP_SPF
#define BB_1115_DVLP_SPF_2
#define BB_8922_DVLP_SPF
#define BB_8922_DVLP_SPF_2
#endif
#else
#ifdef CONFIG_RTL8922A
//#define BB_8922A_SUPPORT
#endif
#define BB_8922A_DVLP_SPF_2
#endif
#endif
3rd/devourer/hal/halbb/g6/vendor/halbb_cfo_trk.c
Vendored
+1516
View File
File diff suppressed because it is too large Load Diff
3rd/devourer/hal/halbb/g6/vendor/halbb_cfo_trk.h
Vendored
+209
View File
@@ -0,0 +1,209 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_CFO_TRK_H__
#define __HALBB_CFO_TRK_H__
/*@--------------------------[Define] ---------------------------------------*/
#define CFO_TRK_TH_SIZE 4
#define CFO_TRK_TH_4 30 /* @kHz disable CFO_Track threshold*/
#define CFO_TRK_TH_3 20 /* @kHz disable CFO_Track threshold*/
#define CFO_TRK_TH_2 10 /* @kHz disable CFO_Track threshold*/
#define CFO_TRK_TH_1 3 /* @kHz disable CFO_Track threshold*/
#define CFO_STEP_1 1 /* @kHz disable CFO_Track threshold*/
#define CFO_STEP_2 1 /* @kHz disable CFO_Track threshold*/
#define CFO_STEP_3 3 /* @kHz disable CFO_Track threshold*/
#define CFO_STEP_4 3 /* @kHz disable CFO_Track threshold*/
#define CFO_TRK_ENABLE_TH 3 /* @kHz enable CFO_Track threshold*/
#define CFO_TRK_STOP_TH 3 /* @kHz disable CFO_Track threshold*/
#define NO_PKT_RETURN_TH 10
#define CFO_VALID_BOUNDARY 64
#define CFO_SW_COMP_FINE_TUNE 5 /* @kHz expected CFO Comp. per Xcap ofst*/ /*0.8ppm~1ppm per Xcap ofst*/
#define DIGI_CFO_COMP_LIMIT 5 /* @kHz enable digital CFO comp threshold*/
#define DIGI_CFO_COMP_LIMIT 5 /* @kHz enable digital CFO comp threshold*/
#define CFO_RECORD_NUM 6
#define CFO_LIMIT_PERIOD 60 /*60 sec*/
#define SC_XO 1 /* xcap setting output value */
#define SC_XI 0 /* xcap setting input value */
#define STA_CFO_TOLERANCE_2G 30 /* kHz */
#define STA_CFO_TOLERANCE_5G 80 /* kHz */
#define CFO_HW_RPT_2_KHZ(val) (((val) << 1) + ((val) >> 1))
#define CFO_PERIOD_CNT 15
#define CFO_TP_UPPER 100 /*MHz*/
#define CFO_TP_LOWER 50 /*MHz*/
#define CFO_COMP_PERIOD 250 /*ms*/
#define CFO_TF_CNT_TH 300
/*@--------------------------[Enum]------------------------------------------*/
enum bb_cfo_trk_src_t {
CFO_SRC_FD = 0,
CFO_SRC_PREAMBLE = 1
};
enum bb_cfo_trk_st_t {
CFO_STATE_0 = 0,
CFO_STATE_1 = 1,
CFO_STATE_2 =2
};
enum bb_cfo_trk_acc_mode_t {
CFO_ACC_MODE_0 = 0, /*disable ul_ofdma cfo acc after 30s acc*/
CFO_ACC_MODE_1 = 1, /*enable ul_ofdma cfo acc after 30s acc*/
};
enum multi_sta_cfo_mode_t {
PKT_BASED_AVG_MODE = 0,
ENTRY_BASED_AVG_MODE = 1,
TP_BASED_AVG_MODE = 2,
};
#ifdef BB_DYN_CFO_TRK_LOP
enum bb_dctl_state_t {
DCTL_SNR = 0,
DCTL_LINK = 1,
DCTL_NUM
};
#endif
/*@--------------------------[Structure]-------------------------------------*/
#ifdef BB_DYN_CFO_TRK_LOP
struct bb_cfo_trk_lop_cr_info {
u8 dctl_data; /*data tracking loop filter bandwidth selection for 3rd step*/
u8 dctl_pilot; /*pilot tracking loop filter bandwidth selection for 3rd step*/
};
struct bb_dyn_cfo_trk_lop_info {
bool dyn_cfo_trk_loop_en;
enum bb_dctl_state_t dyn_cfo_trk_loop_state;
u16 dctl_snr_th_l;
u16 dctl_snr_th_h;
u8 dctl_hold_cnt;
struct bb_cfo_trk_lop_cr_info bb_cfo_trk_lop_cr_i[DCTL_NUM];
};
#endif
struct bb_cfo_trk_cr_info {
u32 r_cfo_comp_seg0_312p5khz;
u32 r_cfo_comp_seg0_312p5khz_m;
u32 r_cfo_comp_seg0_312p5khz_1;
u32 r_cfo_comp_seg0_312p5khz_1_m;
u32 r_cfo_comp_seg0_312p5khz_2;
u32 r_cfo_comp_seg0_312p5khz_2_m;
u32 r_cfo_comp_seg0_312p5khz_3;
u32 r_cfo_comp_seg0_312p5khz_3_m;
u32 r_cfo_comp_seg0_vld;
u32 r_cfo_comp_seg0_vld_m;
u32 r_cfo_wgting;
u32 r_cfo_wgting_m;
};
struct bb_cfo_rc_info {
u8 step_history[CFO_RECORD_NUM];
u8 step_bitmap;
bool damping_lock_en;
bool force_damping_step;
u32 limit_time;
};
struct bb_cfo_diver_info {
bool divergence_lock_en;
u32 limit_time;
};
struct bb_cfo_trk_info {
#ifdef HALBB_CFO_DAMPING_CHK
struct bb_cfo_rc_info bb_cfo_rc_i;
#endif
struct bb_cfo_diver_info bb_cfo_div_i;
bool cfo_trig_by_timer_en;
bool is_adjust; /*@already modify crystal cap*/
u8 cfo_th[CFO_TRK_TH_SIZE]; /*u(8,2)*/
u8 step[CFO_TRK_TH_SIZE];
u8 cfo_th_en;
u8 cfo_th_stop; /*u(8,2)*/
s8 x_cap_ofst;
u8 crystal_cap;
u8 def_x_cap;
u8 x_cap_ub;
u8 x_cap_lb;
s32 cfo_avg_pre; /*S(12,2), -512~+511.75 kHz*/
u32 cfo_pkt_cnt;
u8 no_pkt_cnt;
u32 rvrt_val; /*all rvrt_val for pause API must set to u32*/
u8 tb_tx_comp_cfo_th; /*u(8,2)*/
u8 sw_comp_fine_tune; /*u(8,2)*/
u8 bb_cfo_trk_cnt;
u8 sta_cfo_tolerance;
u8 shift4dcfo;
s32 cfo_avg_4dcfo;
s32 cfo_avg_4dcfo_pre;
bool man_cfo_tol;
bool cfo_dyn_acc_en;
bool cfo_trk_by_data_en;
u8 cfo_period_cnt;
u32 cfo_tf_cnt_th;
u32 cfo_tf_cnt_pre;
s32 dcfo_comp_offset; /* For manually fine tune digital cfo*/
enum bb_cfo_trk_src_t cfo_src;
enum bb_cfo_trk_st_t bb_cfo_trk_state;
enum bb_cfo_trk_acc_mode_t bb_cfo_trk_acc_mode;
enum multi_sta_cfo_mode_t multi_sta_cfo_mode;
#ifdef BB_DYN_CFO_TRK_LOP
struct bb_dyn_cfo_trk_lop_info bb_dyn_cfo_trk_lop_i;
#endif
struct halbb_timer_info cfo_timer_i;
};
struct bb_info;
/*@--------------------------[Prptotype]-------------------------------------*/
#ifdef BB_DYN_CFO_TRK_LOP
void halbb_dyn_cfo_trk_loop_en(struct bb_info *bb, bool en);
void halbb_cfo_trk_loop_cr_cfg(struct bb_info *bb, enum bb_dctl_state_t state);
void halbb_dyn_cfo_trk_loop(struct bb_info *bb);
void halbb_dyn_cfo_trk_loop_init(struct bb_info *bb);
#endif
void halbb_cfo_trk_init(struct bb_info *bb);
void halbb_set_crystal_cap(struct bb_info *bb, u8 crystal_cap);
void halbb_set_cfo_pause_val(struct bb_info *bb, u32 *val_buf, u8 val_len);
void halbb_cfo_acc_io_en(struct bb_info *bb);
void halbb_cfo_acc_timer_init(struct bb_info *bb);
void halbb_cfo_dm(struct bb_info *bb);
void halbb_cfo_watchdog(struct bb_info *bb);
void halbb_parsing_cfo(struct bb_info *bb, u32 physts_bitmap,
struct physts_rxd *desc);
void halbb_cfo_trk_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len);
void halbb_cr_cfg_cfo_trk_init(struct bb_info *bb);
void halbb_cfo_ul_ofdma_acc_enable(struct bb_info *bb);
void halbb_cfo_ul_ofdma_acc_disable(struct bb_info *bb);
void halbb_cfo_diver_init(struct bb_info *bb);
#endif
3rd/devourer/hal/halbb/g6/vendor/halbb_ch_info.c
Vendored
+1663
View File
File diff suppressed because it is too large Load Diff
3rd/devourer/hal/halbb/g6/vendor/halbb_ch_info.h
Vendored
+121
View File
@@ -0,0 +1,121 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_CH_INFO_H__
#define __HALBB_CH_INFO_H__
#ifdef HALBB_CH_INFO_SUPPORT
/*@--------------------------[Define] ---------------------------------------*/
#define TEST_CH_INFO_MAX_SEG 4
#define TEST_CH_SEG_LEN (12 * 8) /*Byte*/
/*@--------------------------[Enum]------------------------------------------*/
enum bb_ch_info_state_type {
CH_RPT_START_TO_WAIT = 0,
CH_RPT_GETTED = 1,
CH_RPT_ALWAYS_ON = 2
};
enum bb_ch_info_ack_rxsc_t{
RXSC_FULLBW = 0,
RXSC_20 = 1,
RXSC_DUPILCATE_40 = 9,
RXSC_DUPILCATE_80 = 13
};
/*@--------------------------[Structure]-------------------------------------*/
struct bb_ch_info_physts_info {
enum bb_ch_info_state_type ch_info_state;
bool get_ch_rpt_success;
u32 force_bitmap_type; /*force setting*/
u32 bitmap_type_rpt; /*report*/
bool valid_ch_info_only_en;
bool filter_rxsc_en;
u8 filter_rxsc_tgrt_idx;
bool watchdog_mode;
u16 show_ch_info_max_cnt;
u16 show_ch_info_cnt;
bool bitmap_type_auto_en;
u8 rxsc;
u8 n_rx;
u8 n_sts;
u16 ch_info_len;
u8 evm_1_sts;
u8 evm_2_sts;
u8 avg_idle_noise_pwr;
bool is_ch_info_len_valid;
enum rtw_gi_ltf gi_ltf;
u16 data_rate;
enum bb_ch_info_event_type ch_info_event;
};
struct bb_ch_info_raw_info {
s16 *octet;
u32 ch_info_buf_len; /*Byte*/
};
struct bb_ch_info_cr_info {
u32 ch_info_en_0;
u32 ele_bitmap;
u32 ch_info_type;
u32 ch_info_type_m;
u32 seg_len;
u32 seg_len_m;
u32 ch_info_off_powersaving;
};
struct bb_ch_rpt_info {
u8 seg_idx_pre;
u32 csi_raw_data_total_len; /*Raw data length(Unit: byte) = total_len - 16*/
u32 total_len_remnant;
u16 ch_rpt_hdr_len;
u16 phy_info_len;
bool skip_ch_info; /*wait for seg_0*/
u32 raw_data_len_acc;
u8 *test_buf;
u8 *test_buf_curr;
bool print_en;
enum bb_ch_info_en_t ch_info_data_mode;
struct bb_ch_info_cr_cfg_info bb_ch_info_cr_cfg_i;
struct bb_ch_info_cr_cfg_info bb_ch_info_cur_cr_cfg_i;
struct bb_ch_rpt_size_info bb_ch_rpt_size_i;
struct bb_ch_info_raw_info bb_ch_info_raw_i; /*save dumped ch-info data*/
struct bb_ch_info_physts_info bb_ch_info_physts_i;
struct bb_ch_info_snr_bin_info bb_ch_info_snr_bin_i;
};
struct bb_info;
/*@--------------------------[Prptotype]-------------------------------------*/
bool halbb_ch_info_valid_chk_8852a(struct bb_info *bb, struct physts_rxd *desc);
void halbb_ch_info_buf_rls(struct bb_info *bb);
bool halbb_ch_info_buf_alloc(struct bb_info *bb);
void halbb_ch_info_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len);
void halbb_ch_info_deinit(struct bb_info *bb);
void halbb_ch_info_init(struct bb_info *bb);
void halbb_cr_cfg_ch_info_init(struct bb_info *bb);
void halbb_ch_info_modify_ack_rxsc(struct bb_info *bb, struct physts_rxd *desc, u32 csi_raw_data_total_len, u8 *rxsc);
void halbb_ch_info_watchdog(struct bb_info *bb);
void halbb_ch_info_print(struct bb_info *bb);
#endif
#endif
3rd/devourer/hal/halbb/g6/vendor/halbb_ch_info_ex.h
Vendored
+174
View File
@@ -0,0 +1,174 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_CH_INFO_EX_H__
#define __HALBB_CH_INFO_EX_H__
/*@--------------------------[Define] ---------------------------------------*/
#define CH_DESI_OPT_NUM 4 /*CH info decimation number 1/2/4/16 */
#define CH_INFO_BW_NUM 4 /*20/40/80/160*/
#define CH_INFO_RXD_LEN 8 /*len of a ch_info */
#define CH_INFO_SNR_BIN_NUM 9 /*SNR BIN number*/
/*@--------------------------[Enum]------------------------------------------*/
enum bb_ch_info_en_t {
CH_INFO_DISABLE = 0,
CH_INFO_FROM_PHY_STS = BIT0, /*Report CH info form phy-status*/
CH_INFO_FROM_CH_STS = BIT1 /*Report CH info form CH_info-status*/
};
enum bb_ch_info_t {
BB_CH_INFO_SUCCESS = 0, /*Get ch_info segment success*/
BB_CH_INFO_LAST_SEG, /*Get ch_info segment success, and which is the last segment*/
BB_CH_INFO_FAIL, /*Get ch_info segment fail*/
};
enum bb_ch_mode_t {
BB_CH_LEGACY_CH = 0,
BB_CH_MIMO_CH = 1
};
/*@--------------------------[Structure]-------------------------------------*/
struct bb_ch_rpt_size_info {
u8 data_byte; /* 1&2 Byte, 1Byte:S(8,4), 2Byte:S(16,12)*/
u8 n_c; /*column of channel matrix, RX path number*/
u8 n_r; /*row of channel matrix, TX path number*/
u16 ch_info_rpt_len[CH_INFO_BW_NUM]; /*20,40,80; Unit: Byte; ch_info rpt length calculated by current tone decimatin configuration*/
u16 ch_info_rpt_len_he[CH_INFO_BW_NUM]; /*HE 20,40,80; Byte; ch_info rpt length calculated by current tone decimatin configuration*/
u16 ch_info_tone_num_lgcy[CH_INFO_BW_NUM]; /*20,40,80;*/
u16 ch_info_tone_num[CH_INFO_BW_NUM]; /*20,40,80; Byte; current tone decimatin configuration*/
u16 ch_info_tone_num_he[CH_INFO_BW_NUM]; /*HE 20,40,80; Byte; current tone decimatin configuration*/
u16 per_tone_ch_rpt_size; /*Per tone ch_info size*/
u16 tone_num_lgcy[CH_INFO_BW_NUM][CH_DESI_OPT_NUM];
u16 tone_num[CH_INFO_BW_NUM][CH_DESI_OPT_NUM]; /*look up table for tone number under different tone decimatin CR configuration*/
u16 tone_num_he[CH_INFO_BW_NUM][CH_DESI_OPT_NUM];/*look up table for HE tone number under different tone decimatin CR configuration*/
bool valid_size_physts_lgcy[CH_INFO_BW_NUM]; /*<1024 Byte*/
bool valid_size_physts_ht[CH_INFO_BW_NUM]; /*<1024 Byte*/
bool valid_size_physts_vht[CH_INFO_BW_NUM]; /*<1024 Byte*/
bool valid_size_physts_he[CH_INFO_BW_NUM]; /*<1024 Byte*/
};
struct bb_ch_info_cr_cfg_info {
bool ch_i_data_src; /*0~1: CH-estimation, CH-smoothing*/
bool ch_i_cmprs; /*0~1: 8/16 bit, 0:S(8,4), 1:S(16,12)*/
u8 ch_i_grp_num; /*[Lgcy/HT/VHT] 0~3: decimation to 1/1, 1/2, 1/4, 1/16*/
u8 ch_i_grp_num_he; /*[HE]0~3: decimation to 1/1, 1/2, 1/4, 1/16*/
u8 ch_i_blk_start_idx; /*1~10*/
u8 ch_i_blk_end_idx; /*1~10*/
u32 ch_i_ele_bitmap; /*Channel matrix size, ex: 0x303:2X2, 0x1: 1X1, legacy CSI only support 0x101 or 0x1, 1T1R IC only support 0x1*/
enum bb_ch_mode_t ch_i_type; /*0~1: Legacy-CH, MIMO-CH*/
u8 ch_i_seg_len; /*0~3: 12/28/60/124 (8byte)*/
};
struct bb_ch_info_buf_cfg_info {
u8 ch_i_blk_start_idx; /*1~10*/
u8 ch_i_blk_end_idx; /*1~10*/
u8 ch_i_seg_len; /*0~3: 12/28/60/124 (8byte)*/
};
struct bb_ch_rpt_hdr_info {
u16 total_len_l; /*header(16byte) + Raw data length(Unit: byte)*/
#if (PLATFOM_IS_LITTLE_ENDIAN)
u8 total_len_m:1;
u8 total_seg_num:7;
#else
u8 total_seg_num:7;
u8 total_len_m:1;
#endif
u8 avg_noise_pow; /*U(8,1)*/
#if (PLATFOM_IS_LITTLE_ENDIAN)
u8 is_pkt_end:1;
u8 set_valid:1;
u8 n_rx:3;
u8 n_sts:3;
#else
u8 n_sts:3;
u8 n_rx:3;
u8 set_valid:1;
u8 is_pkt_end:1;
#endif
u8 segment_size; /*unit (8Byte)*/
u8 sts0_evm;
u8 seq_num;
};
struct bb_phy_info_rpt {
u8 rssi[2];
u16 rsvd_0;
u8 rssi_avg;
#if (PLATFOM_IS_LITTLE_ENDIAN)
u8 rxsc:4;
u8 sts1_evm_l:4;
u8 sts1_evm_m:4; /*(sts1_evm_m << 4 | sts1_evm_l): U(8,2)*/
u8 rsvd_1:4;
#else
u8 rsvd_1:4;
u8 sts1_evm_m:4;
u8 sts1_evm_l:4;
u8 rxsc:4;
#endif
u8 rsvd_2;
};
struct bb_ch_info_drv_rpt {
u32 raw_data_len;
u8 seg_idx_curr;
bool get_ch_rpt_success;
};
struct bb_ch_info_snr_bin_info{
u8 ch_info_snr[4][CH_INFO_SNR_BIN_NUM];
};
enum bb_ch_info_event_type {
CH_RPT_TRIG_ONCE = 0,
CH_RPT_TRIG_ALWAYS= 1
};
struct bb_info;
/*@--------------------------[Prptotype]-------------------------------------*/
bool halbb_ch_info_wait_from_physts(struct bb_info *bb, u32 dly, u32 dly_max,
u32 bitmap, bool valid_rpt_only);
void halbb_ch_info_cfg_mu_buff_cr(struct bb_info *bb, bool en);
bool halbb_cfg_ch_info_cr(struct bb_info *bb, struct bb_ch_info_cr_cfg_info *cfg);
void halbb_ch_info_size_query(struct bb_info *bb, struct bb_ch_rpt_size_info *exp_rpt_size, enum phl_phy_idx phy_idx);
void halbb_ch_info_physts_en(struct bb_info *bb, bool en,
u32 bitmap, enum phl_phy_idx phy_idx);
void halbb_ch_info_status_en(struct bb_info *bb, bool en, enum phl_phy_idx phy_idx);
void halbb_ch_trig_select(struct bb_info *bb, u8 event);
void halbb_ch_info_close_powersaving(struct bb_info *bb, bool en, enum phl_phy_idx phy_idx);
bool halbb_ch_info_calc_pertone_snr(struct bb_info *bb, u8 snrvalue, u16 *addr, u32 len);
u8 halbb_ch_info_ack_verify(struct bb_info *bb, u16 *addr, u8 datasize, u16 len);
u32 halbb_ch_info_ic_cfg(struct bb_info *bb, enum bb_ch_mode_t ch_i_type);
enum bb_ch_info_t halbb_ch_info_parsing(struct bb_info *bb, u8 *addr, u32 len,
struct physts_rxd *desc,
u8 *rpt_buf,
struct bb_ch_rpt_hdr_info *hdr,
struct bb_phy_info_rpt *phy_info,
struct bb_ch_info_drv_rpt *drv);
#endif
3rd/devourer/hal/halbb/g6/vendor/halbb_cmn_rpt.h
Vendored
+144
View File
@@ -0,0 +1,144 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_CMN_RPT_H__
#define __HALBB_CMN_RPT_H__
/*@--------------------------[Define] ---------------------------------------*/
#define RSSI_MA_H 4 /*moving average factor for RSSI: 2^4=16 */
#define RSSI_MA_M 3
#define RSSI_MA_L 2
#define RSSI_MA_UL 1
#define BB_HIST_SIZE 12
#define BB_HIST_TH_SIZE (BB_HIST_SIZE - 1)
#define POP_HIST_SIZE 4
/*@--------------------------[Enum]------------------------------------------*/
/*@--------------------------[Structure]-------------------------------------*/
struct bb_rssi_mu_acc_info { /*all in U(8,1)*/
/*acc value*/
u32 rssi_t_avg_acc;
u32 rssi_t_acc[HALBB_MAX_PATH]; /*VHT, HE*/
};
struct bb_pkt_cnt_bcn_info {
u8 pkt_cnt_beacon;
u8 beacon_cnt_in_period; /*@beacon cnt within watchdog period*/
u16 beacon_phy_rate;
};
struct bb_rssi_su_acc_info { /*all in U(8,1)*/
/*acc value*/
u32 rssi_cck_avg_acc;
u32 rssi_cck_acc[HALBB_MAX_PATH];
u32 rssi_ofdm_avg_acc;
u32 rssi_ofdm_acc[HALBB_MAX_PATH]; /*L-OFDM*/
u32 rssi_t_avg_acc;
u32 rssi_t_acc[HALBB_MAX_PATH]; /*HT, VHT, HE*/
};
struct bb_pkt_cnt_cap_info {
u32 pkt_cnt_ldpc; /*pkt_cnt_ofdm = pkt_cnt_ldpc + pkt_cnt_bcc*/
u32 pkt_cnt_bcc;
u32 pkt_cnt_stbc;
u32 pkt_cnt_subf;
u32 pkt_cnt_su_non_bf;
u32 pkt_cnt_mu;
};
struct bb_physts_hist_info {
u16 evm_1ss[BB_HIST_SIZE];
u16 evm_min_hist[BB_HIST_SIZE];
u16 evm_max_hist[BB_HIST_SIZE];
u16 snr_avg_hist[BB_HIST_SIZE];
u16 cn_avg_hist[BB_HIST_SIZE];
u16 cfo_avg_hist[BB_HIST_SIZE]; /*ABS(cfo) 0~256 Khz*/
};
struct bb_physts_hist_th_info {
u8 evm_hist_th[BB_HIST_TH_SIZE]; /*threshold*/
u8 cn_hist_th[BB_HIST_TH_SIZE]; /*threshold*/
u8 cfo_hist_th[BB_HIST_TH_SIZE]; /*threshold*/
};
struct bb_physts_acc_info {
u32 evm_1ss; /*U(8,2)*/ /*only for 1SS & L-OFDM*/
u32 evm_min_acc; /*U(8,2)*/ /*only for >= 2SS*/
u32 evm_max_acc; /*U(8,2)*/ /*only for >= 2SS*/
u32 snr_avg_acc; /*U(6,0)*/
u32 snr_per_path_acc[HALBB_MAX_PATH]; /*U(6,0)*/
u32 cn_avg_acc; /*U(7,1)*/
s32 cfo_avg_acc; /*U(8,2)*/
u16 pkt_cnt_cn_valid;
};
struct bb_physts_pop_info {
u16 pop_hist_cck[POP_HIST_SIZE]; /*U(8,0) pop_idx histogram*/
u16 pop_hist_ofdm[POP_HIST_SIZE]; /*U(8,0) pop_idx histogram*/
};
struct bb_cmn_rpt_info {
bool is_cck_rate;
u8 consec_idle_prd_su; /*consecutive idle period*/
u8 consec_idle_prd_mu;
struct bb_rate_info bb_rate_i;
struct bb_pkt_cnt_bcn_info bb_pkt_cnt_bcn_i; /*beacon info*/
struct bb_pkt_cnt_cap_info bb_pkt_cnt_all_i; /*capibility info*/
struct bb_pkt_cnt_su_info bb_pkt_cnt_su_i; /*Packet count*/
struct bb_rssi_su_acc_info bb_rssi_su_acc_i; /*acc RSSI*/
struct bb_rssi_su_avg_info bb_rssi_su_avg_i; /*avg RSSI*/
struct bb_physts_hist_th_info bb_physts_hist_th_i;
struct bb_physts_hist_info bb_physts_hist_i; /*phy-sts histogram*/
struct bb_physts_acc_info bb_physts_acc_i; /*acc phy-sts*/
struct bb_physts_avg_info bb_physts_avg_i; /*avg phy-sts*/
struct bb_physts_pop_info bb_physts_pop_i; /*pop info*/
/*[MU]*/
struct bb_pkt_cnt_mu_info bb_pkt_cnt_mu_i; /*Packet count*/
struct bb_rssi_mu_acc_info bb_rssi_mu_acc_i; /*acc RSSI*/
struct bb_rssi_mu_avg_info bb_rssi_mu_avg_i; /*avg RSSI*/
struct bb_pkt_cnt_su_store_info bb_pkt_cnt_su_store_i;
};
struct bb_info;
/*@--------------------------[Prptotype]-------------------------------------*/
void halbb_print_hist_2_buf_u8(struct bb_info *bb, u8 *val, u16 len, char *buf,
u16 buf_size);
void halbb_print_hist_2_buf(struct bb_info *bb, u16 *val, u16 len, char *buf,
u16 buf_size);
u16 halbb_get_plurality_rx_rate_mu(struct bb_info *bb);
u16 halbb_get_plurality_rx_rate_su(struct bb_info *bb);
void halbb_basic_dbg_07_hist_su(struct bb_info *bb);
void halbb_show_rssi_and_rate_distribution_mu(struct bb_info *bb);
void halbb_show_rssi_and_rate_distribution_su(struct bb_info *bb);
void halbb_cmn_rpt_get_avg_val(struct bb_info *bb);
void halbb_rx_pkt_cnt_rpt_reset(struct bb_info *bb);
void halbb_cmn_rpt_watchdog(struct bb_info *bb);
void halbb_cmn_rpt(struct bb_info *bb, struct physts_rxd *desc, u32 physts_bitmap);
void halbb_cmn_info_rpt_store_data(struct bb_info *bb);
void halbb_cmn_info_rpt_reset(struct bb_info *bb);
void halbb_cmn_rpt_init(struct bb_info *bb);
#endif
3rd/devourer/hal/halbb/g6/vendor/halbb_cmn_rpt_ex.h
Vendored
+125
View File
@@ -0,0 +1,125 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_CMN_RPT_EX_H__
#define __HALBB_CMN_RPT_EX_H__
/*@--------------------------[Define] ---------------------------------------*/
/*@--------------------------[Enum]------------------------------------------*/
/*@--------------------------[Structure]-------------------------------------*/
struct bb_rssi_mu_avg_info { /*all in U(8,1)*/
u8 rssi_t_avg;
u8 rssi_t[HALBB_MAX_PATH]; /*VHT, HE*/
};
struct bb_rssi_su_avg_info { /*all in U(8,1)*/
u8 rssi_cck_avg;
u8 rssi_cck[HALBB_MAX_PATH];
u8 rssi_ofdm_avg;
u8 rssi_ofdm[HALBB_MAX_PATH]; /*L-OFDM*/
u8 rssi_t_avg;
u8 rssi_t[HALBB_MAX_PATH]; /*HT, VHT, HE*/
};
struct bb_physts_avg_info {
u8 evm_1ss; /*U(8,2) 0~63*/
u8 evm_min; /*U(8,2) 0~63*/
u8 evm_max; /*U(8,2) 0~63*/
u8 snr_avg; /*U(6,0) 0~63*/
u8 snr_per_path_avg[HALBB_MAX_PATH]; /*U(6,0)*/
u8 cn_avg; /*U(7,1) 0~63*/
s16 cfo_avg; /*U(16,2) 0~512*/
};
struct bb_pkt_cnt_mu_info {
/*====[Phy rate counter]=============================================*/
u16 pkt_cnt_all; /*VHT, HE = pkt_cnt_1ss + pkt_cnt_2ss*/
u16 gi_ltf_cnt[RTW_GILTF_MAX];
u16 pkt_cnt_1ss; /*VHT, HE*/
u16 pkt_cnt_2ss; /*VHT, HE*/
u16 pkt_cnt_sc20[LOW_BW_RATE_NUM]; /*@20M SC*/
bool sc20_occur;
/*VHT*/
u16 pkt_cnt_vht[VHT_RATE_NUM];
u16 pkt_cnt_sc40[LOW_BW_RATE_NUM]; /*@40M SC*/
bool vht_pkt_not_zero;
bool sc40_occur;
u16 pkt_cnt_sc80[LOW_BW_RATE_NUM];
bool sc80_occur;
/*HE*/
u16 pkt_cnt_he[HE_RATE_NUM];
bool he_pkt_not_zero;
/*EHT*/
u16 pkt_cnt_eht[EHT_RATE_NUM];
bool eht_pkt_not_zero;
};
struct bb_pkt_cnt_su_store_info {
bool ht_pkt_not_zero;
bool vht_pkt_not_zero;
bool he_pkt_not_zero;
};
struct bb_pkt_cnt_su_info {
/*====[Phy rate counter]=============================================*/
u16 pkt_cnt_all; /*CCK + OFDM + HT, VHT, HE*/
u16 gi_ltf_cnt[RTW_GILTF_MAX];
u16 pkt_cnt_cck;
u16 pkt_cnt_ofdm; /*L-OFDM*/
u16 pkt_cnt_t; /*HT, VHT, HE = pkt_cnt_1ss + pkt_cnt_2ss*/
u16 pkt_cnt_1ss; /*HT, VHT, HE*/
u16 pkt_cnt_2ss; /*HT, VHT, HE*/
/*Legacy*/
u16 pkt_cnt_legacy[LEGACY_RATE_NUM];
/*HT*/
u16 pkt_cnt_ht[HT_RATE_NUM];
u16 pkt_cnt_sc20[LOW_BW_RATE_NUM]; /*@20M SC*/
bool ht_pkt_not_zero;
bool sc20_occur;
/*VHT*/
u16 pkt_cnt_vht[VHT_RATE_NUM];
u16 pkt_cnt_sc40[LOW_BW_RATE_NUM]; /*@40M SC*/
bool vht_pkt_not_zero;
bool sc40_occur;
/*HE*/
u16 pkt_cnt_he[HE_RATE_NUM];
u16 pkt_cnt_sc80[LOW_BW_RATE_NUM]; /*@80M SC*/
bool he_pkt_not_zero;
bool sc80_occur;
/*EHT*/
u16 pkt_cnt_eht[EHT_RATE_NUM];
bool eht_pkt_not_zero;
/*non_data packet*/
u16 pkt_cnt_legacy_non_data[LEGACY_RATE_NUM];
u16 pkt_cnt_else_non_data;
};
struct bb_info;
/*@--------------------------[Prptotype]-------------------------------------*/
void halbb_get_rx_pkt_cnt_rpt_su(struct bb_info *bb, struct bb_pkt_cnt_su_info *pkt_cnt_rpt, enum phl_phy_idx phy_idx);
void halbb_cmn_rpt_export_physts_avg_rpt(struct bb_info * bb, struct bb_physts_avg_info *info);
#endif
3rd/devourer/hal/halbb/g6/vendor/halbb_dbcc.h
Vendored
+55
View File
@@ -0,0 +1,55 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_DBCC_H__
#define __HALBB_DBCC_H__
#ifdef HALBB_DBCC_SUPPORT
/*@--------------------------[Define] ---------------------------------------*/
#define HALBB_GET_PHY_PTR(bb, bb_out, phy_idx)\
do { \
if ((bb->bb_phy_hooker) && (phy_idx != bb->bb_phy_idx) && (bb->phl_com->dev_cap.dbcc_sup)) \
bb_out = bb->bb_phy_hooker; \
else \
bb_out = bb; \
} while (0)
/*@--------------------------[Enum]------------------------------------------*/
/*@--------------------------[Structure]-------------------------------------*/
struct bb_dbcc_info {
bool tmp_val;
};
/*@--------------------------[Prptotype]-------------------------------------*/
struct bb_info;
void halbb_cfo_trk_joint_phy_dec(struct bb_info *bb);
enum bb_path halbb_get_cur_phy_valid_path(struct bb_info *bb);
void halbb_dbcc_early_init(struct bb_info *bb);
void halbb_dbcc_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len);
struct bb_info *halbb_get_curr_bb_pointer(struct bb_info *bb,
enum phl_phy_idx phy_idx);
u32 halbb_buffer_init_phy1(struct bb_info *bb_phy_0);
#endif
#endif
3rd/devourer/hal/halbb/g6/vendor/halbb_dbcc_ex.h
Vendored
+44
View File
@@ -0,0 +1,44 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_DBCC_EX_H__
#define __HALBB_DBCC_EX_H__
/*@--------------------------[Define] ---------------------------------------*/
/*@--------------------------[Enum]------------------------------------------*/
/*@--------------------------[Structure]-------------------------------------*/
struct bb_dbcc_cfg_info {
bool dbcc_en;
enum phl_phy_idx cck_phy_map;
};
/*@--------------------------[Prptotype]-------------------------------------*/
struct bb_info;
void halbb_dbcc_band_switch_notify(struct bb_info *bb);
bool halbb_ctrl_dbcc(struct bb_info *bb, bool dbcc_enable);
bool halbb_cfg_dbcc_cck_phy_map(struct bb_info *bb, enum phl_phy_idx cck_phy_map);
bool halbb_cfg_dbcc(struct bb_info *bb, struct bb_dbcc_cfg_info *cfg);
#endif
3rd/devourer/hal/halbb/g6/vendor/halbb_dbg.h
Vendored
+537
View File
@@ -0,0 +1,537 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_DBG_H__
#define __HALBB_DBG_H__
#include "../../hal_headers_le.h"
/*@--------------------------[Define] ---------------------------------------*/
#define HALBB_WATCHDOG_PERIOD 2 /*second*/
#define PHY_HIST_SIZE 12
#define PHY_HIST_TH_SIZE (PHY_HIST_SIZE - 1)
#define LA_CLK_EN 0x014 /*Just for dbg, will be removed*/
#define LA_CLK_EN_M 0x1 /*Just for dbg, will be removed*/
#define FRC_PRINT_LINE 0xffffffff
#define REG_DUMP_HISTORY_NUM 20
#ifdef HALBB_DBG_TRACE_SUPPORT
#ifdef HALBB_DBCC_SUPPORT
#define BB_DBG(bb, comp, fmt, ...) \
do {\
if(bb->dbg_component & comp) {\
_os_dbgdump("[BB][%d]" fmt, bb->bb_phy_idx, ##__VA_ARGS__);\
} \
} while (0)
#define BB_TRACE1(bb, fmt, ...) \
do {\
_os_dbgdump("[BB][%d]" fmt, bb->bb_phy_idx, ##__VA_ARGS__);\
} while (0)
#else
#define BB_DBG(bb, comp, fmt, ...) \
do {\
if(bb->dbg_component & comp) {\
_os_dbgdump("[BB]" fmt, ##__VA_ARGS__);\
} \
} while (0)
#define BB_TRACE1(bb, fmt, ...) \
do {\
_os_dbgdump("[BB]" fmt, ##__VA_ARGS__);\
} while (0)
#endif
#define BB_TRACE(fmt, ...) \
do {\
_os_dbgdump("[BB]" fmt, ##__VA_ARGS__);\
} while (0)
#define BB_WARNING(fmt, ...) \
do {\
_os_dbgdump("[WARNING][BB]" fmt, ##__VA_ARGS__);\
} while (0)
#define BB_DBG_CNSL2(in_cnsl, max_buff_len, used_len, buff_addr, remain_len, fmt, ...)\
do { \
u32 *used_len_tmp = &(used_len); \
u32 len_tmp = 0; \
if (*used_len_tmp < max_buff_len) { \
len_tmp = _os_snprintf(buff_addr, remain_len, fmt, ##__VA_ARGS__); \
if (in_cnsl) { \
*used_len_tmp += len_tmp; \
} else { \
BB_TRACE("%s\n", buff_addr); \
} \
}\
} while (0)
#else
#define BB_DBG
#define BB_TRACE
#define BB_TRACE1
#define BB_WARNING
#define BB_DBG_CNSL2(in_cnsl, max_buff_len, used_len, buff_addr, remain_len, fmt, ...)\
do { \
u32 *used_len_tmp = &(used_len); \
if (*used_len_tmp < max_buff_len) \
*used_len_tmp += _os_snprintf(buff_addr, remain_len, fmt, ##__VA_ARGS__);\
} while (0)
#endif
#define BB_DBG_VAST(max_buff_len, used_len, buff_addr, remain_len, fmt, ...)\
do {\
_os_dbgdump("[CNSL]" fmt, ##__VA_ARGS__);\
} while (0)
#define BB_DBG_CNSL(max_buff_len, used_len, buff_addr, remain_len, fmt, ...)\
do { \
u32 *used_len_tmp = &(used_len); \
if (*used_len_tmp < max_buff_len) \
*used_len_tmp += _os_snprintf(buff_addr, remain_len, fmt, ##__VA_ARGS__);\
} while (0)
#define DBGPORT_PRI_3 3 /*@Debug function (the highest priority)*/
#define DBGPORT_PRI_2 2 /*@Check hang function & Strong function*/
#define DBGPORT_PRI_1 1 /*Watch dog function*/
#define DBGPORT_RELEASE 0 /*@Init value (the lowest priority)*/
/*@--------------------------[Enum]------------------------------------------*/
enum bb_dbg_devider_len_t
{
BB_DEVIDER_LEN_32 = 0,
BB_DEVIDER_LEN_16 = 1,
};
enum bb_dbg_port_ip_t
{
DBGPORT_IP_TD = 1,
DBGPORT_IP_RX_INNER = 2,
DBGPORT_IP_TX_INNER = 3,
DBGPORT_IP_OUTER = 4,
DBGPORT_IP_INTF = 5,
DBGPORT_IP_CCK = 6,
DBGPORT_IP_BF = 7,
DBGPORT_IP_RX_OUTER = 8,
DBGPORT_IP_RFC0 = 0X1B,
DBGPORT_IP_RFC1 = 0X1C,
DBGPORT_IP_RFC2 = 0X1D,
DBGPORT_IP_RFC3 = 0X1E,
DBGPORT_IP_TST = 0X1F,
};
enum bb_frc_phy_dump_reg
{
FRC_DUMP_PHY0 = 0,
FRC_DUMP_PHY1 = 1,
FRC_DUMP_ALL
};
enum bb_basic_dbg_info
{
BB_BASIC_DBG_01_SYSTEM = BIT1,
BB_BASIC_DBG_02_ENVMNTR = BIT2,
BB_BASIC_DBG_03_PMAC = BIT3,
BB_BASIC_DBG_04_TX = BIT4,
BB_BASIC_DBG_05_RX = BIT5,
BB_BASIC_DBG_06_RSSI_RATE = BIT6,
BB_BASIC_DBG_07_HIST = BIT7,
BB_BASIC_DBG_08_RSSI_RATE_MU = BIT8,
BB_BASIC_DBG_09_DM_SUMMARY = BIT9
};
enum FWBB_DBG_COMP {
/*=============RA=============*/
FWBBDBG_BF = BIT0,
FWBBDBG_RA_STASTISTIC = BIT1, /*RA main debug log: rty ratio*/
FWBBDBG_RA_SEARCH_RATE = BIT2, /*BW switch/search rate/choose rate*/
FWBBDBG_RA_RATE_STATE_DECISION = BIT3, /*RU/RD/RS decision*/
FWBBDBG_RA_TRY_RESULT = BIT4, /*Try state & write cmac table*/
FWBBDBG_RA_TX_RPT_TRY = BIT5, // tx_rpt in try state
FWBBDBG_RA_TX_RPT_NONTRY = BIT6, // tx_rpt in non-try state and tx_cnt=1
FWBBDBG_RA_TX_RPT_NONTRY_ARFR = BIT7, // tx_rpt in non-try state and tx_cnt>1(re-transmit)
FWBBDBG_RA_RECEIVED_H2C = BIT8 // RA received H2C
/*============================*/
};
enum FWBB_DBG_NUM_BF {
BBDBG_NUM_BF_CHECK_BF_EXIST_0_0 = 0,
BBDBG_NUM_BF_CHECK_BF_EXIST_0_1 = 1,
BBDBG_NUM_BF_CHECK_BF_EXIST_0_2 = 2,
BBDBG_NUM_BF_CHECK_BF_EXIST_0_3 = 3,
BBDBG_NUM_BF_CHECK_BF_EXIST_0_4 = 4,
BBDBG_NUM_BF_CHECK_BF_EXIST_0_5 = 5,
BBDBG_NUM_BF_CHECK_BF_EXIST_0_6 = 6,
BBDBG_NUM_BF_CHECK_BF_EXIST_0_7 = 7,
BBDBG_NUM_BF_CHECK_BF_EXIST_0_8 = 8,
BBDBG_NUM_BF_CHECK_BF_EXIST_0_9 = 9,
};
enum FWBB_DBG_NUM_STASTISTIC {
BBDBG_NUM_RA_RATE_CHANGED_1_0 = 0,
BBDBG_NUM_RA_CAL_PARA_1_1 = 1,
BBDBG_NUM_RA_CAL_PARA_1_2 = 2
};
enum FWBB_DBG_NUM_SEARCH_RATE {
BBDBG_NUM_RA_SEARCH_RATE_RU_2_0 = 0,
BBDBG_NUM_RA_SEARCH_RATE_RU_2_1 = 1,
BBDBG_NUM_RA_SEARCH_RATE_RD_2_2 = 2,
BBDBG_NUM_RA_SEARCH_RATE_RD_2_3 = 3,
BBDBG_NUM_RA_RATE_LOCK_2_4 = 4,
BBDBG_NUM_RA_RATE_LOCK_2_5 = 5,
BBDBG_NUM_RA_RATE_LOCK_2_6 = 6
};
enum FWBB_DBG_NUM_RATE_STATE {
BBDBG_NUM_RA_D_O_PARA_3_0 = 0,
BBDBG_NUM_RA_UP_DOWN_TH_3_1 = 1,
BBDBG_NUM_RA_RATE_DOWN_3_2 = 2,
BBDBG_NUM_RA_RATE_FORCE_DOWN_3_3 = 3,
BBDBG_NUM_RA_RATE_UP_3_4 = 4,
BBDBG_NUM_RA_RATE_STAY_3_5 = 5
};
enum FWBB_DBG_NUM_TRY_RESULT {
BBDBG_NUM_RA_WRITE_CMAC_4_0 = 0,
BBDBG_NUM_RA_TRY_RESULT_4_1 = 1,
BBDBG_NUM_RA_TRY_RESULT_4_2 = 2,
BBDBG_NUM_RA_TRY_RESULT_4_3 = 3,
BBDBG_NUM_RA_TRY_RESULT_4_4 = 4,
BBDBG_NUM_RA_TRY_FAIL_4_5 = 5,
BBDBG_NUM_RA_TRY_SUCCESS_4_6 = 6
};
enum FWBB_DBG_NUM_TX_RPT_TRY {
BBDBG_NUM_RA_TX_RPT_TRY_5_0 = 0,
BBDBG_NUM_RA_TX_RPT_TRY_5_1 = 1,
BBDBG_NUM_RA_TX_RPT_TRY_5_2 = 2
};
enum FWBB_DBG_NUM_TX_RPT_NONTRY {
BBDBG_NUM_RA_TX_RPT_NONTRY_6_0 = 0, // unused
BBDBG_NUM_RA_TX_RPT_NONTRY_6_1 = 1,
BBDBG_NUM_RA_TX_RPT_NONTRY_6_2 = 2
};
enum FWBB_DBG_NUM_TX_RPT_NONTRY_ARFR {
BBDBG_NUM_RA_TX_RPT_NONTRY_ARFR_7_0 = 0, // unused
BBDBG_NUM_RA_TX_RPT_NONTRY_ARFR_7_1 = 1,
BBDBG_NUM_RA_TX_RPT_NONTRY_ARFR_7_2 = 2
};
enum FWBB_DBG_NUM_RA_RECEIVED_H2C {
BBDBG_NUM_RA_RECEIVED_H2C_8_0 = 0,
BBDBG_NUM_RA_RECEIVED_H2C_8_1 = 1,
BBDBG_NUM_RA_RECEIVED_H2C_8_2 = 2,
BBDBG_NUM_RA_RECEIVED_H2C_8_3 = 3,
BBDBG_NUM_RA_RECEIVED_H2C_8_4 = 4,
BBDBG_NUM_RA_RECEIVED_H2C_8_5 = 5,
BBDBG_NUM_RA_RECEIVED_H2C_8_6 = 6,
BBDBG_NUM_RA_RECEIVED_H2C_8_7 = 7,
BBDBG_NUM_RA_RECEIVED_H2C_8_8 = 8,
BBDBG_NUM_RA_RECEIVED_H2C_8_9 = 9,
BBDBG_NUM_RA_RECEIVED_H2C_8_10 = 10, //0xa
BBDBG_NUM_RA_RECEIVED_H2C_8_11 = 11, //0xb
BBDBG_NUM_RA_RECEIVED_H2C_8_13 = 13, //0xd
BBDBG_NUM_RA_RECEIVED_H2C_8_14 = 14, //0xe
BBDBG_NUM_RA_RECEIVED_H2C_8_15 = 15, //0xf
BBDBG_NUM_RA_RECEIVED_H2C_8_16 = 16, //0x10
BBDBG_NUM_RA_RECEIVED_H2C_8_32 = 32, //0x20
BBDBG_NUM_RA_RECEIVED_H2C_8_33 = 33 //0x21
};
enum bb_dbg_bbcr_cnt_t {
BB_CR_CNT_DISABLE = 0,
BB_CR_CNT_ENABLE_ACCUMULATE = 1,
BB_CR_CNT_ENABLE_RESET = 2,
};
/*@--------------------------[Structure]-------------------------------------*/
struct bb_dbg_cr_info {
u32 dbgport_ip;
u32 dbgport_ip_m;
u32 dbgport_idx;
u32 dbgport_idx_m;
u32 dbgport_val;
u32 dbgport_val_m;
u32 clk_en;
u32 clk_en_m;
u32 dbgport_en;
u32 dbgport_en_m;
u32 bb_monitor_sel0;
u32 bb_monitor_sel0_m;
u32 bb_monitor0;
u32 bb_monitor0_m;
u32 bb_monitor_sel1;
u32 bb_monitor_sel1_m;
u32 bb_monitor1;
u32 bb_monitor1_m;
u32 mac_phy_intf_sel_phy1;
u32 mac_phy_intf_sel_phy1_m;
u32 mac_phy_txinfo[6];
u32 mac_phy_txt2rct[2];
u32 mac_phy_txcomct[2];
u32 mac_phy_txusrct[4][2];
u32 mac_phy_txtimct;
u32 mac_phy_lsig;
u32 mac_phy_siga_0;
u32 mac_phy_siga_1;
u32 mac_phy_vht_sigb_0;
u32 mac_phy_usig_1;
u32 mac_phy_usig_2;
u32 path_0_txpw;
u32 path_0_txpw_m;
u32 path_1_txpw;
u32 path_1_txpw_m;
u32 bmode_tx;
/*AGC cr*/
u32 agc_en_path[HALBB_MAX_PATH];
u32 agc_en_path_m[HALBB_MAX_PATH];
u32 lna_idx_init_path[HALBB_MAX_PATH];
u32 lna_idx_init_path_m[HALBB_MAX_PATH];
u32 tia_idx_init_path[HALBB_MAX_PATH];
u32 tia_idx_init_path_m[HALBB_MAX_PATH];
u32 rxbb_idx_init_path[HALBB_MAX_PATH];
u32 rxbb_idx_init_path_m[HALBB_MAX_PATH];
u32 tia_shrink_en_path[HALBB_MAX_PATH];
u32 tia_shrink_en_path_m[HALBB_MAX_PATH];
u32 tia_shrink_init_path[HALBB_MAX_PATH];
u32 tia_shrink_init_path_m[HALBB_MAX_PATH];
u32 elna_idx_pre_agc_rdy_path[HALBB_MAX_PATH];
u32 elna_idx_pre_agc_rdy_path_m[HALBB_MAX_PATH];
u32 lna_idx_pre_agc_rdy_path[HALBB_MAX_PATH];
u32 lna_idx_pre_agc_rdy_path_m[HALBB_MAX_PATH];
u32 tia_idx_pre_agc_rdy_path[HALBB_MAX_PATH];
u32 tia_idx_pre_agc_rdy_path_m[HALBB_MAX_PATH];
u32 tia_shrink_pre_agc_rdy_path[HALBB_MAX_PATH];
u32 tia_shrink_pre_agc_rdy_path_m[HALBB_MAX_PATH];
u32 rxbb_idx_pre_agc_rdy_path[HALBB_MAX_PATH];
u32 rxbb_idx_pre_agc_rdy_path_m[HALBB_MAX_PATH];
u32 elna_idx_post_agc_rdy_path[HALBB_MAX_PATH];
u32 elna_idx_post_agc_rdy_path_m[HALBB_MAX_PATH];
u32 lna_idx_post_agc_rdy_path[HALBB_MAX_PATH];
u32 lna_idx_post_agc_rdy_path_m[HALBB_MAX_PATH];
u32 tia_idx_post_agc_rdy_path[HALBB_MAX_PATH];
u32 tia_idx_post_agc_rdy_path_m[HALBB_MAX_PATH];
u32 tia_shrink_post_agc_rdy_path[HALBB_MAX_PATH];
u32 tia_shrink_post_agc_rdy_path_m[HALBB_MAX_PATH];
u32 rxbb_idx_post_agc_rdy_path[HALBB_MAX_PATH];
u32 rxbb_idx_post_agc_rdy_path_m[HALBB_MAX_PATH];
u32 elna_idx_nlgc_agc_rdy_path[HALBB_MAX_PATH];
u32 elna_idx_nlgc_agc_rdy_path_m[HALBB_MAX_PATH];
u32 lna_idx_nlgc_agc_rdy_path[HALBB_MAX_PATH];
u32 lna_idx_nlgc_agc_rdy_path_m[HALBB_MAX_PATH];
u32 tia_idx_nlgc_agc_rdy_path[HALBB_MAX_PATH];
u32 tia_idx_nlgc_agc_rdy_path_m[HALBB_MAX_PATH];
u32 tia_shrink_nlgc_agc_rdy_path[HALBB_MAX_PATH];
u32 tia_shrink_nlgc_agc_rdy_path_m[HALBB_MAX_PATH];
u32 rxbb_idx_nlgc_agc_rdy_path[HALBB_MAX_PATH];
u32 rxbb_idx_nlgc_agc_rdy_path_m[HALBB_MAX_PATH];
u32 p_diff_pre_agc_rdy_path[HALBB_MAX_PATH];
u32 p_diff_pre_agc_rdy_path_m[HALBB_MAX_PATH];
u32 p_diff_pd_hit_path[HALBB_MAX_PATH];
u32 p_diff_pd_hit_path_m[HALBB_MAX_PATH];
u32 p_diff_post_agc_rdy_path[HALBB_MAX_PATH];
u32 p_diff_post_agc_rdy_path_m[HALBB_MAX_PATH];
u32 p_diff_nlgc_agc_rdy_path[HALBB_MAX_PATH];
u32 p_diff_nlgc_agc_rdy_path_m[HALBB_MAX_PATH];
u32 rssi_agc_rdy_path[HALBB_MAX_PATH];
u32 rssi_agc_rdy_path_m[HALBB_MAX_PATH];
u32 rssi_always_run_path[HALBB_MAX_PATH];
u32 rssi_always_run_path_m[HALBB_MAX_PATH];
};
struct bb_tx_info {
/*From reg*/
u8 type;
u8 ppdu_var;
u8 tx_path_en;
u8 path_map;
u8 txcmd_num;
u8 txsc;
u8 bw;
u16 tx_pw; /*tmac*/
u8 n_usr;
u8 max_mcs;
bool stbc;
u8 gi;
u8 ltf;
u8 u_id[4];
u8 n_sts[4];
bool fec[4];
u8 mcs[4];
bool dcm[4];
u8 precoding[4];
u16 n_sym;
u8 pkt_ext;
u8 pre_fec;
u32 l_sig;
u32 sig_a1;
u32 sig_a2;
u32 sig_b;
u32 usig_1;
u32 usig_2;
u32 txinfo[6];
u32 txt2rct[2];
u32 txcomct[2];
u32 txusrct[4][2];
u32 txtimct;
u16 txpw_path0; /*bb_path0*/
u16 txpw_path1; /*bb_path1*/
u32 bmode;
u8 bmode_rate;
u16 bmode_length; /*1 = 1M, 2 = 2M, 4 = 5.5M, 8 = 11M*/
u8 bmode_service;
bool bmode_type; /*0 = TX long preamble, 1 = TX short preamble*/
/*sw variable*/
u16 t_data;
u32 psdu_length;
};
struct bb_ra_dbgreg {
u32 macid;
u32 cmac_tbl_id0;
u32 cmac_tbl_id1;
u32 per;
u32 rdr;
u32 r4;
u32 cls;
u32 rate_up_lmt_cnt;
u32 per_ma;
u32 var;
u32 d_o_n;
u32 d_o_p;
u32 rd_th;
u32 ru_th;
u32 try_per;
u32 try_rdr;
u32 try_r4;
u32 txrpt_tot;
u32 ra_timer;
u32 tot_disra_trying_return;
u32 r4_return;
u32 ra_mask_h;
u32 ra_mask_l;
u32 highest_rate;
u32 lowest_rate;
u32 upd_all_h2c_0;
u32 upd_all_h2c_1;
u32 upd_all_h2c_2;
u32 upd_all_h2c_3;
u32 dyn_stbc;
u32 mu_mcs;
u32 mu_id_lowest_rate;
u32 mu_rd_ru_th;
u32 mu_per;
bool is_rate_up;
};
struct bb_dbg_info {
enum bb_dbg_bbcr_cnt_t cr_cnt_ctrl;
u32 cr_recorde_w_cnt;
u32 cr_recorde_r_cnt;
u32 wrapcr_recorde_w_cnt;
enum bb_dbg_bbcr_cnt_t rfcr_cnt_ctrl;
u32 rfcr_recorde_w_cnt;
u32 rfcr_recorde_r_cnt;
bool cr_recorder_en;
bool cr_mp_recorder_en;
bool cr_init_hook_recorder_en;
bool cr_fake_init_hook_en;
u32 cr_fake_init_hook_val;
bool cr_recorder_rf_en; /*HALRF write BB CR*/
/*CR init debug control*/
bool cr_dbg_mode_en;
u32 cut_curr_dbg;
u32 rfe_type_curr_dbg;
#ifdef HALBB_TDMA_CR_SUPPORT
struct halbb_timer_info tdma_cr_timer_i;
bool tdma_cr_en;
u8 tdma_cr_state;
u32 tdma_cr_idx;
u32 tdma_cr_mask;
u32 tdma_cr_val_0;
u32 tdma_cr_val_1;
u32 tdma_cr_period_0;
u32 tdma_cr_period_1;
#endif
struct bb_tx_info tx_info_i;
struct bb_ra_dbgreg ra_dbgreg_i;
};
/*@--------------------------[Prptotype]-------------------------------------*/
struct bb_info;
void halbb_print_devider(struct bb_info *bb, u8 len, bool with_space, u64 comp);
#ifdef HALBB_TDMA_CR_SUPPORT
void halbb_tdma_cr_sel_io_en(struct bb_info *bb);
void halbb_tdma_cr_timer_init(struct bb_info *bb);
void halbb_tdma_cr_sel_main(struct bb_info *bb);
void halbb_tdma_cr_sel_init(struct bb_info *bb);
#endif
void halbb_dbg_comp_init(struct bb_info *bb);
void halbb_bb_dbg_port_clock_en(struct bb_info *bb, u8 enable);
u32 halbb_get_bb_dbg_port_idx(struct bb_info *bb);
void halbb_set_bb_dbg_port(struct bb_info *bb, u32 dbg_port);
void halbb_set_bb_dbg_port_ip(struct bb_info *bb, enum bb_dbg_port_ip_t ip);
void halbb_release_bb_dbg_port(struct bb_info *bb);
bool halbb_bb_dbg_port_racing(struct bb_info *bb, u8 curr_dbg_priority);
u32 halbb_get_bb_dbg_port_val(struct bb_info *bb);
u16 halbb_trx_utility(struct bb_info *bb, enum bb_mode_type mode,
u16 avg_phy_rate, u8 rx_max_ss, enum channel_width bw);
u16 halbb_rx_avg_phy_rate(struct bb_info *bb);
u16 halbb_tx_avg_phy_rate(struct bb_info *bb);
void halbb_get_tx_dbg_reg(struct bb_info *bb);
void halbb_basic_dbg_message(struct bb_info *bb);
void halbb_basic_profile_dbg(struct bb_info *bb, u32 *_used, char *output, u32 *_out_len);
void halbb_get_bb_para_pkg_ver(struct bb_info *bb, u32 *date, u32 *release_ver);
void halbb_dump_reg_dbg(struct bb_info *bb, char input[][16], u32 *_used, char *output, u32 *_out_len);
void halbb_dd_dump_dbg(struct bb_info *bb, char input[][16], u32 *_used, char *output, u32 *_out_len);
void halbb_cr_table_dump(struct bb_info *bb, u32 *cr_table, u32 cr_len);
void halbb_cr_hook_fake_init(struct bb_info *bb, u32 *str_table, u32 len);
void halbb_cr_struc_dump(struct bb_info *bb, u32 *str_table, u32 len);
void halbb_cr_hook_init_dump(struct bb_info *bb, u32 *str_table, u32 len);
void halbb_dump_bb_reg(struct bb_info *bb, u32 *_used, char *output,
u32 *_out_len, bool dump_2_buff,
enum bb_frc_phy_dump_reg frc_phy_dump);
void halbb_dump_hioe_reg(struct bb_info *bb, u32 *_used, char *output,
u32 *_out_len, bool dump_2_buff,
enum phl_phy_idx phy_idx);
void halbb_tx_info_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len);
void halbb_cmn_dbg(struct bb_info *bb, char input[][16], u32 *_used, char *output, u32 *_out_len);
void halbb_dbg_setting_init(struct bb_info *bb);
void halbb_agc_dbg(struct bb_info *bb, char input[][16], u32 *_used, char *output, u32 *_out_len);
void halbb_cr_cfg_dbg_init(struct bb_info *bb);
void halbb_mac_phy_intf_txcmd_txtp(struct bb_info *bb, u8 txcmd_num, char **txcmd);
void halbb_mac_phy_intf_txcmd_txtp_7(struct bb_info *bb, u8 txcmd_num, char **txcmd);
void halbb_mac_phy_intf_ppdu_type(struct bb_info *bb, u8 type, char **ppdu);
void halbb_mac_phy_intf_ppdu_var_type_7(struct bb_info *bb, u8 ppdu_type, u8 ppdu_var, char **ppdu);
u32 halbb_c2h_fw_dbg(struct bb_info *bb, u16 len, u8 *c2h);
#endif
3rd/devourer/hal/halbb/g6/vendor/halbb_dbg_cmd.h
Vendored
+84
View File
@@ -0,0 +1,84 @@
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HALBB_DBG_CMD_H_
#define _HALBB_DBG_CMD_H_
/*@--------------------------[Define] ---------------------------------------*/
#define MAX_ARGC 20
#define MAX_ARGV 16
#if 1
#define HALBB_SCAN _os_sscanf
#define DCMD_DECIMAL "%d"
#define DCMD_HEX "%x"
#define DCMD_HEX64 "%llx"
#define DCMD_CHAR "%s"
#else
#define HALBB_SCAN halbb_scanf
enum bb_scanf_type
{
DCMD_DECIMAL = 1,
DCMD_HEX = 2,
DCMD_CHAR = 3,
};
#endif
#define DCMD_SCAN_LIMIT 10
/*@--------------------------[Enum]------------------------------------------*/
enum bb_scanf_type
{
DCMD2_DECIMAL = 1,
DCMD2_HEX = 2,
DCMD2_CHAR = 3,
};
enum FWBB_DBG_COMP_SET {
FWBBDBG_H2C = BIT0,
FWBBDBG_RA = BIT8,
FWBBDBG_RUA = BIT16,
FWBBDBG_ULPWR_CTRL = BIT24,
FWBBDBG_ULRA = BIT25,
};
/*@--------------------------[Structure]-------------------------------------*/
struct bb_echo_cmd_info {
u8 cmd_size;
enum phl_phy_idx echo_phy_idx;
};
struct bb_fw_dbg_cmn_info {
u8 fw_dbg_comp[4];
u8 fw_dbg_trace;
u8 fw_cmn_info;
u8 fw_rty_rpt_ctrl;
u8 rsvd0;
};
/*@--------------------------[Prptotype]-------------------------------------*/
struct bb_info;
void halbb_dbgport_dump_all(struct bb_info *bb, u32 *_used, char *output,
u32 *_out_len);
void halbb_dbgport_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len);
void halbb_scanf(char *in, enum bb_scanf_type type, u32 *out);
void halbb_cmd_parser_init(struct bb_info *bb);
void halbb_fw_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len);
void halbb_lps_ch_info_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len);
#endif
3rd/devourer/hal/halbb/g6/vendor/halbb_dbg_cmd_ex.h
Vendored
+39
View File
@@ -0,0 +1,39 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_DBG_CMD_EX_H__
#define __HALBB_DBG_CMD_EX_H__
#define MAX_ARGV 16
struct bb_info;
s32 halbb_cmd(struct bb_info *bb, char *input, char *output, u32 out_len);
void halbb_cmd_parser(struct bb_info *bb, char input[][MAX_ARGV],
u32 input_num, char *output, u32 out_len);
#endif
3rd/devourer/hal/halbb/g6/vendor/halbb_dbg_cmd_table.h
Vendored
+174
View File
@@ -0,0 +1,174 @@
/******************************************************************************
*
* Copyright(c) 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _HALBB_DBG_CMD_TABLE_H_
#define _HALBB_DBG_CMD_TABLE_H_
/*@--------------------------[Define] ---------------------------------------*/
/*@--------------------------[Enum]------------------------------------------*/
enum HALBB_CMD_ID {
HALBB_HELP,
HALBB_DEMO,
HALBB_REG_RW,
HALBB_CMN_DBG,
HALBB_RA,
HALBB_PROFILE,
HALBB_TRACE,
HALBB_MP_DBG,
HALBB_SUPPORT_ABILITY,
HALBB_TX_PW,
HALBB_IC_API,
HALBB_SPUR_SUPP,
HALBB_LA_MODE,
HALBB_DUMP_REG,
HALBB_AUTO_DBG,
HALBB_DD_DBG,
HALBB_SHOW_RXRATE,
HALBB_NBI_EN,
HALBB_CSI_MASK_EN,
HALBB_DFS_DBG,
HALBB_DIG,
HALBB_NHM,
HALBB_CLM,
HALBB_IFS_CLM,
HALBB_FAHM,
HALBB_EDCCA_CLM,
HALBB_EDCCA,
HALBB_ENV_MNTR,
HALBB_BB_INFO,
HALBB_H2C,
HALBB_STASISTICS,
HALBB_PSD,
HALBB_DBG_PORT,
HALBB_CFO_TRK,
HALBB_UL_TB,
HALBB_ADAPTIVITY_DBG,
HALBB_STA_INFO,
HALBB_PAUSE_FUNC,
HALBB_PER_TONE_EVM,
HALBB_DYN_TXPWR,
HALBB_PHY_STATUS,
HALBB_RX_DESC,
HALBB_DCC,
HALBB_PMAC_TX,
HALBB_FW_DBG,
HALBB_CH_INFO,
HALBB_RUA_TBL,
HALBB_TD_CFG,
HALBB_FD_CFG,
HALBB_DBCC,
HALBB_ANT_DIV,
HALBB_DCR_DBG,
HALBB_HW_CFG,
HALBB_RX_GAIN_TABLE,
HALBB_RX_OP1DB_TABLE,
HALBB_HW_SETTING,
HALBB_PATH_DIV,
HALBB_DTP,
HALBB_TX_INFO,
HALBB_DYN_1R_CCA,
HALBB_CMN_INFO,
HALBB_SNIFFER_MODE,
HALBB_DTR_DBG,
HALBB_FW_OFLD,
HALBB_MATH,
HALBB_LPS_CH_INFO,
HALBB_SPATIAL_REUSE,
HALBB_DV_DBG,
HALBB_DV_PXP_DBG,
HALBB_PLCP_DBG,
HALBB_AGC
};
/*@--------------------------[Structure]-------------------------------------*/
struct halbb_cmd_info {
char name[16];
u8 id;
};
static const struct halbb_cmd_info halbb_cmd_i[] = {
{"-h", HALBB_HELP}, /*@do not move this element to other position*/
{"demo", HALBB_DEMO}, /*@do not move this element to other position*/
{"cr", HALBB_REG_RW},
{"cmn", HALBB_CMN_DBG},
{"ra", HALBB_RA},
{"profile", HALBB_PROFILE},
{"dbg", HALBB_TRACE},
{"mp_dbg", HALBB_MP_DBG},
{"ability", HALBB_SUPPORT_ABILITY},
{"tx_pw", HALBB_TX_PW},
{"ic_api", HALBB_IC_API},
{"spur", HALBB_SPUR_SUPP},
{"lamode", HALBB_LA_MODE},
{"psd", HALBB_PSD},
{"dumpreg", HALBB_DUMP_REG},
{"auto_dbg", HALBB_AUTO_DBG},
{"dd_dbg", HALBB_DD_DBG},
{"cfo_trk", HALBB_CFO_TRK},
{"ul_tb", HALBB_UL_TB},
{"rxrate", HALBB_SHOW_RXRATE},
//{"nbi", HALBB_NBI_EN},
//{"csi_mask", HALBB_CSI_MASK_EN},
{"dfs", HALBB_DFS_DBG},
{"dig", HALBB_DIG},
{"nhm", HALBB_NHM},
{"clm", HALBB_CLM},
{"ifs_clm", HALBB_IFS_CLM},
{"fahm", HALBB_FAHM},
{"edcca_clm", HALBB_EDCCA_CLM},
{"edcca", HALBB_EDCCA},
{"env_mntr", HALBB_ENV_MNTR},
//{"bbinfo", HALBB_BB_INFO},
//{"h2c", HALBB_H2C},
{"stat", HALBB_STASISTICS},
{"dbgport", HALBB_DBG_PORT},
{"sta_info", HALBB_STA_INFO},
{"pause", HALBB_PAUSE_FUNC},
{"physts", HALBB_PHY_STATUS},
{"rxd", HALBB_RX_DESC},
{"pmac_tx", HALBB_PMAC_TX},
{"fw_dbg", HALBB_FW_DBG},
{"ch_info", HALBB_CH_INFO},
{"td", HALBB_TD_CFG},
{"fd", HALBB_FD_CFG},
{"dbcc", HALBB_DBCC},
{"rua", HALBB_RUA_TBL},
{"ant_div", HALBB_ANT_DIV},
{"dcr", HALBB_DCR_DBG},
{"hw_cfg", HALBB_HW_CFG},
{"gain_table", HALBB_RX_GAIN_TABLE},
{"dtr", HALBB_DTR_DBG},
{"op1db_table", HALBB_RX_OP1DB_TABLE},
{"hw_set", HALBB_HW_SETTING},
{"path_div", HALBB_PATH_DIV},
{"dtp", HALBB_DTP},
{"txinfo", HALBB_TX_INFO},
{"dyn_1r_cca", HALBB_DYN_1R_CCA},
{"cmn_info", HALBB_CMN_INFO},
{"snif", HALBB_SNIFFER_MODE},
{"fw_ofld", HALBB_FW_OFLD},
{"math", HALBB_MATH},
{"lps_ch_info", HALBB_LPS_CH_INFO},
{"sr", HALBB_SPATIAL_REUSE},
{"dv_dbg", HALBB_DV_DBG},
{"dv_pxp_dbg", HALBB_DV_PXP_DBG},
{"plcp_tx", HALBB_PLCP_DBG},
{"agc", HALBB_AGC}
};
/*@--------------------------[Prptotype]-------------------------------------*/
#endif
3rd/devourer/hal/halbb/g6/vendor/halbb_dbg_cnsl_out.h
Vendored
+43
View File
@@ -0,0 +1,43 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_DBG_CNSL_OUT_H__
#define __HALBB_DBG_CNSL_OUT_H__
#include "../../hal_headers_le.h"
/*@--------------------------[Define] ---------------------------------------*/
/*@--------------------------[Prptotype]-------------------------------------*/
struct bb_info;
void halbb_ra_dbgreg_cnsl(struct bb_info *bb, u32 *_used, char *output,
u32 *_out_len);
void halbb_basic_dbg_msg_tx_dbg_reg_cnsl(struct bb_info *bb, u32 *_used,
char *output, u32 *_out_len);
void halbb_basic_dbg_message_cnsl_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len);
void halbb_show_rx_rate(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len);
#endif
3rd/devourer/hal/halbb/g6/vendor/halbb_dbg_cnsl_out_ex.h
Vendored
+75
View File
@@ -0,0 +1,75 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_DBG_CNSL_OUT_EX_H__
#define __HALBB_DBG_CNSL_OUT_EX_H__
/*@--------------------------[Define] ---------------------------------------*/
struct halbb_statistic_exp_t {
u16 tx_rate;
u8 tx_per;
#if 1
struct bb_pkt_cnt_su_info bb_pkt_cnt_exp;
#else
u16 pkt_cnt_cck;
u16 pkt_cnt_ofdm;
u16 pkt_cnt_1ss;
u16 pkt_cnt_2ss;
bool ht_pkt_not_zero;
bool low_bw_20_occur;
bool vht_pkt_not_zero;
bool low_bw_40_occur;
u16 num_qry_legacy_pkt[12];
u16 num_qry_ht_pkt[16];
u16 num_qry_pkt_sc_20m[24];
u16 num_qry_vht_pkt[24];
u16 num_qry_pkt_sc_40m[24];
#endif
#if 1
struct bb_rssi_su_avg_info bb_rssi_su_avg_exp;
#else
u8 rssi_cck_avg[2];
u8 rssi_ofdm_avg[2];
u8 rssi_1ss_avg[2];
u8 rssi_2ss_avg[2];
#endif
//struct bb_rssi_su_acc_info bb_rssi_su_acc_exp;
//struct bb_physts_avg_info avg_info;
u8 evm_1ss; /*1ss rate*/
u8 evm_max; /*2ss rate*/
u8 evm_min; /*2ss rate*/
u8 snr_avg;
s8 edcca_fb_pwdb; /*full bandwidth edcca_pwdb, unit: dBm, value = -128 when Tx*/
};
/*@--------------------------[Prptotype]-------------------------------------*/
struct bb_info;
void halbb_statistic_exp(struct bb_info *bb_0,
struct halbb_statistic_exp_t *exp,
enum phl_phy_idx phy_idx);
void halbb_statistic_reset(struct bb_info *bb);
void halbb_statistic_exp_en(struct bb_info *bb, bool en);
#endif
3rd/devourer/hal/halbb/g6/vendor/halbb_dbg_ex.h
Vendored
+35
View File
@@ -0,0 +1,35 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_DBG_EX_H__
#define __HALBB_DBG_EX_H__
/*@--------------------------[Define] ---------------------------------------*/
/*@--------------------------[Enum]------------------------------------------*/
/*@--------------------------[Structure]-------------------------------------*/
struct bb_info;
/*@--------------------------[Prptotype]-------------------------------------*/
u32 halbb_get_bb_mntr(struct bb_info *bb, u8 mntr_idx, u32 sel);
u32 halbb_get_dbgport_val_by_racing(struct bb_info *bb, u32 dbg_port);
#endif
3rd/devourer/hal/halbb/g6/vendor/halbb_dfs.h
Vendored
+484
View File
@@ -0,0 +1,484 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_DFS_H__
#define __HALBB_DFS_H__
/*@--------------------------[Define] ---------------------------------------*/
#define DFS_RPT_LENGTH 8
#define DFS_RDR_TYP_NUM 8
#define DFS_L_RDR_IDX 6
#define DFS_SPCL_RDR_IDX_ETSI 3
#define PW_FTR_IDLE 1
#define PRI_FTR_IDLE 1
#define PW_FTR 3
#define PRI_FTR 3
#define DFS_PPB_PRCNT 4
#define DFS_PPB_IDLE_PRCNT 5
#define DFS_FCC_LP_LNGTH 12 /*Real Waveform length of FCC-LP is 12 secs*/
#define DFS_MAX_SEQ_NUM 127
#define DFS_ADPTV_CNT1 1
#define DFS_ADPTV_CNT2 1
#define DFS_ADPTV_CNT_TH 30
#define DFS_Normal_State 0
#define DFS_Adaptive_State 1
#ifdef HALBB_DFS_GEN2_SERIES
#define REF_TYPE_PRI 111 /* 1428us / 12.8(unit) */
#define SRRC_RFE_TYPE_PRI 78 /* 1000us / 12.8(unit) */
#define W56_Type1_PRI 108 /* 1388us / 12.8(unit) */
#endif
#ifdef HALBB_DBG_TRACE_SUPPORT
#ifdef HALBB_DBCC_SUPPORT
#define BB_DFS_DBG(bb, case, fmt, ...)\
do {\
if((bb->dbg_component & BB_DFS) && (bb->bb_dfs_i.dbg_print_component & case)) {\
_os_dbgdump("[BB][%d]" fmt, bb->bb_phy_idx, ##__VA_ARGS__);\
}\
} while (0)
#else
#define BB_DFS_DBG(bb, case, fmt, ...)\
do {\
if((bb->dbg_component & BB_DFS) && (bb->bb_dfs_i.dbg_print_component & case)) {\
_os_dbgdump("[BB]" fmt, ##__VA_ARGS__);\
}\
} while (0)
#endif
#else
#define BB_DFS_DBG(bb, case, fmt, ...)
#endif
/*@--------------------------[Enum]------------------------------------------*/
enum dfs_dbg_print_case {
HWDET_PRINT = BIT(1),
SWDET_PRINT = BIT(2),
BRK_PRINT = BIT(3),
DYN_PRINT = BIT(4),
TRIVIL_PRINT = BIT(5)
};
/*@--------------------------[Structure]-------------------------------------*/
struct bb_dfs_cr_info {
u32 dfs_en;
u32 dfs_en_m;
u32 tw_dfs_en;
u32 tw_dfs_en_m;
u32 dfs_en_p1;
u32 dfs_en_p1_m;
u32 dfs_l2h_th;
u32 dfs_l2h_th_m;
};
struct bb_dfs_info {
//============= Used by TW DFS ==============//
bool is_tw_en;
bool bypass_seg0;
//===========================================//
u8 dbg_print_component;
u8 dfs_rgn_domain;
u8 ppb_prcnt;
u16 pw_rpt[DFS_MAX_SEQ_NUM];
u8 pri_rpt[DFS_MAX_SEQ_NUM];
u8 seq_num_rpt[DFS_MAX_SEQ_NUM];
u8 seq_num_rpt_all[DFS_MAX_SEQ_NUM];
bool chrp_rpt[DFS_MAX_SEQ_NUM];
#ifdef HALBB_DFS_GEN2_SERIES
bool dfs_more[DFS_MAX_SEQ_NUM];
bool dfs_phy_def[DFS_MAX_SEQ_NUM];
u8 format[DFS_MAX_SEQ_NUM];
u8 bbid[DFS_MAX_SEQ_NUM];
u16 seq_num[DFS_MAX_SEQ_NUM];
u16 RSVD[DFS_MAX_SEQ_NUM];
u16 sub20_1_pw[DFS_MAX_SEQ_NUM];
u16 sub20_1_pri[DFS_MAX_SEQ_NUM];
bool sub20_1_chirp_flag[DFS_MAX_SEQ_NUM];
bool sub20_1_pres[DFS_MAX_SEQ_NUM];
u16 sub20_0_pw[DFS_MAX_SEQ_NUM];
u16 sub20_0_pri[DFS_MAX_SEQ_NUM];
bool sub20_0_chirp_flag[DFS_MAX_SEQ_NUM];
bool sub20_0_pres[DFS_MAX_SEQ_NUM];
u8 sub20_0_srt_rdr_cnt[DFS_RDR_TYP_NUM];
u8 sub20_1_srt_rdr_cnt[DFS_RDR_TYP_NUM];
u8 sub20_2_srt_rdr_cnt[DFS_RDR_TYP_NUM];
u8 sub20_3_srt_rdr_cnt[DFS_RDR_TYP_NUM];
u8 sub20_4_srt_rdr_cnt[DFS_RDR_TYP_NUM];
u8 sub20_5_srt_rdr_cnt[DFS_RDR_TYP_NUM];
u8 sub20_6_srt_rdr_cnt[DFS_RDR_TYP_NUM];
u8 sub20_7_srt_rdr_cnt[DFS_RDR_TYP_NUM];
u8 sub20_0_lng_rdr_cnt;
u8 sub20_1_lng_rdr_cnt;
u8 sub20_2_lng_rdr_cnt;
u8 sub20_3_lng_rdr_cnt;
u8 sub20_4_lng_rdr_cnt;
u8 sub20_5_lng_rdr_cnt;
u8 sub20_6_lng_rdr_cnt;
u8 sub20_7_lng_rdr_cnt;
u8 adv_pri_cnt[DFS_RDR_TYP_NUM];
bool sub20_detect_en;
#endif
u16 pw_ofst;
u16 pri_ofst;
u16 adv_pri_ofst;
u32 l2h_init_val;
u32 l2h_val; /* for FCC detection BW */
//===========================================//
//===========================================//
//============= Used by TW DFS ==============//
bool seg_rpt[DFS_MAX_SEQ_NUM];
bool seg_rpt_all[DFS_MAX_SEQ_NUM];
//===========================================//
//u8 chrp_cnt;
//u8 chrp_th;
u32 chrp_srt_t;
u8 lng_rdr_cnt;
u8 chrp_rdr_cnt;
u8 lng_rdr_cnt_pre;
//============= Used by TW DFS ==============//
u32 chrp_srt_t_sg1;
u8 n_cnfd_lvl_sg1;
u8 chrp_rdr_cnt_sg1;
u8 lng_rdr_cnt_sg1;
u8 lng_rdr_cnt_sg1_pre;
//===========================================//
u8 srt_rdr_cnt[DFS_RDR_TYP_NUM];
u16 pw_lbd[DFS_RDR_TYP_NUM];
u16 pw_ubd[DFS_RDR_TYP_NUM];
u16 pri_lbd[DFS_RDR_TYP_NUM];
u16 pri_ubd[DFS_RDR_TYP_NUM];
u16 pw_min_tab[DFS_RDR_TYP_NUM];
u16 pw_max_tab[DFS_RDR_TYP_NUM];
u16 pri_min_tab[DFS_RDR_TYP_NUM];
u16 pri_max_tab[DFS_RDR_TYP_NUM];
u8 ppb_tab[DFS_RDR_TYP_NUM];
u8 ppb_tp_tab[DFS_RDR_TYP_NUM];
u8 ppb_typ_th[DFS_RDR_TYP_NUM];
u8 lst_seq_num;
u8 lst_seg_idx;
u8 pw_factor;
u8 pri_factor;
//============= Used by TW DFS ==============//
u8 srt_rdr_cnt_sg1[DFS_RDR_TYP_NUM];
u8 lst_seq_num_sg1;
u8 rpt_sg_history;
u8 rpt_sg_history_all;
//===========================================//
bool is_mic_w53;
bool is_mic_w56;
bool l_rdr_exst_flag;
bool chrp_obsrv_flag;
bool n_seq_flag;
//============= Used by TW DFS ==============//
bool chrp_obsrv_flag_sg1;
bool n_seq_flag_sg1;
//===========================================//
bool idle_flag;
bool first_dyn_set_flag;
bool dyn_reset_flag;
bool dfs_sw_trgr_mode;
bool dfs_sw_trgr_mode_extra;
bool dfs_dbg_mode;
bool mask_fake_rpt_en;
bool dfs_dyn_setting_en;
u16 dfs_fa_th;
u8 fk_dfs_num_th;
u8 dfs_tp_th;
u8 dfs_idle_prd_th;
u8 dfs_rx_rto_th;
u8 dfs_nhm_th;
u8 dfs_rssi_th;
u8 adap_detect_cnt;
u8 adap_detect_cnt_init;
u8 adap_detect_cnt_add;
u8 adap_detect_cnt_all;
u8 adap_detect_cnt_th;
u8 detect_state;
bool adap_detect_brk_en;
u8 pri_mask_th;
u8 rpt_rdr_cnt;
u8 pri_full_cnt;
u8 fake_rdr_cnt_th;
bool In_CAC_Flag;
u16 pw_diff_th;
u16 pw_lng_chrp_diff_th;
u16 pri_diff_th;
u16 pw_max_th;
u16 invalid_lng_pulse_h_th;
u16 invalid_lng_pulse_l_th;
u16 min_pw_shrt[DFS_RDR_TYP_NUM];
u16 min_pw_lng;
u16 min_pw_chrp;
u16 min_pri_shrt[DFS_RDR_TYP_NUM];
u16 max_pw_shrt[DFS_RDR_TYP_NUM];
u16 max_pw_lng;
u16 max_pw_chrp;
u16 max_pri_shrt[DFS_RDR_TYP_NUM];
u16 pw_diff_shrt[DFS_RDR_TYP_NUM];
u16 pri_diff_shrt[DFS_RDR_TYP_NUM];
//============= Used by TW DFS ==============//
u16 min_pw_shrt_sg1[DFS_RDR_TYP_NUM];
u16 min_pw_lng_sg1;
u16 min_pw_chrp_sg1;
u16 min_pri_shrt_sg1[DFS_RDR_TYP_NUM];
u16 max_pw_shrt_sg1[DFS_RDR_TYP_NUM];
u16 max_pw_lng_sg1;
u16 max_pw_chrp_sg1;
u16 max_pri_shrt_sg1[DFS_RDR_TYP_NUM];
u16 pw_diff_shrt_sg1[DFS_RDR_TYP_NUM];
u16 pw_diff_lng_sg1;
u16 pri_diff_shrt_sg1[DFS_RDR_TYP_NUM];
//===========================================//
};
struct bb_dfs_rpt {
u8 *dfs_ptr;
u16 dfs_num;
u8 phy_idx; /*phy0,phy1*/
};
#ifdef HALBB_DFS_GEN2_SERIES
#if (PLATFOM_IS_LITTLE_ENDIAN)
struct bb_rdr_info_gen2 {
u8 dfs_sub20_0_pres : 1; /*whether rpt is valid*/
u8 dfs_sub20_0_chirp_flag : 1;
u8 dfs_sub20_0_pri_l : 6;
u8 dfs_sub20_0_pri_m : 3;
u8 dfs_sub20_0_pw_l : 5;
u8 dfs_sub20_0_pw_m : 4;
u8 dfs_sub20_1_pres : 1;
u8 dfs_sub20_1_chirp_flag : 1;
u8 dfs_sub20_1_pri_l : 2;
u8 dfs_sub20_1_pri_m : 7;
u8 dfs_sub20_1_pw_l : 1;
u8 dfs_sub20_1_pw_m;
u8 RSVD_l;
u8 RSVD_m : 4;
u8 dfs_seq_num_l : 4;
u8 dfs_seq_num_m : 3;
u8 dfs_bbid : 1; /*BB0,BB1*/
u8 dfs_format : 2;
u8 dfs_phy_def : 1; /*phy0,phy1*/
u8 dfs_more : 1;
};
#else
struct bb_rdr_info_gen2 {
u8 dfs_sub20_0_pri_l : 6;
u8 dfs_sub20_0_chirp_flag : 1;
u8 dfs_sub20_0_pres : 1;
u8 dfs_sub20_0_pw_l : 5;
u8 dfs_sub20_0_pri_m : 3;
u8 dfs_sub20_1_pri_l : 2;
u8 dfs_sub20_1_chirp_flag : 1;
u8 dfs_sub20_1_pres : 1;
u8 dfs_sub20_0_pw_m : 4;
u8 dfs_sub20_1_pw_l : 1;
u8 dfs_sub20_1_pri_m : 7;
u8 dfs_sub20_1_pw_m;
u8 RSVD_l;
u8 dfs_seq_num_l : 4;
u8 RSVD_m : 4;
u8 dfs_more : 1;
u8 dfs_phy_def : 1;
u8 dfs_format : 2;
u8 dfs_bbid : 1;
u8 dfs_seq_num_m : 3;
};
#endif
#endif
#ifdef HALBB_TW_DFS_SERIES
#if (PLATFOM_IS_LITTLE_ENDIAN)
struct bb_rdr_info_gen1 {
u8 rdr_info_sg1_chirp_flag : 1; /*[18:9],[8:1],[0]*/
u8 rdr_info_sg1_pri_l : 7;
u8 rdr_info_sg1_pri_m : 1;
u8 rdr_info_sg1_pw_l : 7;
u8 rdr_info_sg1_pw_m : 3;
u8 rdr_info_sg0_chirp_flag : 1; /*[37:28],[27:20],[19]*/
u8 rdr_info_sg0_pri_l : 4;
u8 rdr_info_sg0_pri_m : 4;
u8 rdr_info_sg0_pw_l : 4;
u8 rdr_info_sg0_pw_m : 6;
u8 rdr_info_rsvd_l : 2; /*[48:38]*/
u8 rdr_info_rsvd_m;
u8 rdr_info_rsvd_h : 1;
u8 rdr_info_sg1_seq : 7; /*[55:49]*/
u8 rdr_info_sg0_seq : 7; /*[62:56]*/
u8 rdr_info_path_opt : 1; /*[63]*/
};
#else
struct bb_rdr_info_gen1 {
u8 rdr_info_sg1_pri_l : 7;
u8 rdr_info_sg1_chirp_flag : 1;
u8 rdr_info_sg1_pw_l : 7;
u8 rdr_info_sg1_pri_m : 1;
u8 rdr_info_sg0_pri_l : 4;
u8 rdr_info_sg0_chirp_flag : 1;
u8 rdr_info_sg1_pw_m : 3;
u8 rdr_info_sg0_pw_l : 4;
u8 rdr_info_sg0_pri_m : 4;
u8 rdr_info_rsvd_l : 2;
u8 rdr_info_sg0_pw_m : 6;
u8 rdr_info_rsvd_m;
u8 rdr_info_sg1_seq : 7;
u8 rdr_info_rsvd_h : 1;
u8 rdr_info_path_opt : 1;
u8 rdr_info_sg0_seq : 7;
};
#endif
#endif
#if (PLATFOM_IS_LITTLE_ENDIAN)
struct bb_rdr_info_gen0{
u8 rdr_info_sg0_chirp_flag:1; /*[18:9],[8:1],[0]*/
u8 rdr_info_sg0_pri_l:7;
u8 rdr_info_sg0_pri_m:1;
u8 rdr_info_sg0_pw_l:7;
u8 rdr_info_sg0_pw_m:3;
u8 rdr_info_sg1_chirp_flag:1; /*[37:28],[27:20],[19]*/
u8 rdr_info_sg1_pri_l:4;
u8 rdr_info_sg1_pri_m:4;
u8 rdr_info_sg1_pw_l:4;
u8 rdr_info_sg1_pw_m:6;
u8 rdr_info_zw_chirp_flag:1; /*[56:47],[46:39],[38]*/
u8 rdr_info_zw_pri_l:1;
u8 rdr_info_zw_pri_m:7;
u8 rdr_info_zw_pw_l:1;
u8 rdr_info_zw_pw_m;
u8 rdr_info_zw_pw_h:1;
u8 rdr_info_seq:7;
};
#else
struct bb_rdr_info_gen0 {
u8 rdr_info_sg0_pri_l:7;
u8 rdr_info_sg0_chirp_flag:1;
u8 rdr_info_sg0_pw_l:7;
u8 rdr_info_sg0_pri_m:1;
u8 rdr_info_sg1_pri_l:4;
u8 rdr_info_sg1_chirp_flag:1;
u8 rdr_info_sg0_pw_m:3;
u8 rdr_info_sg1_pw_l:4;
u8 rdr_info_sg1_pri_m:4;
u8 rdr_info_zw_pri_l:1;
u8 rdr_info_zw_chirp_flag:1;
u8 rdr_info_sg1_pw_m:6;
u8 rdr_info_zw_pw_l:1;
u8 rdr_info_zw_pri_m:7;
u8 rdr_info_zw_pw_m;
u8 rdr_info_seq:7;
u8 rdr_info_zw_pw_h:1;
};
#endif
/*@--------------------------[Prptotype]-------------------------------------*/
struct bb_info;
struct hal_dfs_rpt;
void halbb_dfs(struct bb_info *bb);
void halbb_mac_cfg_dfs_rpt(struct bb_info *bb, bool rpt_en);
void halbb_dfs_rgn_dmn_dflt_cnfg(struct bb_info *bb);
void halbb_dfs_rgn_dmn_cnfg_by_ch(struct bb_info *bb, bool w53_band,
bool w56_band);
void halbb_radar_chrp_mntr(struct bb_info *bb, bool chrp_flag, bool is_sg1);
void halbb_radar_seq_inspctn(struct bb_info *bb, u16 dfs_rpt_idx,
u8 c_num, u8 p_num, bool is_sg1, u8 c_seg, u8 p_seg);
void halbb_radar_ptrn_cmprn(struct bb_info *bb, u16 dfs_rpt_idx,
u8 pri, u16 pw, bool chrp_flag, bool is_sg1);
void halbb_radar_info_processing(struct bb_info *bb,
struct hal_dfs_rpt *dfs_rpt, u16 dfs_rpt_idx);
void halbb_dfs_dyn_setting(struct bb_info *bb);
void halbb_dfs_debug(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len);
void halbb_cr_cfg_dfs_init(struct bb_info *bb);
#ifdef HALBB_DFS_GEN2_SERIES
void halbb_radar_info_processing_gen2(struct bb_info *bb, struct hal_dfs_rpt *rpt, u16 dfs_rpt_idx);
void halbb_radar_cnt_accumulate(struct bb_info *bb, u8 rpt_idx, bool sub20_1, u8 rdr_type_idx, bool is_long);
void halbb_radar_ptrn_cmprn_gen2(struct bb_info *bb);
u16 halbb_radar_judge_gen2(struct bb_info *bb);
u16 halbb_radar_detect_gen2(struct bb_info *bb, struct hal_dfs_rpt *dfs_rpt);
void halbb_dfs_dyn_setting_gen2(struct bb_info *bb);
void halbb_radar_show_log(struct bb_info *bb, struct hal_dfs_rpt *dfs_rp, u16 rdr_detected);
#endif
#endif
3rd/devourer/hal/halbb/g6/vendor/halbb_dfs_ex.h
Vendored
+62
View File
@@ -0,0 +1,62 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_DFS_EX_H__
#define __HALBB_DFS_EX_H__
/*@--------------------------[Define] ---------------------------------------*/
/*@--------------------------[Enum]------------------------------------------*/
enum halbb_radar_detect_t {
RDR_EXTRA_SUB20_7 = BIT(15),
RDR_EXTRA_SUB20_6 = BIT(14),
RDR_EXTRA_SUB20_5 = BIT(13),
RDR_EXTRA_SUB20_4 = BIT(12),
RDR_EXTRA_SUB20_3 = BIT(11),
RDR_EXTRA_SUB20_2 = BIT(10),
RDR_EXTRA_SUB20_1 = BIT(9),
RDR_EXTRA_SUB20_0 = BIT(8),
RDR_SUB20_7 = BIT(7),
RDR_SUB20_6 = BIT(6),
RDR_SUB20_5 = BIT(5),
RDR_SUB20_4 = BIT(4),
RDR_SUB20_3 = BIT(3),
RDR_SUB20_2 = BIT(2),
RDR_SUB20_1 = BIT(1),
RDR_SUB20_0 = BIT(0),
RDR_EXTRA_FULL = 0xff00,
RDR_FULL = 0x00ff
};
/*@--------------------------[Structure]-------------------------------------*/
struct bb_info;
struct hal_dfs_rpt;
/*@--------------------------[Prptotype]-------------------------------------*/
void halbb_dfs_init(struct bb_info *bb);
void halbb_radar_detect_reset(struct bb_info *bb);
void halbb_radar_detect_disable(struct bb_info *bb);
void halbb_radar_detect_enable(struct bb_info *bb);
void halbb_dfs_enable_cac_flag(struct bb_info* bb);
void halbb_dfs_disable_cac_flag(struct bb_info* bb);
void halbb_dfs_change_dmn(struct bb_info *bb, u8 ch, u8 bw);
bool halbb_is_dfs_band(struct bb_info *bb, u8 ch, u8 bw);
u16 halbb_radar_detect(struct bb_info *bb, struct hal_dfs_rpt *rpt);
#endif
3rd/devourer/hal/halbb/g6/vendor/halbb_dig.c
Vendored
+2713
View File
File diff suppressed because it is too large Load Diff
3rd/devourer/hal/halbb/g6/vendor/halbb_dig.h
Vendored
+396
View File
@@ -0,0 +1,396 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_DIG_H__
#define __HALBB_DIG_H__
#define DIG_VERSION "5.0"
//#define DIG_DBCC_DEV_TMP
/*@--------------------------[Define] ---------------------------------------*/
#define BB_LNA_SIZE 7
#define BB_TIA_SIZE 2
#define IGI_RSSI_TH_NUM 5
#define FA_TH_NUM 4
#define RSSI_MAX 110
#define RSSI_MIN 0
#ifdef DIG_DBCC_DEV_TMP
#define IGI_NOLINK (38 + 20)
#else
#define IGI_NOLINK 38
#endif
#define LNA_IDX_MAX 6
#define LNA_IDX_MIN 0
#define TIA_IDX_MAX 1
#define TIA_IDX_MIN 0
#define RXB_IDX_MAX 31
#define RXB_IDX_MIN 0
#define LNA6_GAIN 24
#define LNA5_GAIN 16
#define LNA4_GAIN 8
#define LNA3_GAIN 0
#define LNA2_GAIN (-8)
#define LNA1_GAIN (-16)
#define LNA0_GAIN (-24)
#define TIA1_GAIN_A 20
#define TIA0_GAIN_A 12
#define TIA1_GAIN_G 24
#define TIA0_GAIN_G 16
#define IGI_OFFSET_MAX 25 /* IGI window size */
#define IGI_MAX_PERFORMANCE_MODE 0x5a
#define IGI_MAX_BALANCE_MODE 0x3e
#define PD_TH_MAX_RSSI 70 /* -40dBm */
#define PD_TH_MIN_RSSI 8 /* -102dBm */
#define PD_TH_BW80_CMP_VAL 6
#define PD_TH_BW40_CMP_VAL 3
#define PD_TH_BW20_CMP_VAL 0
#define PD_TH_SB_FLTR_CMP_VAL 7
#define DIG_CCX_WD_TRIGTIME 1900
#define IGI_EDCCA_GAP_LIMIT 35
#ifdef HALBB_DIG_TDMA_SUPPORT
#define IGI_MAX_AT_STATE_L 0x26
#define WACHDOG_PERIOD_IN_MS 2000
#define H_STATE_NUM_MAX 20
#define L_STATE_NUM_MAX 10
#endif
#define DIG_RECORD_NUM 6
#define DIG_LIMIT_PERIOD 60 /*60 sec*/
#define DIG_EVENT_PERIOD 5
#ifdef HALBB_DBG_TRACE_SUPPORT
#define BB_DIG_DBG(bb, lv, fmt, ...)\
do {\
if(bb->dbg_component & DBG_DIG && bb->bb_dig_i.dbg_lv >= lv) {\
_os_dbgdump("[BB][%d]" fmt, bb->bb_phy_idx, ##__VA_ARGS__);\
}\
} while (0)
#else
#define BB_DIG_DBG(bb, lv, fmt, ...)
#endif
/*@--------------------------[Enum]------------------------------------------*/
enum dig_noisy_level {
DIG_NOISY_LV0 = 0, /*FA free*/
DIG_NOISY_LV1 = 1,
DIG_NOISY_LV2 = 2,
DIG_NOISY_LV3 = 3,
DIG_NOISY_LV_MAX = 4
};
#ifdef HALBB_DIG_TDMA_SUPPORT
enum dig_tdma_state {
DIG_TDMA_LOW = 0,
DIG_TDMA_HIGH = 1
};
#endif
enum dig_dbg_level {
DIG_DBG_LV0 = 0,
DIG_DBG_LV1 = 1,
DIG_DBG_LV2 = 2
};
/*@--------------------------[Structure]-------------------------------------*/
struct bb_dig_cr_info {
u32 path0_ib_pbk;
u32 path0_ib_pbk_m;
u32 path0_ib_pkpwr;
u32 path0_ib_pkpwr_m;
u32 path1_ib_pbk;
u32 path1_ib_pbk_m;
u32 path1_ib_pkpwr;
u32 path1_ib_pkpwr_m;
u32 path0_lna_init_idx;
u32 path0_lna_init_idx_m;
u32 path1_lna_init_idx;
u32 path1_lna_init_idx_m;
u32 path0_tia_init_idx;
u32 path0_tia_init_idx_m;
u32 path1_tia_init_idx;
u32 path1_tia_init_idx_m;
u32 path0_rxb_init_idx;
u32 path0_rxb_init_idx_m;
u32 path1_rxb_init_idx;
u32 path1_rxb_init_idx_m;
u32 seg0r_pd_spatial_reuse_en_a;
u32 seg0r_pd_spatial_reuse_en_a_m;
u32 seg0r_pd_lower_bound_a;
u32 seg0r_pd_lower_bound_a_m;
u32 path0_p20_follow_by_pagcugc_en_a;
u32 path0_s20_follow_by_pagcugc_en_a;
u32 path1_p20_follow_by_pagcugc_en_a;
u32 path1_s20_follow_by_pagcugc_en_a;
u32 path0_p20_follow_by_pagcugc_en_a_m;
u32 path0_s20_follow_by_pagcugc_en_a_m;
u32 path1_p20_follow_by_pagcugc_en_a_m;
u32 path1_s20_follow_by_pagcugc_en_a_m;
u32 path0_lna_err_g0_a;
u32 path0_lna_err_g0_a_m;
u32 path0_lna_err_g0_g;
u32 path0_lna_err_g0_g_m;
u32 path0_lna_err_g1_a;
u32 path0_lna_err_g1_a_m;
u32 path0_lna_err_g1_g;
u32 path0_lna_err_g1_g_m;
u32 path0_lna_err_g2_a;
u32 path0_lna_err_g2_a_m;
u32 path0_lna_err_g2_g;
u32 path0_lna_err_g2_g_m;
u32 path0_lna_err_g3_a;
u32 path0_lna_err_g3_a_m;
u32 path0_lna_err_g3_g;
u32 path0_lna_err_g3_g_m;
u32 path0_lna_err_g4_a;
u32 path0_lna_err_g4_a_m;
u32 path0_lna_err_g4_g;
u32 path0_lna_err_g4_g_m;
u32 path0_lna_err_g5_a;
u32 path0_lna_err_g5_a_m;
u32 path0_lna_err_g5_g;
u32 path0_lna_err_g5_g_m;
u32 path0_lna_err_g6_a;
u32 path0_lna_err_g6_a_m;
u32 path0_lna_err_g6_g;
u32 path0_lna_err_g6_g_m;
u32 path0_tia_err_g0_a;
u32 path0_tia_err_g0_a_m;
u32 path0_tia_err_g0_g;
u32 path0_tia_err_g0_g_m;
u32 path0_tia_err_g1_a;
u32 path0_tia_err_g1_a_m;
u32 path0_tia_err_g1_g;
u32 path0_tia_err_g1_g_m;
u32 path1_lna_err_g0_a;
u32 path1_lna_err_g0_a_m;
u32 path1_lna_err_g0_g;
u32 path1_lna_err_g0_g_m;
u32 path1_lna_err_g1_a;
u32 path1_lna_err_g1_a_m;
u32 path1_lna_err_g1_g;
u32 path1_lna_err_g1_g_m;
u32 path1_lna_err_g2_a;
u32 path1_lna_err_g2_a_m;
u32 path1_lna_err_g2_g;
u32 path1_lna_err_g2_g_m;
u32 path1_lna_err_g3_a;
u32 path1_lna_err_g3_a_m;
u32 path1_lna_err_g3_g;
u32 path1_lna_err_g3_g_m;
u32 path1_lna_err_g4_a;
u32 path1_lna_err_g4_a_m;
u32 path1_lna_err_g4_g;
u32 path1_lna_err_g4_g_m;
u32 path1_lna_err_g5_a;
u32 path1_lna_err_g5_a_m;
u32 path1_lna_err_g5_g;
u32 path1_lna_err_g5_g_m;
u32 path1_lna_err_g6_a;
u32 path1_lna_err_g6_a_m;
u32 path1_lna_err_g6_g;
u32 path1_lna_err_g6_g_m;
u32 path1_tia_err_g0_a;
u32 path1_tia_err_g0_a_m;
u32 path1_tia_err_g0_g;
u32 path1_tia_err_g0_g_m;
u32 path1_tia_err_g1_a;
u32 path1_tia_err_g1_a_m;
u32 path1_tia_err_g1_g;
u32 path1_tia_err_g1_g_m;
u32 cca_rssi_lmt_en_a;
u32 cca_rssi_lmt_en_a_m;
u32 rssi_nocca_low_th_a;
u32 rssi_nocca_low_th_a_m;
u32 path0_dig_mode_en_a;
u32 path0_dig_mode_en_a_m;
u32 path0_igi_for_dig_a;
u32 path0_igi_for_dig_a_m;
u32 path0_backoff_wb_gain_a;
u32 path0_backoff_wb_gain_a_m;
u32 path1_dig_mode_en_a;
u32 path1_dig_mode_en_a_m;
u32 path1_igi_for_dig_a;
u32 path1_igi_for_dig_a_m;
u32 path1_backoff_wb_gain_a;
u32 path1_backoff_wb_gain_a_m;
};
struct agc_gaincode_set {
u8 lna_idx;
u8 tia_idx;
u8 rxb_idx;
};
struct bb_dig_fa_info {
u16 fa_r_cck_onesec;
u16 fa_r_ofdm_onesec;
u16 fa_r_onesec; /* overall fa_ratio */
};
struct bb_dig_op_para_unit {
bool dyn_pd_th_en;
u8 igi_rssi_th[IGI_RSSI_TH_NUM];
u16 fa_th[FA_TH_NUM]; /* permil */
};
#ifdef HALBB_DIG_DAMPING_CHK
struct bb_dig_record_info {
u8 igi_bitmap; /*@Don't add any new parameter before this*/
u8 igi_history[DIG_RECORD_NUM];
u32 fa_history[DIG_RECORD_NUM];
bool damping_lock_en;
u8 damping_limit_val; /*@Limit IGI_dyn_min*/
u32 limit_time;
u8 limit_rssi; /*s(8,1)*/
};
#endif
/* struct for state unit, i.e., L/H */
struct bb_dig_op_unit {
#ifdef HALBB_DIG_TDMA_SUPPORT
enum dig_tdma_state state_identifier; /* L/H */
#endif
struct agc_gaincode_set cur_gaincode;
enum dig_noisy_level cur_noisy_lv;
struct agc_gaincode_set force_gaincode;
struct bb_dig_op_para_unit dig_op_para;
u16 fa_r_acc; /* acced one shot fa_ratio */
u16 fa_r_avg; /* acced one shot fa_ratio */
u8 fa_valid_state_cnt;
u8 state_num_lmt;
u8 passed_state_cnt;
u8 igi_fa_rssi; /*final IGI calaulated by FA & RSSI*/
u8 cca_pd_fa_rssi; /*final PD calaulated by FA & RSSI*/
u8 fa_rssi_ofst;
u8 abs_igi_max;
u8 abs_igi_min;
u8 dyn_igi_max;
u8 dyn_igi_min;
u8 pd_low_th_ofst; /* pd low safe cca region */
u8 pd_low_th;
s8 rssi_nocca_low_th;
bool sdagc_follow_pagc_en;
};
struct bb_dig_info {
bool init_dig_cr_success;
enum dig_op_mode dig_mode;
enum dig_op_mode pre_dig_mode;
struct agc_gaincode_set max_gaincode;
u8 igi_rssi; //rssi_min
u8 ib_pbk;
s8 ib_pkpwr;
s8 lna_gain_a[BB_LNA_SIZE];
s8 lna_gain_g[BB_LNA_SIZE];
s8 *lna_gain;
s8 tia_gain_a[BB_TIA_SIZE];
s8 tia_gain_g[BB_TIA_SIZE];
s8 *tia_gain;
s8 le_igi_ofst; /* low end mode IGI offset */
struct bb_dig_op_unit *p_cur_dig_unit;
struct bb_dig_op_unit dig_state_h_i; /* high state */
#ifdef HALBB_DIG_TDMA_SUPPORT
struct bb_dig_op_unit dig_state_l_i; /* low state */
bool gaincode_update_en;
u16 tdma_passed_time_acc; /* check if 1sec reach */
u8 tdma_timestamp_pre;
u8 tdma_timestamp_cur;
struct halbb_timer_info dig_timer_i;
#endif
#ifdef HALBB_ENV_MNTR_SUPPORT
u8 fahm_timestamp;
struct fahm_para_info fahm_para_i;
bool fahm_is_triggered;
#endif
struct bb_dig_fa_info dig_fa_i;
enum dig_dbg_level dbg_lv;
#ifdef HALBB_SELF_DIAG_SUPPORT
u8 dig_event_cnt;
#endif
u32 rvrt_val[DIG_PAUSE_INFO_SIZE]; /*[Pause fucntion] must set to u32*/
u16 igi_pause_cnt; /*consective pause counter*/
bool need_update;
u16 dig_hold_cnt;
#ifdef HALBB_DIG_DAMPING_CHK
struct bb_dig_record_info bb_dig_record_i;
u8 rls_rssi_diff_th; /*s(8,1)*/
bool dig_dl_en; /*@damping limit function enable*/
bool sr_coexist_en;
u8 igi_ofst_sr_coexist; /* igi low offset for SR coexistence */
#endif
};
#ifdef HALBB_MCC_SUPPORT
#if PLATFOM_IS_LITTLE_ENDIAN
struct halbb_c2h_mr_dm {
u8 cur_mr_dm_en: 1;
u8 mrdm_err_hdl:4;
u8 rsvd0: 3;
u8 mrdm_switch_reg_cnt;
u8 central_ch;
u8 sw_mlo_mod;
};
#else
struct halbb_c2h_mr_dm {
u8 rsvd0: 3;
u8 mrdm_err_hdl:4;
u8 cur_mr_dm_en: 1;
u8 mrdm_switch_reg_cnt;
u8 central_ch;
u8 sw_mlo_mod;
};
#endif
#endif
struct bb_info;
/*@--------------------------[Prptotype]-------------------------------------*/
#ifdef HALBB_DIG_TDMA_SUPPORT
void halbb_dig_timercheck_watchdog(struct bb_info*);
void halbb_tdmadig_io_en(struct bb_info *bb);
void halbb_dig_timer_init(struct bb_info *bb);
#endif
void halbb_dig_lps(struct bb_info *bb);
void halbb_dig_cfg_bbcr(struct bb_info *bb, u8 igi_new);
u8 halbb_dig_igi_by_ofst(struct bb_info *bb, u8 igi_pre, s8 ofst);
void halbb_dig(struct bb_info *bb);
void halbb_dig_init(struct bb_info *bb);
void halbb_dig_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len);
void halbb_cr_cfg_dig_init(struct bb_info *bb);
void* halbb_get_dig_fa_statistic(struct bb_info *bb);
void halbb_set_dig_pause_val(struct bb_info *bb, u32 *val_buf, u8 val_len);
#ifdef HALBB_DIG_SUPPORT
#ifdef HALBB_MCC_SUPPORT
void halbb_init_mccdm(struct bb_info *bb);
void halbb_mccdm_switch(struct bb_info *bb);
u32 halbb_c2h_mccdm_check(struct bb_info *bb, u16 len, u8 *c2h);
void halbb_mccdm_ctrl(struct bb_info *bb);
#endif
#endif
u8 halbb_get_lna_idx(struct bb_info *bb, enum rf_path path);
u8 halbb_get_tia_idx(struct bb_info *bb, enum rf_path path);
u8 halbb_get_rxb_idx(struct bb_info *bb, enum rf_path path);
#endif
3rd/devourer/hal/halbb/g6/vendor/halbb_dig_ex.h
Vendored
+59
View File
@@ -0,0 +1,59 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_DIG_EX_H__
#define __HALBB_DIG_EX_H__
/*@--------------------------[Define] ---------------------------------------*/
#define DIG_PAUSE_INFO_SIZE 2
/*@--------------------------[Enum]------------------------------------------*/
enum dig_op_mode {
DIG_ORIGIN = 0,
#ifdef HALBB_DIG_TDMA_SUPPORT
DIG_TDMA = 1,
DIG_TDMA_ADV = 2,
#endif
DIG_SIMPLE = 3,
DIG_NONE
};
enum dig_pause_case {
PAUSE_OFDM = 0,
PAUSE_OFDM_CCK = 1
};
/*@--------------------------[Structure]-------------------------------------*/
struct bb_bkp_dig_info {
u8 h_pd_low_th;
u8 l_pd_low_th;
s8 h_rssi_nocca_low_th;
s8 l_rssi_nocca_low_th;
};
struct bb_info;
/*@--------------------------[Prptotype]-------------------------------------*/
void halbb_dig_mode_update(struct bb_info *bb, enum dig_op_mode mode, enum phl_phy_idx phy_idx);
void halbb_dig_simple(struct bb_info *bb, u8 rssi_ofst);
u8 halbb_get_dig_igi(struct bb_info *bb);
void halbb_query_dig_info(struct bb_info *bb_0, struct bb_bkp_dig_info *dig_i, enum phl_phy_idx phy_idx);
#endif
3rd/devourer/hal/halbb/g6/vendor/halbb_dv_dbg.h
Vendored
+52
View File
@@ -0,0 +1,52 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_DV_PXP_DBG_H__
#define __HALBB_DV_PXP_DBG_H__
#include "../../hal_headers_le.h"
/*@--------------------------[Define] ---------------------------------------*/
/*@--------------------------[Enum]------------------------------------------*/
/*@--------------------------[Structure]-------------------------------------*/
struct bb_dv_pxp_dbg_info {
bool is_dv_pxp_dbg;
bool is_print;
};
struct bb_dv_pxp_dbg_cr_info {
u32 dummy;
};
/*@--------------------------[Prptotype]-------------------------------------*/
struct bb_info;
void halbb_dv_pxp_dbg(struct bb_info *bb, char input[][16], u32 *_used, char *output, u32 *_out_len);
void halbb_dv_pxp_print_en(struct bb_info *bb, bool en);
void halbb_dv_pxp_dbg_init(struct bb_info *bb);
#if 0
void halbb_cr_cfg_dv_dbg_init(struct bb_info *bb);
#endif
#endif
3rd/devourer/hal/halbb/g6/vendor/halbb_dyn_1r_cca.h
Vendored
+46
View File
@@ -0,0 +1,46 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_DYN_1R_CCA_H__
#define __HALBB_DYN_1R_CCA_H__
#ifdef HALBB_DYN_1R_CCA_SUPPORT
struct bb_dyn_1r_cca_info {
bool dyn_1r_cca_en;
enum rf_path dyn_1r_cca_cfg;
u16 dyn_1r_cca_rssi_diff_th; /*RSSI u(16,5)*/
u16 dyn_1r_cca_rssi_min_th; /*RSSI u(16,5)*/
};
void halbb_dyn_1r_cca_rst(struct bb_info *bb);
void halbb_dyn_1r_cca_dbg(struct bb_info *bb, char input[][16],
u32 *_used, char *output, u32 *_out_len);
void halbb_dyn_1r_cca(struct bb_info *bb);
void halbb_dyn_1r_cca_init(struct bb_info *bb);
#endif
#endif
3rd/devourer/hal/halbb/g6/vendor/halbb_dyn_1r_cca_ex.h
Vendored
+37
View File
@@ -0,0 +1,37 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_DYN_1R_CCA_H__EX_H__
#define __HALBB_DYN_1R_CCA_H__EX_H__
/*@--------------------------[Define] ---------------------------------------*/
/*@--------------------------[Enum]------------------------------------------*/
/*@--------------------------[Structure]-------------------------------------*/
/*@--------------------------[Prptotype]-------------------------------------*/
#endif
3rd/devourer/hal/halbb/g6/vendor/halbb_dyn_csi_rsp.h
Vendored
+62
View File
@@ -0,0 +1,62 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_DYN_CSI_RSP_H__
#define __HALBB_DYN_CSI_RSP_H__
#ifdef HALBB_DYN_CSI_RSP_SUPPORT
struct bf_ch_raw_info {
/*result*/
bool is_csi_rsp_en;
bool cbl_lnk_state;
bool csi_on_chk;
/*state machine*/
u8 dyn_csi_rsp_dbg_en;
u8 dyn_csi_rsp_en;
u8 ch_chk_cnt;
u8 cbl_lnk_cnt;
u8 period_cnt;
/*set val*/
u32 ch_est_dly;
u32 get_phy_sts_dly;
u32 max_est_tone_num;
s32 cablelink_cnt_th;
enum channel_width dcr_bw;
};
struct bb_info;
/*@--------------------------[Enum]------------------------------------------*/
enum dcr_csi_rsp {
dcr_csi_rsp_dis = 0, /*Disale*/
dcr_csi_rsp_en = 1, /*Enable*/
};
void halbb_dcr_init(struct bb_info *bb);
void halbb_dcr_reset(struct bb_info *bb);
void halbb_dyn_csi_rsp_dbg(struct bb_info *bb, char input[][16],
u32 *_used, char *output, u32 *_out_len);
void halbb_dyn_csi_rsp_main(struct bb_info *bb);
void halbb_dcr_env_det(struct bb_info * bb);
#endif
#endif
3rd/devourer/hal/halbb/g6/vendor/halbb_dyn_csi_rsp_ex.h
Vendored
+40
View File
@@ -0,0 +1,40 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_DYN_CSI_RSP_EX_H__
#define __HALBB_DYN_CSI_RSP_EX_H__
/*@--------------------------[Define] ---------------------------------------*/
/*@--------------------------[Enum]------------------------------------------*/
/*@--------------------------[Structure]-------------------------------------*/
/*@--------------------------[Prptotype]-------------------------------------*/
bool halbb_dcr_en(struct bb_info *bb, bool en);
bool halbb_dyn_csi_rsp_rlt_get(struct bb_info *bb);
bool halbb_dcr_rssi_chk(struct bb_info * bb);
#endif
3rd/devourer/hal/halbb/g6/vendor/halbb_dyn_dtr.h
Vendored
+54
View File
@@ -0,0 +1,54 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_DYN_DTR_H__
#define __HALBB_DYN_DTR_H__
struct bb_dyn_dtr_info {
bool dtr_trig_by_timer_en;
bool dyn_dtr_en;
bool dyn_dtr_acc_en;
u8 dyn_dtr_rssi_th_2g;
u8 dyn_dtr_rssi_th_5g;
u8 dtr_period_cnt;
u8 dyn_dtr_rssi_th_bkf_2g;
u8 dyn_dtr_rssi_th_bkf_5g;
struct halbb_timer_info dtr_timer_i;
};
struct bb_info;
void halbb_dtr_acc_io_en(struct bb_info *bb);
void halbb_dtr_acc_timer_init(struct bb_info *bb);
void halbb_dtr_deinit(struct bb_info *bb);
void halbb_dyn_dtr_en(struct bb_info *bb, bool en);
void halbb_dyn_dtr_init(struct bb_info *bb);
void halbb_dyn_dtr_main(struct bb_info *bb);
void halbb_dyn_dtr_watchdog(struct bb_info *bb);
void halbb_dyn_dtr_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len);
#endif
3rd/devourer/hal/halbb/g6/vendor/halbb_edcca.c
Vendored
+1591
View File
File diff suppressed because it is too large Load Diff
3rd/devourer/hal/halbb/g6/vendor/halbb_edcca.h
Vendored
+283
View File
@@ -0,0 +1,283 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_EDCCA_H__
#define __HALBB_EDCCA_H__
/*@--------------------------[Define] ---------------------------------------*/
#define EDCCA_HL_DIFF_ADPTVTY 7
#define EDCCA_HL_DIFF_NORMAL 8
// EDCCA
#define CBP_6G 53 /*@-75 dB to avoid cross-band loss*/
#define EDCCA_5G 63 /*@-62 dBm -3 dB margin*/
#define EDCCA_2G 68 /*@-57 dBm -3 dB margin*/
#define CARRIER_SENSE 75 /*@-50dBm -3 dB margin*/
#define EDCCA_TH_INIT 66 /*init val*/
#define EDCCA_MAX 249 /*@ 127dBm for normal mode*/
#define EDCCA_TH_L2H_LB 66 /*@ -62 dBm from IEEE*/
#define EDCCA_TH_H_UP 66 /*@ -62 dBm for normal mode upperbound*/
#define EDCCA_TH_H_LOW 53 /*@ -75 dBm for normal mode loweround*/
#define EDCCA_PWDB_EXCLU_TX 128 /*128 - 256 = -128dBm when Tx*/
#define EDCCA_PWDB_TO_RSSI(pwdb) ((pwdb + 110) < 0 ? 0 : (pwdb + 110))
#define EDCCA_PWROFST_DEFAULT 18 /*2dB is phyUD default value. Note that the loss from adc to snd is actually 0.5dB*/
#define EDCCA_TH_REF 3
// Collision T2R/R2T TH
#define COLLOSION_TH_LOW 0
#define COLLOSION_TH_HIGH 31
#define COLLOSION_TH_RSSI2VAL 50
#define COLLOSION_TH_OFST 0
// FW EDCCA
#define EDCCA_5G_TH 70 // -62
#define EDCCA_2p4G_TH 65// -57
#define CARRIER_SENSE_TH 58 // -50
/*@--------------------------[Enum]------------------------------------------*/
/*@--------------------------[Structure]-------------------------------------*/
struct bb_h2c_fw_edcca {
u8 mode;
u8 band;
u8 pwr_th_5g;
u8 pwr_th_2p4;
u8 pwr_th_cs;
u8 enable;
u8 rsvd1;
u8 rsvd2;
};
struct bb_edcca_cr_info {
u32 r_snd_en;
u32 r_snd_en_m;
u32 r_snd_en_s80_1;
u32 r_snd_en_s80_1_m;
u32 r_snd_en_s80_2;
u32 r_snd_en_s80_2_m;
u32 r_snd_en_s80_3;
u32 r_snd_en_s80_3_m;
u32 r_dwn_level;
u32 r_dwn_level_m;
u32 r_dwn_level_s80_1;
u32 r_dwn_level_s80_1_m;
u32 r_dwn_level_s80_2;
u32 r_dwn_level_s80_2_m;
u32 r_dwn_level_s80_3;
u32 r_dwn_level_s80_3_m;
u32 r_edcca_level;
u32 r_edcca_level_m;
u32 r_edcca_level_p;
u32 r_edcca_level_p_m;
u32 r_edcca_level_s80_1;
u32 r_edcca_level_s80_1_m;
u32 r_edcca_level_s80_1_p;
u32 r_edcca_level_s80_1_p_m;
u32 r_edcca_level_s80_2;
u32 r_edcca_level_s80_2_m;
u32 r_edcca_level_s80_2_p;
u32 r_edcca_level_s80_2_p_m;
u32 r_edcca_level_s80_3;
u32 r_edcca_level_s80_3_m;
u32 r_edcca_level_s80_3_p;
u32 r_edcca_level_s80_3_p_m;
u32 r_edcca_rpt_a;
u32 r_edcca_rpt_a_m;
u32 r_edcca_rpt_b;
u32 r_edcca_rpt_b_m;
u32 r_edcca_rpt_a_p1;
u32 r_edcca_rpt_a_p1_m;
u32 r_edcca_rpt_b_p1;
u32 r_edcca_rpt_b_p1_m;
u32 r_edcca_rpt_sel;
u32 r_edcca_rpt_sel_m;
u32 r_edcca_rpt_sel_p1;
u32 r_edcca_rpt_sel_p1_m;
u32 r_edcca_rptreg_sel_be_dd;
u32 r_edcca_rptreg_sel_be_dd_m;
u32 r_ppdu_level;
u32 r_ppdu_level_m;
u32 r_ppdu_level_p;
u32 r_ppdu_level_p_m;
u32 r_obss_level;
u32 r_obss_level_m;
u32 collision_r2t_th;
u32 collision_r2t_th_m;
u32 collision_t2r_th_mcs0;
u32 collision_t2r_th_mcs0_m;
u32 collision_t2r_th_mcs1;
u32 collision_t2r_th_mcs1_m;
u32 collision_t2r_th_mcs2;
u32 collision_t2r_th_mcs2_m;
u32 collision_t2r_th_mcs3;
u32 collision_t2r_th_mcs3_m;
u32 collision_t2r_th_mcs4;
u32 collision_t2r_th_mcs4_m;
u32 collision_t2r_th_mcs5;
u32 collision_t2r_th_mcs5_m;
u32 collision_t2r_th_mcs6;
u32 collision_t2r_th_mcs6_m;
u32 collision_t2r_th_mcs7;
u32 collision_t2r_th_mcs7_m;
u32 collision_t2r_th_mcs8;
u32 collision_t2r_th_mcs8_m;
u32 collision_t2r_th_mcs9;
u32 collision_t2r_th_mcs9_m;
u32 collision_t2r_th_mcs10;
u32 collision_t2r_th_mcs10_m;
u32 collision_t2r_th_mcs11;
u32 collision_t2r_th_mcs11_m;
u32 collision_t2r_th_mcs12;
u32 collision_t2r_th_mcs12_m;
u32 collision_t2r_th_mcs13;
u32 collision_t2r_th_mcs13_m;
u32 collision_t2r_th_cck;
u32 collision_t2r_th_cck_m;
u32 collision_t2r_th_cck_1M;
u32 collision_t2r_th_cck_1M_m;
u32 collision_t2r_th_cck_2M;
u32 collision_t2r_th_cck_2M_m;
u32 collision_t2r_th_cck_5p5M;
u32 collision_t2r_th_cck_5p5M_m;
u32 collision_t2r_th_cck_11M;
u32 collision_t2r_th_cck_11M_m;
u32 collision_map2dbm;
u32 collision_map2dbm_m;
u32 collision_t2r_th_he_dcm_mcs0;
u32 collision_t2r_th_he_dcm_mcs0_m;
u32 collision_t2r_th_he_dcm_mcs1;
u32 collision_t2r_th_he_dcm_mcs1_m;
u32 collision_t2r_th_he_dcm_mcs2;
u32 collision_t2r_th_he_dcm_mcs2_m;
u32 collision_t2r_th_he_dcm_mcs3;
u32 collision_t2r_th_he_dcm_mcs3_m;
u32 collision_t2r_th_he_dcm_mcs4;
u32 collision_t2r_th_he_dcm_mcs4_m;
u32 collision_t2r_th_eht_dcm_mcs14;
u32 collision_t2r_th_eht_dcm_mcs14_m;
u32 collision_t2r_th_eht_dcm_mcs15;
u32 collision_t2r_th_eht_dcm_mcs15_m;
u32 collision_t2r_th_legacy_6M;
u32 collision_t2r_th_legacy_6M_m;
u32 collision_t2r_th_legacy_9M;
u32 collision_t2r_th_legacy_9M_m;
u32 collision_t2r_th_legacy_12M;
u32 collision_t2r_th_legacy_12M_m;
u32 collision_t2r_th_legacy_18M;
u32 collision_t2r_th_legacy_18M_m;
u32 collision_t2r_th_legacy_24M;
u32 collision_t2r_th_legacy_24M_m;
u32 collision_t2r_th_legacy_36M;
u32 collision_t2r_th_legacy_36M_m;
u32 collision_t2r_th_legacy_48M;
u32 collision_t2r_th_legacy_48M_m;
u32 collision_t2r_th_legacy_54M;
u32 collision_t2r_th_legacy_54M_m;
u32 r_collision_t2r_state;
u32 r_collision_t2r_state_m;
u32 r_pwrofst;
u32 r_pwrofst_m;
u32 r_dc_remove;
u32 r_dc_remove_m;
};
struct edcca_hw_rpt {
s8 pwdb_fb; /*52A/52B is 0 when BW=40, 92XB would fix*/
s8 pwdb_p20;
s8 pwdb_s20;
s8 pwdb_s40;
s8 pwdb_s80;
bool flag_fb;
bool flag_p20;
bool flag_s20;
bool flag_s40;
bool flag_s80;
s8 pwdb_0;
s8 pwdb_1;
s8 pwdb_2;
s8 pwdb_3;
s8 pwdb_4;
s8 pwdb_5;
s8 pwdb_6;
s8 pwdb_7;
s8 pwdb_8;
u8 path;
s8 per20_bitmap_0;
s8 per20_bitmap_1;
s8 per20_bitmap_2;
s8 per20_bitmap_3;
s8 per20_bitmap_4;
s8 per20_bitmap_5;
s8 per20_bitmap_6;
s8 per20_bitmap_7;
};
struct bb_edcca_info {
u8 th_l;
u8 th_h;
u8 th_hl_diff;
u8 edcca_mode;
u8 th_h_lb;
u8 th_h_6g;
u8 th_h_5g;
u8 th_h_2p4g;
u8 th_h_cs;
u8 th_h_nrml_up;
u8 th_h_nrml_low;
u8 th_h_obss;
bool collision_th_en;
u8 colli_th;
u8 colli_ofst;
struct edcca_hw_rpt edcca_rpt;
u8 pwrofst; /*max(ext_loss, 2), 0~31=>[-16:1:15]*/
u32 rvrt_val; /*all rvrt_val for pause API must set to u32*/
bool init_edcca_cr_success;
};
#ifdef HALBB_DYN_L2H_SUPPORT
struct bb_dyn_l2h_info {
bool en_dyn_l2h;
u32 low_rate_rty_cnt;
u32 drop_cnt;
u8 l2h_th;
};
#endif
struct bb_info;
/*@--------------------------[Prptotype]-------------------------------------*/
void halbb_edcca_get_result(struct bb_info *bb);
void halbb_edcca(struct bb_info *bb);
void halbb_edcca_thre_calc(struct bb_info * bb);
void halbb_set_collision_th(struct bb_info *bb);
void halbb_set_collision_thre(struct bb_info *bb);
void halbb_set_edcca_pause_val(struct bb_info *bb, u32 *val_buf, u8 val_len);
void halbb_edcca_event_nofity(struct bb_info * bb, u8 pause_type);
void halbb_edcca_dev_hw_cap(struct bb_info * bb);
void halbb_edcca_init_io_en(struct bb_info *bb);
void halbb_edcca_init(struct bb_info *bb);
void halbb_cr_cfg_edcca_init(struct bb_info *bb);
void halbb_edcca_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len);
void halbb_edcca_cmn_log(struct bb_info *bb);
void halbb_edcca_self_diag(struct bb_info *bb);
#endif
3rd/devourer/hal/halbb/g6/vendor/halbb_edcca_ex.h
Vendored
+44
View File
@@ -0,0 +1,44 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_EDCCA_EX_H__
#define __HALBB_EDCCA_EX_H__
/*@--------------------------[Define] ---------------------------------------*/
/*@--------------------------[Enum]------------------------------------------*/
enum bb_edcca_mode {
EDCCA_NORMAL_MODE = 0,
EDCCA_ADAPT_MODE = 1,
EDCCA_CARRIER_SENSE_MODE = 2,
EDCCA_CBP_MODE = 3,
EDCCA_UK_MODE = 4,
EDCCA_SRRC_MODE = 5,
};
/*@--------------------------[Structure]-------------------------------------*/
struct bb_info;
/*@--------------------------[Prptotype]-------------------------------------*/
void halbb_fw_edcca(struct bb_info *bb);
#endif
3rd/devourer/hal/halbb/g6/vendor/halbb_env_mntr.c
Vendored
+5730
View File
File diff suppressed because it is too large Load Diff
3rd/devourer/hal/halbb/g6/vendor/halbb_env_mntr.h
Vendored
+542
View File
@@ -0,0 +1,542 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_ENV_MNTR_H__
#define __HALBB_ENV_MNTR_H__
/*--------------------------[Define] ---------------------------------------*/
#define ENV_MNTR_FAIL_BYTE 0xff
#define ENV_MNTR_FAIL_WORD 0xffff
#define ENV_MNTR_FAIL_DWORD 0xffffffff
#define MAX_ENV_MNTR_TIME 8 /*second*/
#define MS_TO_4US_RATIO 250
/*NHM*/
#define RSSI_2_NHM_TH(rssi) ((rssi) << 1) /*NHM_threshold = u(8,1)*/
#define NHM_TH_2_RSSI(th) (th >> 1)
#define NHM_PWR_OFST 20
#define NHM_NOISE_F_TH 60 /*60/2 = 30 = -80 dBm*/
#define NHM_160M_NOISE_F_TH 70 /*70/2 = 35 = -75 dBm*/
#define NHM_WA_TH 109 /*109 = -1 dBm*/
#define NHM_WA_PWR 26 /*26 - 110 = -84dBm, only for 52A*/
/*FAHM*/
#define RSSI_2_FAHM_TH(rssi) ((rssi) << 1) /*FAHM_threshold = u(8,1)*/
#define FAHM_TH_2_RSSI(th) (th >> 1)
#define FAHM_PWR_OFST 20
#define FAHM_WA_TH 109 /*109 = -1 dBm*/
#define FAHM_INCLU_FA BIT(0)
#define FAHM_INCLU_CRC_OK BIT(1)
#define FAHM_INCLU_CRC_ERR BIT(2)
#define FAHM_TH_NUM 11 /*threshold number of FAHM*/
#define FAHM_RPT_NUM 12
/*--------------------------[Enum]------------------------------------------*/
enum ccx_unit {
CCX_04_US = 0, /*4us*/
CCX_08_US = 1, /*8us*/
CCX_16_US = 2, /*16us*/
CCX_32_US = 3 /*32us*/
};
enum fahm_application {
FAHM_INIT = 0,
FAHM_BACKGROUND = 1, /*IEEE 11K for background*/
FAHM_DIG = 2,
FAHM_DBG_11K = 3, /*IEEE 11K for dbg cmd*/
FAHM_DBG_MANUAL = 4 /*fahm_th[0] & th_ofst is manual*/
};
enum env_mntr_sel {
NHM_SEL = BIT(0),
CLM_SEL = BIT(1),
IFS_CLM_SEL = BIT(2),
EDCCA_CLM_SEL = BIT(3),
FAHM_SEL = BIT(4),
CCX_SEL_EXCLU_NHM_FAHM = 0xe,
CCX_SEL_EXCLU_FAHM = 0xf,
CCX_SEL = 0x1f
};
enum env_mode_detection_sel {
ENV_RVR_CLEAN = 0, /*clean, AWGN, | Shielding BOX & Conductive link*/
ENV_SMALL_AREA_CLEAN, /*without-intf, low delay spread | Single House*/
ENV_SMALL_AREA_NOISY_LV1, /*L-intf, low delay spread | Townhouse*/
ENV_SMALL_AREA_NOISY_LV2, /*M-intf, low delay spread | Condo, Cofee shop*/
ENV_SMALL_AREA_NOISY_LV3, /*H-intf, low delay spread | Small Office*/
ENV_LARGE_AREA_CLEAN, /*without-intf, large delay spread | Outdoor*/
ENV_LARGE_AREA_NOISY_LV1, /*L-intf, large delay spread | School*/
ENV_LARGE_AREA_NOISY_LV2, /*M-intf, large delay spread | Shopping mall*/
ENV_LARGE_AREA_NOISY_LV3, /*H-intf, large delay spread | Large Office*/
};
/*--------------------------[Structure]-------------------------------------*/
struct bb_env_mntr_cr_info {
u32 ccx_en;
u32 ccx_en_m;
u32 ccx_trig_opt;
u32 ccx_trig_opt_m;
u32 ccx_trig;
u32 ccx_trig_m;
u32 ccx_edcca_opt;
u32 ccx_edcca_opt_m;
u32 ccx_source_sel;
u32 ccx_source_sel_m;
u32 clm_unit_idx;
u32 clm_unit_idx_m;
u32 clm_en;
u32 clm_en_m;
u32 clm_opt;
u32 clm_opt_m;
u32 clm_period;
u32 clm_period_m;
u32 clm_dbg_sel;
u32 clm_dbg_sel_m;
u32 clm_nav_en;
u32 clm_nav_en_m;
u32 clm_rssi_th_en;
u32 clm_rssi_th_en_m;
u32 clm_rssi_th;
u32 clm_rssi_th_m;
u32 clm_cnt;
u32 clm_cnt_m;
u32 clm_rdy;
u32 clm_rdy_m;
u32 edcca_clm_period;
u32 edcca_clm_period_m;
u32 edcca_clm_unit_idx;
u32 edcca_clm_unit_idx_m;
u32 edcca_clm_en;
u32 edcca_clm_en_m;
u32 edcca_clm_cnt;
u32 edcca_clm_cnt_m;
u32 edcca_clm_rdy;
u32 edcca_clm_rdy_m;
u32 nhm_en;
u32 nhm_en_m;
u32 nhm_method_sel;
u32 nhm_method_sel_m;
u32 nhm_period;
u32 nhm_period_m;
u32 nhm_unit_idx;
u32 nhm_unit_idx_m;
u32 nhm_inclu_cca;
u32 nhm_inclu_cca_m;
u32 nhm_nav_en;
u32 nhm_nav_en_m;
u32 nhm_rssi_th_en;
u32 nhm_rssi_th_en_m;
u32 nhm_rssi_th;
u32 nhm_rssi_th_m;
u32 nhm_th0;
u32 nhm_th0_m;
u32 nhm_th1;
u32 nhm_th1_m;
u32 nhm_th2;
u32 nhm_th2_m;
u32 nhm_th3;
u32 nhm_th3_m;
u32 nhm_th4;
u32 nhm_th4_m;
u32 nhm_th5;
u32 nhm_th5_m;
u32 nhm_th6;
u32 nhm_th6_m;
u32 nhm_th7;
u32 nhm_th7_m;
u32 nhm_th8;
u32 nhm_th8_m;
u32 nhm_th9;
u32 nhm_th9_m;
u32 nhm_th10;
u32 nhm_th10_m;
u32 nhm_cnt0;
u32 nhm_cnt0_m;
u32 nhm_cnt1;
u32 nhm_cnt1_m;
u32 nhm_cnt2;
u32 nhm_cnt2_m;
u32 nhm_cnt3;
u32 nhm_cnt3_m;
u32 nhm_cnt4;
u32 nhm_cnt4_m;
u32 nhm_cnt5;
u32 nhm_cnt5_m;
u32 nhm_cnt6;
u32 nhm_cnt6_m;
u32 nhm_cnt7;
u32 nhm_cnt7_m;
u32 nhm_cnt8;
u32 nhm_cnt8_m;
u32 nhm_cnt9;
u32 nhm_cnt9_m;
u32 nhm_cnt10;
u32 nhm_cnt10_m;
u32 nhm_cnt11;
u32 nhm_cnt11_m;
u32 nhm_cca_cnt;
u32 nhm_cca_cnt_m;
u32 nhm_tx_cnt;
u32 nhm_tx_cnt_m;
u32 nhm_idle_cnt;
u32 nhm_idle_cnt_m;
u32 nhm_rdy;
u32 nhm_rdy_m;
u32 fahm_en;
u32 fahm_en_m;
u32 fahm_ofdm_en;
u32 fahm_ofdm_en_m;
u32 fahm_cck_en;
u32 fahm_cck_en_m;
u32 fahm_numer_opt;
u32 fahm_numer_opt_m;
u32 fahm_denom_opt;
u32 fahm_denom_opt_m;
u32 fahm_dis_count_each_mpdu;
u32 fahm_dis_count_each_mpdu_m;
u32 fahm_period;
u32 fahm_period_m;
u32 fahm_unit_idx;
u32 fahm_unit_idx_m;
u32 fahm_method_sel;
u32 fahm_method_sel_m;
u32 fahm_th0;
u32 fahm_th0_m;
u32 fahm_th1;
u32 fahm_th1_m;
u32 fahm_th2;
u32 fahm_th2_m;
u32 fahm_th3;
u32 fahm_th3_m;
u32 fahm_th4;
u32 fahm_th4_m;
u32 fahm_th5;
u32 fahm_th5_m;
u32 fahm_th6;
u32 fahm_th6_m;
u32 fahm_th7;
u32 fahm_th7_m;
u32 fahm_th8;
u32 fahm_th8_m;
u32 fahm_th9;
u32 fahm_th9_m;
u32 fahm_th10;
u32 fahm_th10_m;
u32 fahm_cnt0;
u32 fahm_cnt0_m;
u32 fahm_cnt1;
u32 fahm_cnt1_m;
u32 fahm_cnt2;
u32 fahm_cnt2_m;
u32 fahm_cnt3;
u32 fahm_cnt3_m;
u32 fahm_cnt4;
u32 fahm_cnt4_m;
u32 fahm_cnt5;
u32 fahm_cnt5_m;
u32 fahm_cnt6;
u32 fahm_cnt6_m;
u32 fahm_cnt7;
u32 fahm_cnt7_m;
u32 fahm_cnt8;
u32 fahm_cnt8_m;
u32 fahm_cnt9;
u32 fahm_cnt9_m;
u32 fahm_cnt10;
u32 fahm_cnt10_m;
u32 fahm_cnt11;
u32 fahm_cnt11_m;
u32 fahm_denom_cnt;
u32 fahm_denom_cnt_m;
u32 fahm_rdy;
u32 fahm_rdy_m;
u32 ifs_clm_en;
u32 ifs_clm_en_m;
u32 ifs_clm_clr;
u32 ifs_clm_clr_m;
u32 ifs_clm_period;
u32 ifs_clm_period_m;
u32 ifs_clm_unit_idx;
u32 ifs_clm_unit_idx_m;
u32 ifs_t1_en;
u32 ifs_t1_en_m;
u32 ifs_t2_en;
u32 ifs_t2_en_m;
u32 ifs_t3_en;
u32 ifs_t3_en_m;
u32 ifs_t4_en;
u32 ifs_t4_en_m;
u32 ifs_t5_en;
u32 ifs_t5_en_m;
u32 ifs_t1_th_l;
u32 ifs_t1_th_l_m;
u32 ifs_t2_th_l;
u32 ifs_t2_th_l_m;
u32 ifs_t3_th_l;
u32 ifs_t3_th_l_m;
u32 ifs_t4_th_l;
u32 ifs_t4_th_l_m;
u32 ifs_t5_th_l;
u32 ifs_t5_th_l_m;
u32 ifs_t1_th_h;
u32 ifs_t1_th_h_m;
u32 ifs_t2_th_h;
u32 ifs_t2_th_h_m;
u32 ifs_t3_th_h;
u32 ifs_t3_th_h_m;
u32 ifs_t4_th_h;
u32 ifs_t4_th_h_m;
u32 ifs_t5_th_h;
u32 ifs_t5_th_h_m;
u32 ifs_clm_tx_cnt;
u32 ifs_clm_tx_cnt_m;
u32 ifs_clm_edcca_exclu_cca;
u32 ifs_clm_edcca_exclu_cca_m;
u32 ifs_clm_cckcca_exclu_fa;
u32 ifs_clm_cckcca_exclu_fa_m;
u32 ifs_clm_ofdmcca_exclu_fa;
u32 ifs_clm_ofdmcca_exclu_fa_m;
u32 ifs_clm_cck_fa;
u32 ifs_clm_cck_fa_m;
u32 ifs_clm_ofdm_fa;
u32 ifs_clm_ofdm_fa_m;
u32 ifs_clm_t1_his;
u32 ifs_clm_t1_his_m;
u32 ifs_clm_t2_his;
u32 ifs_clm_t2_his_m;
u32 ifs_clm_t3_his;
u32 ifs_clm_t3_his_m;
u32 ifs_clm_t4_his;
u32 ifs_clm_t4_his_m;
u32 ifs_clm_t5_his;
u32 ifs_clm_t5_his_m;
u32 ifs_clm_t1_avg;
u32 ifs_clm_t1_avg_m;
u32 ifs_clm_t2_avg;
u32 ifs_clm_t2_avg_m;
u32 ifs_clm_t3_avg;
u32 ifs_clm_t3_avg_m;
u32 ifs_clm_t4_avg;
u32 ifs_clm_t4_avg_m;
u32 ifs_clm_t5_avg;
u32 ifs_clm_t5_avg_m;
u32 ifs_clm_t1_cca;
u32 ifs_clm_t1_cca_m;
u32 ifs_clm_t2_cca;
u32 ifs_clm_t2_cca_m;
u32 ifs_clm_t3_cca;
u32 ifs_clm_t3_cca_m;
u32 ifs_clm_t4_cca;
u32 ifs_clm_t4_cca_m;
u32 ifs_clm_t5_cca;
u32 ifs_clm_t5_cca_m;
u32 ifs_total_cnt;
u32 ifs_total_cnt_m;
u32 ifs_clm_rdy;
u32 ifs_clm_rdy_m;
u32 ifs_clm_cca_opt;
u32 ifs_clm_cca_opt_m;
};
struct fahm_trig_report {
u8 fahm_rpt_stamp;
};
struct fahm_para_info {
enum halbb_racing_lv fahm_rac_lv;
u16 fahm_mntr_time; /*0~2097ms*/
enum fahm_application fahm_app;
u8 fahm_manual_th_ofst;
u8 fahm_manual_th0; /*dbg manual mode*/
u8 fahm_numer_opt;
u8 fahm_denom_opt;
};
struct fahm_report {
u8 fahm_rpt_stamp;
bool fahm_rpt_result;
u8 fahm_rpt[FAHM_RPT_NUM]; /*percent*/
u8 fahm_ratio; /*percent*/
u8 fahm_denom_ratio; /*percent*/
u16 fahm_permil; /*permil*/
u16 fahm_denom_permil; /*permil*/
u8 fahm_pwr; /*110+x(dBm), unit = 1dB*/
u8 fahm_pwr_0p5; /*110+x/2(dBm), unit = 0.5dB*/
};
struct bb_env_mntr_info {
/*sw ctrl*/
u32 ccx_trigger_time;
u8 ccx_rpt_stamp;
u8 ccx_watchdog_result;
bool ccx_ongoing;
u8 ccx_rac_lv;
bool ccx_manual_ctrl;
bool ccx_ext_loss_update;
s8 ccx_ext_loss_pre; /* S(8.1)*/
s8 ccx_ext_loss; /* S(8.1)*/
u16 clm_mntr_time; /*0~2097 ms*/
enum clm_application clm_app;
u16 nhm_mntr_time; /*0~2097 ms*/
enum nhm_application nhm_app;
u16 ifs_clm_mntr_time; /*0~2097 ms*/
enum ifs_clm_application ifs_clm_app;
u32 fahm_trigger_time;
u8 fahm_rpt_stamp;
bool fahm_watchdog_result;
bool fahm_ongoing;
u8 fahm_rac_lv;
bool fahm_manual_ctrl;
u16 fahm_mntr_time; /*0~2097 ms*/
enum fahm_application fahm_app;
u16 edcca_clm_mntr_time; /*0~2097 ms*/
enum edcca_clm_application edcca_clm_app;
/*hw ctrl*/
u16 ccx_period;
u8 ccx_unit_idx;
u8 ccx_edcca_opt;
enum clm_opt_input clm_input_opt;
bool clm_nav_en;
bool clm_rssi_th_en;
u8 clm_rssi_th;
enum nhm_opt_cca_all nhm_include_cca;
u8 nhm_th[NHM_TH_NUM];
bool nhm_nav_en;
bool nhm_rssi_th_en;
u8 nhm_rssi_th;
u16 ifs_clm_th_l[BE_IFS_CLM_NUM];
u16 ifs_clm_th_h[BE_IFS_CLM_NUM];
u16 fahm_period;
u8 fahm_numer_opt;
u8 fahm_denom_opt;
u8 fahm_th[FAHM_TH_NUM];
/*hw report*/
u16 clm_result; /*sample cnt*/
u16 nhm_result[NHM_RPT_NUM]; /*sample cnt*/
u16 nhm_tx_cnt; /*sample cnt*/
u16 nhm_cca_cnt; /*sample cnt*/
u16 nhm_idle_cnt; /*sample cnt*/
u16 ifs_clm_tx; /*sample cnt*/
u16 ifs_clm_edcca_excl_cca; /*sample cnt*/
u16 ifs_clm_ofdmfa; /*sample cnt*/
u16 ifs_clm_ofdmcca_excl_fa; /*sample cnt*/
u16 ifs_clm_cckfa; /*sample cnt*/
u16 ifs_clm_cckcca_excl_fa; /*sample cnt*/
u16 ifs_clm_total_ifs; /*cnt*/
u16 ifs_clm_his[BE_IFS_CLM_NUM]; /*cnt*/
u16 ifs_clm_avg[BE_IFS_CLM_NUM]; /*sample cnt*/
u16 ifs_clm_cca[BE_IFS_CLM_NUM]; /*sample cnt*/
u16 fahm_result[FAHM_RPT_NUM]; /*sample cnt*/
u16 fahm_denom_result; /*sample cnt*/
u16 edcca_clm_result; /*sample cnt*/
/*sw report*/
u8 clm_ratio; /*percent*/
u16 nhm_sw_result[NHM_RPT_NUM]; /*sample cnt*/
u8 nhm_wgt[NHM_RPT_NUM]; /*dBm+110*/
u8 nhm_rpt[NHM_RPT_NUM]; /*percent*/
u8 nhm_tx_ratio; /*percent*/
u8 nhm_cca_ratio; /*percent*/
u8 nhm_idle_ratio; /*percent*/
u8 nhm_ratio; /*percent*/
u16 nhm_result_sum; /*sample cnt*/
u8 nhm_pwr; /*110+x => dBm, unit = 1dB*/
u8 nhm_pwr_0p5; /*110+x/2 => dBm, unit = 0.5dB*/
u8 ifs_clm_tx_ratio; /*percent*/
u8 ifs_clm_edcca_excl_cca_ratio; /*percent*/
u8 ifs_clm_cck_fa_ratio; /*percent*/
u8 ifs_clm_ofdm_fa_ratio; /*percent*/
u8 ifs_clm_cck_cca_excl_fa_ratio; /*percent*/
u8 ifs_clm_ofdm_cca_excl_fa_ratio; /*percent*/
u16 ifs_clm_cck_fa_permil; /*permil*/
u16 ifs_clm_ofdm_fa_permil; /*permil*/
u32 ifs_clm_ifs_avg[BE_IFS_CLM_NUM]; /*us*/
u32 ifs_clm_cca_avg[BE_IFS_CLM_NUM]; /*us*/
u16 fahm_sw_result[FAHM_RPT_NUM]; /*sample cnt*/
u8 fahm_wgt[FAHM_RPT_NUM]; /*dBm+110*/
u8 fahm_rpt[FAHM_RPT_NUM]; /*percent*/
u16 fahm_result_sum; /*sample cnt*/
u8 fahm_ratio; /*percent*/
u8 fahm_denom_ratio; /*percent*/
u16 fahm_permil; /*permil*/
u16 fahm_denom_permil; /*permil*/
u8 fahm_pwr; /*110+x => dBm, unit = 1dB*/
u8 fahm_pwr_0p5; /*110+x/2 => dBm, unit = 0.5dB*/
u8 edcca_clm_ratio; /*percent*/
u8 edcca_noise_bg; /*dBm+110, only for 52A*/
struct env_mntr_rpt env_mntr_rpt_bg;
struct ccx_para_info ccx_para_info_bg;
struct fahm_report fahm_report_bg;
struct fahm_para_info fahm_para_info_bg;
u16 idle_pwr_physts; /*RSSI u(16,3) Idle time pwr from physts*/
u32 tmp_val; /*dummy for pause function*/
u32 rvrt_val; /*dummy for pause function*/
enum env_mode_detection_sel env_mode;
};
struct bb_c2h_nhm_info {
u8 nhm_rpt[NHM_RPT_NUM]; /*percent*/
u8 nhm_tx_ratio; /*percent*/
u8 nhm_cca_ratio; /*percent*/
u8 nhm_idle_ratio; /*percent*/
u8 nhm_ratio; /*percent*/
u8 nhm_pwr_0p5; /*110+x/2 => dBm, unit = 0.5dB*/
u8 phy_idx;
};
/*--------------------------[Prptotype]-------------------------------------*/
struct bb_info;
u32 halbb_ccx_idx_cnt_2_us(struct bb_info *bb, u16 idx_cnt);
#ifdef CLM_SUPPORT
void halbb_clm_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len);
#endif
#ifdef NHM_SUPPORT
void halbb_nhm_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len);
#endif
#ifdef IFS_CLM_SUPPORT
void halbb_ifs_clm_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len);
#endif
#ifdef FAHM_SUPPORT
bool halbb_fahm_trigger(struct bb_info *bb, struct fahm_para_info *para,
struct fahm_trig_report *trig_rpt);
bool halbb_fahm_result(struct bb_info *bb, struct fahm_report *rpt);
void halbb_fahm_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len);
#endif
#ifdef EDCCA_CLM_SUPPORT
void halbb_edcca_clm_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len);
#endif
u32 halbb_env_mntr_get_fw_result_c2h(struct bb_info *bb, u8 *c2h);
void halbb_env_mntr_log(struct bb_info *bb, u32 dbg_comp);
void halbb_idle_time_pwr_physts(struct bb_info *bb, struct physts_rxd *desc,
bool is_cck_rate);
void halbb_env_mntr_pause_val(struct bb_info *bb, u32 *val_buf, u8 val_len);
void halbb_env_mntr(struct bb_info *bb);
void halbb_env_mntr_init(struct bb_info *bb);
void halbb_env_mntr_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len);
void halbb_cr_cfg_env_mntr_init(struct bb_info *bb);
#endif
3rd/devourer/hal/halbb/g6/vendor/halbb_env_mntr_ex.h
Vendored
+226
View File
@@ -0,0 +1,226 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_ENV_MNTR_EX_H__
#define __HALBB_ENV_MNTR_EX_H__
/*--------------------------[Define] ---------------------------------------*/
/*NHM*/
#define NHM_TH_NUM 11 /*threshold number of NHM*/
#define NHM_RPT_NUM 12
/*IFS-CLM*/
#define IFS_CLM_NUM 4
#define BE_IFS_CLM_NUM 5
/*--------------------------[Enum]------------------------------------------*/
enum mntr_result_lv {
CCX_FAIL = 0,
NHM_SUCCESS = BIT(0),
CLM_SUCCESS = BIT(1),
IFS_CLM_SUCCESS = BIT(2),
EDCCA_CLM_SUCCESS = BIT(3),
CCX_SUCCESS = 0xf, /*exclude FAHM*/
};
enum halbb_racing_lv {
RAC_RELEASE = 0,
RAC_LV_1 = 1, /* Low Priority function */
RAC_LV_2 = 2, /* Middle Priority function */
RAC_LV_3 = 3, /* High priority function (ex: Check hang function) */
RAC_LV_4 = 4, /* Debug function (the highest priority) */
RAC_MAX_NUM = 5
};
enum ccx_edcca_opt_sc_idx {
CCX_EDCCA_P0 = 0, /*p20*/
CCX_EDCCA_S1 = 1, /*s20*/
CCX_EDCCA_S2 = 2, /*s40, opposite of p20*/
CCX_EDCCA_S3 = 3, /*s40, opposite of s20*/
};
enum nhm_opt_cca_all {
NHM_EXCLUDE_CCA = 0,
NHM_INCLUDE_CCA = 1,
NHM_CCA_INIT
};
enum nhm_opt_nav_en {
NHM_NAV_EN_DISABLED = 0,
NHM_NAV_EN_ENABLED = 1,
NHM_NAV_EN_INIT
};
enum nhm_opt_rssi_th_en {
NHM_RSSI_TH_EN_DISABLED = 0,
NHM_RSSI_TH_EN_ENABLED = 1,
NHM_RSSI_TH_EN_INIT
};
enum clm_opt_input {
CLM_CCA_P20 = 0,
CLM_CCA_S20 = 1,
CLM_CCA_S40 = 2,
CLM_CCA_S80 = 3,
CLM_CCA_S160 = 4,
CLM_FROM_DBG = 5,
CLM_TXON_CCA = 6,
CLM_CCA_S160_S80_S40_S20 = 7,
CLM_CCA_S160_S80_S40_S20_P20 = 8,
CLM_CCA_INIT
};
#if 0 /*CR Setting Note for AX ICs*/
enum clm_opt_input_ax {
CLM_CCA_P20_ax = 0,
CLM_CCA_S20_ax = 1,
CLM_CCA_S40_ax = 2,
CLM_CCA_S80_ax = 3,
CLM_FROM_DBG_ax = 4,
CLM_TXON_CCA_ax = 5,
CLM_CCA_S80_S40_S20_ax = 6,
CLM_CCA_S80_S40_S20_P20_ax = 7,
};
#endif
enum clm_opt_nav_en {
CLM_NAV_EN_DISABLED = 0,
CLM_NAV_EN_ENABLED = 1,
CLM_NAV_EN_INIT
};
enum clm_opt_rssi_th_en {
CLM_RSSI_TH_EN_DISABLED = 0,
CLM_RSSI_TH_EN_ENABLED = 1,
CLM_RSSI_TH_EN_INIT
};
enum nhm_application {
NHM_INIT = 0,
NHM_BACKGROUND = 1, /*IEEE 11K for background*/
NHM_ACS = 2,
NHM_FW_CTRL = 3,
NHM_DBG_11K = 4, /*IEEE 11K for dbg cmd*/
NHM_DBG_MANUAL = 5 /*nhm_th[0] & th_ofst is manual*/
};
enum clm_application {
CLM_INIT = 0,
CLM_BACKGROUND = 1,/*default*/
CLM_ACS = 2,
CLM_FW_CTRL = 3,
CLM_DBG = 4
};
enum ifs_clm_application {
IFS_CLM_INIT = 0,
IFS_CLM_BACKGROUND = 1,/*default*/
IFS_CLM_ACS = 2,
IFS_CLM_FW_CTRL = 3,
IFS_CLM_DBG = 4,
IFS_CLM_DBG_MANUAL = 5
};
enum edcca_clm_application {
EDCCA_CLM_INIT = 0,
EDCCA_CLM_BACKGROUND = 1,/*default*/
EDCCA_CLM_ACS = 2,
EDCCA_CLM_FW_CTRL = 3,
EDCCA_CLM_DBG = 4
};
/*--------------------------[Structure]-------------------------------------*/
struct bb_info;
struct env_trig_rpt {
u8 ccx_rpt_stamp;
};
struct env_mntr_rpt {
u8 ccx_rpt_stamp;
u8 ccx_rpt_result;
u8 clm_ratio; /*percent*/
u16 clm_result; /*sample cnt*/
u8 nhm_rpt[NHM_RPT_NUM]; /*percent*/
u8 nhm_ratio; /*percent*/
u8 nhm_tx_ratio; /*percent*/
u8 nhm_cca_ratio; /*percent*/
u8 nhm_idle_ratio; /*percent*/
u16 nhm_tx_cnt; /*sample cnt*/
u16 nhm_cca_cnt; /*sample cnt*/
u16 nhm_idle_cnt; /*sample cnt*/
u8 nhm_pwr; /*110+x(dBm), unit = 1dB*/
u8 nhm_pwr_0p5; /*110+x/2(dBm), unit = 0.5dB*/
u8 ifs_clm_tx_ratio; /*percent*/
u8 ifs_clm_edcca_excl_cca_ratio; /*percent*/
u8 ifs_clm_cck_fa_ratio; /*percent*/
u8 ifs_clm_ofdm_fa_ratio; /*percent*/
u8 ifs_clm_cck_cca_excl_fa_ratio; /*percent*/
u8 ifs_clm_ofdm_cca_excl_fa_ratio; /*percent*/
u16 ifs_clm_cck_fa_permil; /*permil*/
u16 ifs_clm_ofdm_fa_permil; /*permil*/
u16 ifs_clm_total_ifs; /*cnt*/
u16 ifs_clm_his[BE_IFS_CLM_NUM]; /*cnt*/
u32 ifs_clm_ifs_avg[BE_IFS_CLM_NUM]; /*us*/
u32 ifs_clm_cca_avg[BE_IFS_CLM_NUM]; /*us*/
u8 edcca_clm_ratio; /*percent*/
};
struct ccx_para_info {
enum halbb_racing_lv rac_lv;
u16 mntr_time; /*0~2097ms*/
enum ccx_edcca_opt_sc_idx ccx_edcca_opt_sc_idx;
enum clm_application clm_app;
enum clm_opt_input clm_input_opt;
enum clm_opt_nav_en clm_nav_en;
enum clm_opt_rssi_th_en clm_rssi_th_en;
u8 clm_rssi_th;
enum nhm_application nhm_app;
u8 nhm_manual_th_ofst;
u8 nhm_manual_th0; /*dbg manual mode*/
enum nhm_opt_cca_all nhm_incld_cca; /*Include CCA*/
enum nhm_opt_nav_en nhm_nav_en;
enum nhm_opt_rssi_th_en nhm_rssi_th_en;
u8 nhm_rssi_th;
enum ifs_clm_application ifs_clm_app;
u32 ifs_clm_manual_th_times;
u32 ifs_clm_manual_th0;/*us*/
enum edcca_clm_application edcca_clm_app;
};
/*--------------------------[Prptotype]-------------------------------------*/
void halbb_env_mntr_get_bg_result(struct bb_info *bb,
struct env_mntr_rpt *bg_rpt,
enum phl_phy_idx phy_idx);
void halbb_env_mntr_get_bg_setting(struct bb_info *bb,
struct ccx_para_info *bg_para,
enum phl_phy_idx phy_idx);
u8 halbb_env_mntr_trigger(struct bb_info *bb, struct ccx_para_info *para,
struct env_trig_rpt *trig_rpt, enum phl_phy_idx phy_idx);
u8 halbb_env_mntr_result(struct bb_info *bb, struct env_mntr_rpt *rpt, enum phl_phy_idx phy_idx);
u8 halbb_env_mntr_get_802_11_k_rsni(struct bb_info *bb, s8 rcpi, s8 anpi);
#endif
3rd/devourer/hal/halbb/g6/vendor/halbb_ex.h
Vendored
+209
View File
@@ -0,0 +1,209 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_EX_H__
#define __HALBB_EX_H__
#include "halbb_ic_hw_info.h"
/*@--------------------------[Define] ---------------------------------------*/
#define HALBB_PAUSE_MAX_LENGTH 5
/*@--------------------------[Enum]------------------------------------------*/
enum halbb_pause_type {
HALBB_PAUSE = 1, /*Pause & Set new value*/
HALBB_PAUSE_NO_SET = 2, /*Pause & Stay in current value*/
HALBB_RESUME = 3,
HALBB_RESUME_NO_RECOVERY = 4,
};
enum halbb_pause_lv_type {
HALBB_PAUSE_RELEASE = -1,
HALBB_PAUSE_LV_0 = 0, /* @Low Priority function */
HALBB_PAUSE_LV_1 = 1, /* @Middle Priority function */
HALBB_PAUSE_LV_2 = 2, /* @High priority function (ex: Check hang function) */
HALBB_PAUSE_LV_3 = 3, /* @Debug function (the highest priority) */
HALBB_PAUSE_MAX_NUM = 4
};
enum halbb_pause_rpt {
PAUSE_FAIL = 0,
PAUSE_SUCCESS = 1
};
/*---[BB Components]---*/
enum habb_fun_t {
F_RA = 0,
F_FA_CNT = 1,
F_HW_CFG = 2,
F_DFS = 3,
F_EDCCA = 4,
F_ENV_MNTR = 5,
F_CFO_TRK = 6,
F_PWR_CTRL = 7,
F_RUA_TBL = 8,
F_AUTO_DBG = 9,
F_ANT_DIV = 10,
F_DIG = 11,
F_PATH_DIV = 12,
F_UL_TB_CTRL = 13,
F_DCR = 31,
F_DEFAULT = 0xff
};
enum bb_watchdog_mode_t {
BB_WATCHDOG_NORMAL = 0,
BB_WATCHDOG_LOW_IO = 1,
BB_WATCHDOG_NON_IO = 2,
};
enum halbb_diag_event_level {
HALBB_DIAG_EVT_LVL_FATAL = 0,
HALBB_DIAG_EVT_LVL_CRITICAL = 1,
HALBB_DIAG_EVT_LVL_ERROR = 2,
HALBB_DIAG_EVT_LVL_WARNING = 3,
HALBB_DIAG_EVT_LVL_INFO = 4,
HALBB_DIAG_EVT_LVL_DBG = 5
};
struct halbb_func_info {
char name[16];
u8 id;
};
static const struct halbb_func_info halbb_func_i[] = {
{"ra", F_RA}, /*@do not move this element to other position*/
{"fa_cnt", F_FA_CNT}, /*@do not move this element to other position*/
{"hw_cfg", F_HW_CFG},
{"dfs", F_DFS},
{"edcca", F_EDCCA},
{"env_mntr", F_ENV_MNTR},
{"cfo_trk", F_CFO_TRK},
{"pwr_ctrl", F_PWR_CTRL},
{"rua_tbl", F_RUA_TBL},
{"auto_dbg", F_AUTO_DBG},
{"ant_div", F_ANT_DIV},
{"dig", F_DIG},
{"path_div", F_PATH_DIV},
{"ul_tb", F_UL_TB_CTRL},
};
/*@=[HALBB supportability]=======================================*/
enum habb_supportability_t {
BB_RA = BIT(F_RA),
BB_FA_CNT = BIT(F_FA_CNT),
BB_HW_CFG = BIT(F_HW_CFG),
BB_DFS = BIT(F_DFS),
BB_EDCCA = BIT(F_EDCCA),
BB_ENVMNTR = BIT(F_ENV_MNTR),
BB_CFO_TRK = BIT(F_CFO_TRK),
BB_PWR_CTRL = BIT(F_PWR_CTRL),
BB_RUA_TBL = BIT(F_RUA_TBL),
BB_AUTO_DBG = BIT(F_AUTO_DBG),
BB_ANT_DIV = BIT(F_ANT_DIV),
BB_DIG = BIT(F_DIG),
BB_PATH_DIV = BIT(F_PATH_DIV),
BB_UL_TB_CTRL = BIT(F_UL_TB_CTRL),
BB_DCR = BIT(F_DCR)
};
/*@=[HALBB Debug Component]=====================================*/
enum halbb_dbg_comp_t {
/*=== [DM Part] ==========================*/
DBG_RA = BIT(F_RA),
DBG_FA_CNT = BIT(F_FA_CNT),
DBG_HW_CFG = BIT(F_HW_CFG),
DBG_DFS = BIT(F_DFS),
DBG_EDCCA = BIT(F_EDCCA),
DBG_ENV_MNTR = BIT(F_ENV_MNTR),
DBG_CFO_TRK = BIT(F_CFO_TRK),
DBG_PWR_CTRL = BIT(F_PWR_CTRL),
DBG_RUA_TBL = BIT(F_RUA_TBL),
DBG_AUTO_DBG = BIT(F_AUTO_DBG),
DBG_ANT_DIV = BIT(F_ANT_DIV),
DBG_DIG = BIT(F_DIG),
DBG_PATH_DIV = BIT(F_PATH_DIV),
DBG_UL_TB_CTRL = BIT(F_UL_TB_CTRL),
/*=== [Non-DM Part] ======================*/
DBG_BIT14 = BIT(14),
DBG_FW_DBG = BIT(15),
DBG_PHY_CONFIG_BE = BIT(16),
DBG_BIT17 = BIT(17),
DBG_SNIFFER = BIT(18),
DBG_CH_INFO = BIT(19),
DBG_PHY_STS = BIT(20),
DBG_CONNECT = BIT(21),
DBG_FW_INFO = BIT(22),
DBG_COMMON_FLOW = BIT(23),
DBG_IC_API = BIT(24),
DBG_DBG_API = BIT(25),
DBG_DBCC = BIT(26),
DBG_DM_SUMMARY = BIT(27),
DBG_PHY_CONFIG = BIT(28),
DBG_INIT = BIT(29),
DBG_CMN = BIT(30),
DBG_DCR = BIT(F_DCR)
};
/*@--------------------------[Structure]-------------------------------------*/
#if 0
/*For development use only, and will move to "struct rtw_rssi_info" in near furture*/
struct bb_rssi_info{
u8 rssi; /*avg RSSI among all RF path, dbm = RSSI - 110*/
u16 rssi_acc; /*U(16,4) version of rssi*/
u8 rssi_cck; /*instance value of CCK RSSI*/
u8 rssi_ofdm; /*instance value of OFDM RSSI*/
};
#endif
struct bb_sta_info {
u8 sta_status_tmp;
};
/*@--------------------------[Prptotype]-------------------------------------*/
struct bb_info;
bool halbb_sta_info_init(struct bb_info *bb,
struct rtw_phl_stainfo_t *phl_sta_info);
bool halbb_sta_info_deinit(struct bb_info *bb,
struct rtw_phl_stainfo_t *phl_sta_info);
bool halbb_sta_info_add_entry(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_info);
bool halbb_sta_info_delete_entry(struct bb_info *bb,
struct rtw_phl_stainfo_t *phl_sta_info);
void halbb_media_status_update(struct bb_info *bb,
struct rtw_phl_stainfo_t *phl_sta_info,
bool is_connected);
void halbb_watchdog_io_saving_en(struct bb_info *bb_0, bool en, enum phl_phy_idx phy_idx);
void halbb_watchdog_reset(struct bb_info *bb);
void halbb_watchdog(struct bb_info *bb, enum bb_watchdog_mode_t mode,
enum phl_phy_idx phy_idx);
u8 halbb_wifi_event_notify(struct bb_info *bb, enum phl_msg_evt_id event, enum phl_phy_idx phy_idx);
void halbb_bb_cmd_notify(struct bb_info *bb, void *bb_cmd, enum phl_phy_idx phy_idx);
u8 halbb_pause_func(struct bb_info *bb, enum habb_fun_t pause_func,
enum halbb_pause_type pause_type,
enum halbb_pause_lv_type lv,
u8 val_lehgth,
u32 *val_buf, enum phl_phy_idx phy_idx);
#endif
3rd/devourer/hal/halbb/g6/vendor/halbb_export_fun.h
Vendored
+80
View File
@@ -0,0 +1,80 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_EXPORT_FUN_H__
#define __HALBB_EXPORT_FUN_H__
#include "halbb_cfg_ic.h"
#include "halbb_ic_hw_info.h"
#include "halbb_hw_cfg_ex.h"
#include "halbb_init_ex.h"
#include "halbb_ex.h"
#include "halbb_dbg_cmd_ex.h"
#include "halbb_physts_ex.h"
#include "halbb_api_ex.h"
#include "halbb_api_be_ex.h"
#include "halbb_interface_ex.h"
#include "halbb_dfs_ex.h"
#include "halbb_dig_ex.h"
#include "halbb_mp_ex.h"
#include "halbb_outsrc_def.h"
#include "halbb_pmac_setting_ex.h"
#include "halbb_la_mode_ex.h"
#include "halbb_ra_ex.h"
#include "halbb_cmn_rpt_ex.h"
#include "halbb_ch_info_ex.h"
#include "halbb_math_lib_ex.h"
#include "halbb_edcca_ex.h"
#include "halbb_dbcc_ex.h"
#include "halbb_rua_tbl_ex.h"
#include "halbb_env_mntr_ex.h"
#include "halbb_pwr_ctrl_ex.h"
#include "halbb_bb_wrapper_outsrc.h"
#include "halbb_dyn_csi_rsp_ex.h"
#include "halbb_dbcc_ex.h"
#include "halbb_snif_ex.h"
#include "halbb_fwofld_ex.h"
#include "halbb_statistics_ex.h"
#include "halbb_ant_div_ex.h"
#include "halbb_dbg_cnsl_out_ex.h"
#include "halbb_dbg_ex.h"
#include "halbb_auto_dbg_ex.h"
#include "halbb_spatial_reuse_ex.h"
#ifdef BB_8852A_2_SUPPORT
#include "halbb_8852a_2/halbb_8852a_2_api_ex.h"
#endif
#ifdef BB_8852B_SUPPORT
#include "halbb_8852b/halbb_8852b_api_ex.h"
#endif
#ifdef BB_8852C_SUPPORT
#include "halbb_8852c/halbb_8852c_api_ex.h"
#include "halbb_8852c/halbb_8852c_dcra_ex.h"
#endif
#ifdef BB_8192XB_SUPPORT
#include "halbb_8192xb/halbb_8192xb_api_ex.h"
#endif
#ifdef HALBB_COMPILE_BE_SERIES
#include "bbmcu/bbmcu_export_fun.h"
#endif
#endif
3rd/devourer/hal/halbb/g6/vendor/halbb_features.h
Vendored
+221
View File
@@ -0,0 +1,221 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_FEATURES_H__
#define __HALBB_FEATURES_H__
#include "../../hal_headers_le.h"
#include "halbb_cfg_ic.h"
#include "halbb_platform.h"
#include "halbb_ic_hw_info.h"
/*[Control by Outer Driver]--------------------------------------------------*/
#if (defined(BB_8852D_SUPPORT))
#define HALBB_BAND_SWH_CR_SEQ_SUPPORT
#endif
#ifndef DRV_BB_TIMER_SUPPORT_DISABLE
#define HALBB_TIMER_SUPPORT
#endif
#ifndef DRV_BB_DBG_TRACE_DISABLE
#define HALBB_DBG_TRACE_SUPPORT
#endif
#ifndef DRV_BB_PHYSTS_PARSING_DISABLE
#define HALBB_PHYSTS_PARSING_SUPPORT
#ifndef DRV_BB_ANT_DIV_DISABLE
#define HALBB_ANT_DIV_SUPPORT
#endif
#ifdef CONFIG_PHL_SNIFFER_SUPPORT
#define HALBB_SNIF_SUPPORT
#endif
#ifndef DRV_BB_PATH_DIV_DISABLE
#define HALBB_PATH_DIV_SUPPORT
#endif
#ifndef DRV_BB_CFO_TRK_DISABLE
#define HALBB_CFO_TRK_SUPPORT
#define HALBB_CFO_DAMPING_CHK
//#define BB_DYN_CFO_TRK_LOP
#endif
/*[DTR]*/
#ifndef DRV_BB_DYN_DTR_DISABLE
#define HALBB_DYN_DTR_SUPPORT
//#define BB_DYN_DTR
#endif
#endif
#ifndef DRV_BB_ENV_MNTR_DISABLE
#define HALBB_ENV_MNTR_SUPPORT
#define CLM_SUPPORT
#define NHM_SUPPORT
#define IFS_CLM_SUPPORT
#define FAHM_SUPPORT
#define EDCCA_CLM_SUPPORT
#endif
#ifndef DRV_BB_STATISTICS_DISABLE
#define HALBB_STATISTICS_SUPPORT
#endif
#ifndef DRV_BB_RA_DISABLE
#define HALBB_RA_SUPPORT
#define HALBB_RA_FW_DBG_SUPPORT
#endif
#ifndef DRV_BB_ADPTVTY_DISABLE
#define HALBB_EDCCA_SUPPORT
#endif
#ifndef DRV_BB_DFS_DISABLE
#define HALBB_DFS_SUPPORT
#endif
#ifndef DRV_BB_DIG_DISABLE
#define HALBB_DIG_SUPPORT
#ifndef DRV_BB_TDMADIG_DISABLE
#if (HLABB_CODE_BASE_NUM >= 34) || (HLABB_CODE_BASE_NUM == 29) || (HLABB_CODE_BASE_NUM == 27) || (HLABB_CODE_BASE_NUM == 25)
#define HALBB_DIG_TDMA_SUPPORT
#endif
#endif
#define HALBB_DIG_DAMPING_CHK
#endif
#ifdef CONFIG_MCC_SUPPORT
#define HALBB_MCC_SUPPORT
#endif
#ifndef DRV_BB_LA_MODE_DISABLE
#define HALBB_LA_MODE_SUPPORT
#ifdef BB_1115_SUPPORT
#define HALBB_LA_320M_PATCH /*for RTL1115 320M 3-phase case only*/
#endif
#define BB_IC_LA_MODE_GEN2 (BB_IC_BE_1 | BB_IC_BE_2)
#if (defined(HALBB_COMPILE_BE1_SERIES)||defined(HALBB_COMPILE_BE2_SERIES))
#define HALBB_COMPILE_LA_MODE_GEN2
#endif
#endif
#ifndef DRV_BB_PSD_DISABLE
#define HALBB_PSD_SUPPORT
#endif
#ifndef DRV_BB_PWR_CTRL_DISABLE
#define HALBB_PWR_CTRL_SUPPORT
#endif
#ifndef DRV_BB_WRAP_DISABLE
#ifdef HALBB_COMPILE_BE_SERIES
#define HALBB_BB_WRAP_SUPPORT
#endif
#endif
#ifndef DRV_BB_SR_DISABLE
#if (HLABB_CODE_BASE_NUM == 29)
#define HALBB_SR_SUPPORT
#endif
#endif
#ifndef DRV_BB_RUA_DISABLE
#define HALBB_RUA_SUPPORT
#endif
#ifndef DRV_BB_PMAC_TX_DISABLE
#define HALBB_PMAC_TX_SUPPORT
#endif
#ifdef CONFIG_PHL_CHANNEL_INFO
#define HALBB_CH_INFO_SUPPORT
#ifndef DRV_BB_DYN_CSI_RSP_DISABLE
#define HALBB_DYN_CSI_RSP_SUPPORT
#endif
#endif
#ifndef DRV_BB_AUTO_DBG_DISABLE
#define HALBB_AUTO_DBG_SUPPORT
#ifndef DRV_BB_SELF_DIAG_DISABLE
#define HALBB_SELF_DIAG_SUPPORT
#endif
#endif
#ifdef CONFIG_PHL_DIAGNOSE
#define HALBB_DIAGNOSE_SUPPORT
#endif
#ifndef DRV_BB_DYN_L2H_DISABLE
#define HALBB_DYN_L2H_SUPPORT
#endif
#ifndef DRV_BB_PMAC_TX_SETTING_DISABLE
#define HALBB_PMAC_TX_SETTING_SUPPORT
#endif
/*[FW OFFLOAD]*/
#if ((defined(CONFIG_PHL_IO_OFLD) ||defined(CONFIG_FW_DBCC_OFLD_SUPPORT)) && defined(HALBB_COMPILE_IC_FWOFLD))
#define HALBB_FW_OFLD_SUPPORT
#if (defined(CONFIG_PHL_IO_OFLD))
#define HALBB_FW_NORMAL_OFLD_SUPPORT
#endif
#if (defined(CONFIG_FW_DBCC_OFLD_SUPPORT) || defined(HALBB_COMPILE_IC_DBCC_MLO))
#define HALBB_FW_DBCC_OFLD_SUPPORT
#endif
#endif
#ifdef CONFIG_PHL_BCNOFLD
#define HALBB_BCNOFLD_SUPPORT
#endif
/*[DBCC]*/
#if (defined(CONFIG_DBCC_SUPPORT) && defined(HALBB_COMPILE_IC_DBCC))
#define HALBB_DBCC_SUPPORT
#define HALBB_DBCC_DVLP_FLAG
#endif
#define HALBB_TDMA_CR_SUPPORT
/*[POP resolved hang]*/
#ifdef DRV_RESOLVED_POP_BY_BB
#define HALBB_RESOLVED_POP_BY_BB
#endif
#ifndef DRV_BB_ULOFDMA_CTRL_DISABLE
#define HALBB_UL_TB_CTRL_SUPPORT
#endif
/*[Shared crystal]*/
#ifdef DRV_BB_CFO_TRK_DISABLE_BY_SHARE_XTAL
#define HALBB_SHARE_XSTAL_SUPPORT
#endif
#define HALBB_DYN_1R_CCA_SUPPORT
#if 1//(defined(DRV_BB_CNSL_CMN_INFO) || !defined(HALBB_DBG_TRACE_SUPPORT))
#define HALBB_CNSL_CMN_INFO_SUPPORT
#endif
#ifdef DRV_BB_DCRA_EN
#define HALBB_DCRA_EN
#endif
#ifdef DRV_BB_INIT_FW_NHM_EN
#define HALBB_INIT_FW_NHM_EN
#endif
#ifdef CONFIG_24G_256QAM
#define HALBB_CONFIG_HT2VHT_SUPPORT
#endif
#ifndef DRV_BB_DV_PXP_DISABLE
#define HALBB_DV_PXP_DBG_SUPPORT
#endif
#endif
3rd/devourer/hal/halbb/g6/vendor/halbb_fwofld.h
Vendored
+74
View File
@@ -0,0 +1,74 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_FWOFLD_H__
#define __HALBB_FWOFLD_H__
/*@--------------------------[Define] ---------------------------------------*/
#define RF18REGMASK 0x30fff /* BW: bit10,11, Ch: bit17,16,9~0 */
/*@--------------------------[Enum]------------------------------------------*/
enum fw_ofld_type {
FW_OFLD_PHY_0_CR_INIT = 0,
FW_OFLD_DM_INIT = 1,
FW_OFLD_BB_API = 2,
FW_OFLD_PHY_1_CR_INIT = 8,
FW_OFLD_PHY_1_DM_INIT = 9,
FW_OFLD_DBCC_API = 10
};
/*@--------------------------[Structure]-------------------------------------*/
struct bb_info;
struct fw_cmd_info {
char name[16];
u16 id;
};
static const struct fw_cmd_info halbb_fw_ofld_info_i[] = {
{"phy0_cr_init",FW_OFLD_PHY_0_CR_INIT}, /*@do not move this element to other position*/
{"dm_init", FW_OFLD_DM_INIT},
{"bb_api", FW_OFLD_BB_API}, /*@do not move this element to other position*/
{"phy1_cr_init", FW_OFLD_PHY_1_CR_INIT},
{"phy1_dm_init", FW_OFLD_PHY_1_DM_INIT},
{"dbcc_cfg", FW_OFLD_DBCC_API}
};
/*@--------------------------[Prptotype]-------------------------------------*/
#ifdef HALBB_FW_OFLD_SUPPORT
void halbb_fwofld_bitmap_en(struct bb_info *bb, bool en, enum fw_ofld_type app);
void halbb_fwofld_bitmap_init(struct bb_info *bb);
bool halbb_fw_set_reg(struct bb_info *bb, u32 addr, u32 mask, u32 val, u8 lc);
bool halbb_fw_set_reg_cmn(struct bb_info *bb, u32 addr, u32 mask, u32 val,
enum phl_phy_idx phy_idx, u8 lc);
bool halbb_fwcfg_bb_phy_8852a_2(struct bb_info *bb, u32 addr, u32 data,
enum phl_phy_idx phy_idx);
bool halbb_fwofld_bw_ch_8852a_2(struct bb_info *bb, u8 pri_ch, u8 central_ch,
enum channel_width bw, enum phl_phy_idx phy_idx);
void halbb_fwofld_set_pmac_tx_8852a_2(struct bb_info *bb,
struct halbb_pmac_info *tx_info,
enum phl_phy_idx phy_idx);
void halbb_fwofld_init(struct bb_info *bb);
void halbb_fw_ofld_dbg(struct bb_info *bb, char input[][16], u32 *_used,
char *output, u32 *_out_len);
#endif
#endif
3rd/devourer/hal/halbb/g6/vendor/halbb_fwofld_ex.h
Vendored
+44
View File
@@ -0,0 +1,44 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2020 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBB_FWOFLD_EX_H__
#define __HALBB_FWOFLD_EX_H__
/*@--------------------------[Define] ---------------------------------------*/
/*@--------------------------[Enum]------------------------------------------*/
/*@--------------------------[Structure]-------------------------------------*/
struct bb_info;
/*@--------------------------[Prptotype]-------------------------------------*/
bool halbb_check_fw_ofld(struct bb_info *bb);
bool halbb_fw_set_reg(struct bb_info *bb, u32 addr, u32 mask, u32 val, u8 lc);
bool halbb_fw_delay(struct bb_info *bb, u32 val);
void halbb_fwofld_cfgcr_start(struct bb_info *bb);
void halbb_fwofld_cfgcr_end(struct bb_info *bb);
#endif

Some files were not shown because too many files have changed in this diff Show More