first
This commit is contained in:
@@ -0,0 +1,733 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __INC_HAL8812PHYREG_H__
|
||||
#define __INC_HAL8812PHYREG_H__
|
||||
/*--------------------------Define Parameters-------------------------------*/
|
||||
/*
|
||||
* BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
|
||||
* 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
|
||||
* 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
|
||||
* 3. RF register 0x00-2E
|
||||
* 4. Bit Mask for BB/RF register
|
||||
* 5. Other defintion for BB/RF R/W
|
||||
* */
|
||||
|
||||
|
||||
/* BB Register Definition */
|
||||
|
||||
#define rCCAonSec_Jaguar 0x838
|
||||
#define rPwed_TH_Jaguar 0x830
|
||||
|
||||
/* BW and sideband setting */
|
||||
#define rBWIndication_Jaguar 0x834
|
||||
#define rL1PeakTH_Jaguar 0x848
|
||||
#define rFPGA0_XA_LSSIReadBack 0x8a0 /*Tranceiver LSSI Readback*/
|
||||
#define rRFMOD_Jaguar 0x8ac /* RF mode */
|
||||
#define rADC_Buf_Clk_Jaguar 0x8c4
|
||||
#define rRFECTRL_Jaguar 0x900
|
||||
#define bRFMOD_Jaguar 0xc3
|
||||
#define rCCK_System_Jaguar 0xa00 /* for cck sideband */
|
||||
#define bCCK_System_Jaguar 0x10
|
||||
|
||||
/* Block & Path enable */
|
||||
#define rOFDMCCKEN_Jaguar 0x808 /* OFDM/CCK block enable */
|
||||
#define bOFDMEN_Jaguar 0x20000000
|
||||
#define bCCKEN_Jaguar 0x10000000
|
||||
#define rRxPath_Jaguar 0x808 /* Rx antenna */
|
||||
#define bRxPath_Jaguar 0xff
|
||||
#define rTxPath_Jaguar 0x80c /* Tx antenna */
|
||||
#define bTxPath_Jaguar 0x0fffffff
|
||||
#define rCCK_RX_Jaguar 0xa04 /* for cck rx path selection */
|
||||
#define bCCK_RX_Jaguar 0x0c000000
|
||||
#define rVhtlen_Use_Lsig_Jaguar 0x8c3 /* Use LSIG for VHT length */
|
||||
|
||||
/* RF read/write-related */
|
||||
#define rHSSIRead_Jaguar 0x8b0 /* RF read addr */
|
||||
#define bHSSIRead_addr_Jaguar 0xff
|
||||
#define bHSSIRead_trigger_Jaguar 0x100
|
||||
#define rA_PIRead_Jaguar 0xd04 /* RF readback with PI */
|
||||
#define rB_PIRead_Jaguar 0xd44 /* RF readback with PI */
|
||||
#define rA_SIRead_Jaguar 0xd08 /* RF readback with SI */
|
||||
#define rB_SIRead_Jaguar 0xd48 /* RF readback with SI */
|
||||
#define rRead_data_Jaguar 0xfffff
|
||||
#define rA_LSSIWrite_Jaguar 0xc90 /* RF write addr */
|
||||
#define rB_LSSIWrite_Jaguar 0xe90 /* RF write addr */
|
||||
#define bLSSIWrite_data_Jaguar 0x000fffff
|
||||
#define bLSSIWrite_addr_Jaguar 0x0ff00000
|
||||
|
||||
|
||||
|
||||
/* YN: mask the following register definition temporarily */
|
||||
#define rFPGA0_XA_RFInterfaceOE 0x860 /* RF Channel switch */
|
||||
#define rFPGA0_XB_RFInterfaceOE 0x864
|
||||
|
||||
#define rFPGA0_XAB_RFInterfaceSW 0x870 /* RF Interface Software Control */
|
||||
#define rFPGA0_XCD_RFInterfaceSW 0x874
|
||||
|
||||
/* #define rFPGA0_XAB_RFParameter 0x878 */ /* RF Parameter
|
||||
* #define rFPGA0_XCD_RFParameter 0x87c */
|
||||
|
||||
/* #define rFPGA0_AnalogParameter1 0x880 */ /* Crystal cap setting RF-R/W protection for parameter4??
|
||||
* #define rFPGA0_AnalogParameter2 0x884
|
||||
* #define rFPGA0_AnalogParameter3 0x888
|
||||
* #define rFPGA0_AdDaClockEn 0x888 */ /* enable ad/da clock1 for dual-phy
|
||||
* #define rFPGA0_AnalogParameter4 0x88c */
|
||||
|
||||
|
||||
/* CCK TX scaling */
|
||||
#define rCCK_TxFilter1_Jaguar 0xa20
|
||||
#define bCCK_TxFilter1_C0_Jaguar 0x00ff0000
|
||||
#define bCCK_TxFilter1_C1_Jaguar 0xff000000
|
||||
#define rCCK_TxFilter2_Jaguar 0xa24
|
||||
#define bCCK_TxFilter2_C2_Jaguar 0x000000ff
|
||||
#define bCCK_TxFilter2_C3_Jaguar 0x0000ff00
|
||||
#define bCCK_TxFilter2_C4_Jaguar 0x00ff0000
|
||||
#define bCCK_TxFilter2_C5_Jaguar 0xff000000
|
||||
#define rCCK_TxFilter3_Jaguar 0xa28
|
||||
#define bCCK_TxFilter3_C6_Jaguar 0x000000ff
|
||||
#define bCCK_TxFilter3_C7_Jaguar 0x0000ff00
|
||||
|
||||
|
||||
/* YN: mask the following register definition temporarily
|
||||
* #define rPdp_AntA 0xb00
|
||||
* #define rPdp_AntA_4 0xb04
|
||||
* #define rConfig_Pmpd_AntA 0xb28
|
||||
* #define rConfig_AntA 0xb68
|
||||
* #define rConfig_AntB 0xb6c
|
||||
* #define rPdp_AntB 0xb70
|
||||
* #define rPdp_AntB_4 0xb74
|
||||
* #define rConfig_Pmpd_AntB 0xb98
|
||||
* #define rAPK 0xbd8 */
|
||||
|
||||
/* RXIQC */
|
||||
#define rA_RxIQC_AB_Jaguar 0xc10 /* RxIQ imblance matrix coeff. A & B */
|
||||
#define rA_RxIQC_CD_Jaguar 0xc14 /* RxIQ imblance matrix coeff. C & D */
|
||||
#define rA_TxScale_Jaguar 0xc1c /* Pah_A TX scaling factor */
|
||||
#define rB_TxScale_Jaguar 0xe1c /* Path_B TX scaling factor */
|
||||
#define rB_RxIQC_AB_Jaguar 0xe10 /* RxIQ imblance matrix coeff. A & B */
|
||||
#define rB_RxIQC_CD_Jaguar 0xe14 /* RxIQ imblance matrix coeff. C & D */
|
||||
#define b_RxIQC_AC_Jaguar 0x02ff /* bit mask for IQC matrix element A & C */
|
||||
#define b_RxIQC_BD_Jaguar 0x02ff0000 /* bit mask for IQC matrix element A & C */
|
||||
|
||||
|
||||
/* DIG-related */
|
||||
#define rA_IGI_Jaguar 0xc50 /* Initial Gain for path-A */
|
||||
#define rB_IGI_Jaguar 0xe50 /* Initial Gain for path-B */
|
||||
#define rOFDM_FalseAlarm1_Jaguar 0xf48 /* counter for break */
|
||||
#define rOFDM_FalseAlarm2_Jaguar 0xf4c /* counter for spoofing */
|
||||
#define rCCK_FalseAlarm_Jaguar 0xa5c /* counter for cck false alarm */
|
||||
#define b_FalseAlarm_Jaguar 0xffff
|
||||
#define rCCK_CCA_Jaguar 0xa08 /* cca threshold */
|
||||
#define bCCK_CCA_Jaguar 0x00ff0000
|
||||
|
||||
/* Tx Power Ttraining-related */
|
||||
#define rA_TxPwrTraing_Jaguar 0xc54
|
||||
#define rB_TxPwrTraing_Jaguar 0xe54
|
||||
|
||||
/* Report-related */
|
||||
#define rOFDM_ShortCFOAB_Jaguar 0xf60
|
||||
#define rOFDM_LongCFOAB_Jaguar 0xf64
|
||||
#define rOFDM_EndCFOAB_Jaguar 0xf70
|
||||
#define rOFDM_AGCReport_Jaguar 0xf84
|
||||
#define rOFDM_RxSNR_Jaguar 0xf88
|
||||
#define rOFDM_RxEVMCSI_Jaguar 0xf8c
|
||||
#define rOFDM_SIGReport_Jaguar 0xf90
|
||||
|
||||
/* Misc functions */
|
||||
#define rEDCCA_Jaguar 0x8a4 /* EDCCA */
|
||||
#define bEDCCA_Jaguar 0xffff
|
||||
#define rAGC_table_Jaguar 0x82c /* AGC tabel select */
|
||||
#define bAGC_table_Jaguar 0x3
|
||||
#define b_sel5g_Jaguar 0x1000 /* sel5g */
|
||||
#define b_LNA_sw_Jaguar 0x8000 /* HW/WS control for LNA */
|
||||
#define rFc_area_Jaguar 0x860 /* fc_area */
|
||||
#define bFc_area_Jaguar 0x1ffe000
|
||||
#define rSingleTone_ContTx_Jaguar 0x914
|
||||
|
||||
/* RFE */
|
||||
#define rA_RFE_Pinmux_Jaguar 0xcb0 /* Path_A RFE cotrol pinmux */
|
||||
#define rB_RFE_Pinmux_Jaguar 0xeb0 /* Path_B RFE control pinmux */
|
||||
#define rA_RFE_Inv_Jaguar 0xcb4 /* Path_A RFE cotrol */
|
||||
#define rB_RFE_Inv_Jaguar 0xeb4 /* Path_B RFE control */
|
||||
#define rA_RFE_Jaguar 0xcb8 /* Path_A RFE cotrol */
|
||||
#define rB_RFE_Jaguar 0xeb8 /* Path_B RFE control */
|
||||
#define r_ANTSEL_SW_Jaguar 0x900 /* ANTSEL SW Control */
|
||||
#define bMask_RFEInv_Jaguar 0x3ff00000
|
||||
#define bMask_AntselPathFollow_Jaguar 0x00030000
|
||||
|
||||
/* TX AGC */
|
||||
#define rTxAGC_A_CCK11_CCK1_JAguar 0xc20
|
||||
#define rTxAGC_A_Ofdm18_Ofdm6_JAguar 0xc24
|
||||
#define rTxAGC_A_Ofdm54_Ofdm24_JAguar 0xc28
|
||||
#define rTxAGC_A_MCS3_MCS0_JAguar 0xc2c
|
||||
#define rTxAGC_A_MCS7_MCS4_JAguar 0xc30
|
||||
#define rTxAGC_A_MCS11_MCS8_JAguar 0xc34
|
||||
#define rTxAGC_A_MCS15_MCS12_JAguar 0xc38
|
||||
#define rTxAGC_A_Nss1Index3_Nss1Index0_JAguar 0xc3c
|
||||
#define rTxAGC_A_Nss1Index7_Nss1Index4_JAguar 0xc40
|
||||
#define rTxAGC_A_Nss2Index1_Nss1Index8_JAguar 0xc44
|
||||
#define rTxAGC_A_Nss2Index5_Nss2Index2_JAguar 0xc48
|
||||
#define rTxAGC_A_Nss2Index9_Nss2Index6_JAguar 0xc4c
|
||||
#define rTxAGC_B_CCK11_CCK1_JAguar 0xe20
|
||||
#define rTxAGC_B_Ofdm18_Ofdm6_JAguar 0xe24
|
||||
#define rTxAGC_B_Ofdm54_Ofdm24_JAguar 0xe28
|
||||
#define rTxAGC_B_MCS3_MCS0_JAguar 0xe2c
|
||||
#define rTxAGC_B_MCS7_MCS4_JAguar 0xe30
|
||||
#define rTxAGC_B_MCS11_MCS8_JAguar 0xe34
|
||||
#define rTxAGC_B_MCS15_MCS12_JAguar 0xe38
|
||||
#define rTxAGC_B_Nss1Index3_Nss1Index0_JAguar 0xe3c
|
||||
#define rTxAGC_B_Nss1Index7_Nss1Index4_JAguar 0xe40
|
||||
#define rTxAGC_B_Nss2Index1_Nss1Index8_JAguar 0xe44
|
||||
#define rTxAGC_B_Nss2Index5_Nss2Index2_JAguar 0xe48
|
||||
#define rTxAGC_B_Nss2Index9_Nss2Index6_JAguar 0xe4c
|
||||
#define bTxAGC_byte0_Jaguar 0xff
|
||||
#define bTxAGC_byte1_Jaguar 0xff00
|
||||
#define bTxAGC_byte2_Jaguar 0xff0000
|
||||
#define bTxAGC_byte3_Jaguar 0xff000000
|
||||
|
||||
/* IQK YN: temporaily mask this part
|
||||
* #define rFPGA0_IQK 0xe28
|
||||
* #define rTx_IQK_Tone_A 0xe30
|
||||
* #define rRx_IQK_Tone_A 0xe34
|
||||
* #define rTx_IQK_PI_A 0xe38
|
||||
* #define rRx_IQK_PI_A 0xe3c */
|
||||
|
||||
/* #define rTx_IQK 0xe40 */
|
||||
/* #define rRx_IQK 0xe44 */
|
||||
/* #define rIQK_AGC_Pts 0xe48 */
|
||||
/* #define rIQK_AGC_Rsp 0xe4c */
|
||||
/* #define rTx_IQK_Tone_B 0xe50 */
|
||||
/* #define rRx_IQK_Tone_B 0xe54 */
|
||||
/* #define rTx_IQK_PI_B 0xe58 */
|
||||
/* #define rRx_IQK_PI_B 0xe5c */
|
||||
/* #define rIQK_AGC_Cont 0xe60 */
|
||||
|
||||
|
||||
/* AFE-related */
|
||||
#define rA_AFEPwr1_Jaguar 0xc60 /* dynamic AFE power control */
|
||||
#define rA_AFEPwr2_Jaguar 0xc64 /* dynamic AFE power control */
|
||||
#define rA_Rx_WaitCCA_Tx_CCKRFON_Jaguar 0xc68
|
||||
#define rA_Tx_CCKBBON_OFDMRFON_Jaguar 0xc6c
|
||||
#define rA_Tx_OFDMBBON_Tx2Rx_Jaguar 0xc70
|
||||
#define rA_Tx2Tx_RXCCK_Jaguar 0xc74
|
||||
#define rA_Rx_OFDM_WaitRIFS_Jaguar 0xc78
|
||||
#define rA_Rx2Rx_BT_Jaguar 0xc7c
|
||||
#define rA_sleep_nav_Jaguar 0xc80
|
||||
#define rA_pmpd_Jaguar 0xc84
|
||||
#define rB_AFEPwr1_Jaguar 0xe60 /* dynamic AFE power control */
|
||||
#define rB_AFEPwr2_Jaguar 0xe64 /* dynamic AFE power control */
|
||||
#define rB_Rx_WaitCCA_Tx_CCKRFON_Jaguar 0xe68
|
||||
#define rB_Tx_CCKBBON_OFDMRFON_Jaguar 0xe6c
|
||||
#define rB_Tx_OFDMBBON_Tx2Rx_Jaguar 0xe70
|
||||
#define rB_Tx2Tx_RXCCK_Jaguar 0xe74
|
||||
#define rB_Rx_OFDM_WaitRIFS_Jaguar 0xe78
|
||||
#define rB_Rx2Rx_BT_Jaguar 0xe7c
|
||||
#define rB_sleep_nav_Jaguar 0xe80
|
||||
#define rB_pmpd_Jaguar 0xe84
|
||||
|
||||
|
||||
/* YN: mask these registers temporaily
|
||||
* #define rTx_Power_Before_IQK_A 0xe94
|
||||
* #define rTx_Power_After_IQK_A 0xe9c */
|
||||
|
||||
/* #define rRx_Power_Before_IQK_A 0xea0 */
|
||||
/* #define rRx_Power_Before_IQK_A_2 0xea4 */
|
||||
/* #define rRx_Power_After_IQK_A 0xea8 */
|
||||
/* #define rRx_Power_After_IQK_A_2 0xeac */
|
||||
|
||||
/* #define rTx_Power_Before_IQK_B 0xeb4 */
|
||||
/* #define rTx_Power_After_IQK_B 0xebc */
|
||||
|
||||
/* #define rRx_Power_Before_IQK_B 0xec0 */
|
||||
/* #define rRx_Power_Before_IQK_B_2 0xec4 */
|
||||
/* #define rRx_Power_After_IQK_B 0xec8 */
|
||||
/* #define rRx_Power_After_IQK_B_2 0xecc */
|
||||
|
||||
|
||||
/* RSSI Dump */
|
||||
#define rA_RSSIDump_Jaguar 0xBF0
|
||||
#define rB_RSSIDump_Jaguar 0xBF1
|
||||
#define rS1_RXevmDump_Jaguar 0xBF4
|
||||
#define rS2_RXevmDump_Jaguar 0xBF5
|
||||
#define rA_RXsnrDump_Jaguar 0xBF6
|
||||
#define rB_RXsnrDump_Jaguar 0xBF7
|
||||
#define rA_CfoShortDump_Jaguar 0xBF8
|
||||
#define rB_CfoShortDump_Jaguar 0xBFA
|
||||
#define rA_CfoLongDump_Jaguar 0xBEC
|
||||
#define rB_CfoLongDump_Jaguar 0xBEE
|
||||
|
||||
|
||||
/* RF Register
|
||||
* */
|
||||
#define RF_AC_Jaguar 0x00 /* */
|
||||
#define RF_RF_Top_Jaguar 0x07 /* */
|
||||
#define RF_TXLOK_Jaguar 0x08 /* */
|
||||
#define RF_TXAPK_Jaguar 0x0B
|
||||
#define RF_CHNLBW_Jaguar 0x18 /* RF channel and BW switch */
|
||||
#define RF_RCK1_Jaguar 0x1c /* */
|
||||
#define RF_RCK2_Jaguar 0x1d
|
||||
#define RF_RCK3_Jaguar 0x1e
|
||||
#define RF_ModeTableAddr 0x30
|
||||
#define RF_ModeTableData0 0x31
|
||||
#define RF_ModeTableData1 0x32
|
||||
#define RF_TxLCTank_Jaguar 0x54
|
||||
#define RF_APK_Jaguar 0x63
|
||||
#define RF_LCK 0xB4
|
||||
#define RF_WeLut_Jaguar 0xEF
|
||||
|
||||
#define bRF_CHNLBW_MOD_AG_Jaguar 0x70300
|
||||
#define bRF_CHNLBW_BW 0xc00
|
||||
|
||||
|
||||
/*
|
||||
* RL6052 Register definition
|
||||
* */
|
||||
#define RF_AC 0x00 /* */
|
||||
#define RF_IPA_A 0x0C /* */
|
||||
#define RF_TXBIAS_A 0x0D
|
||||
#define RF_BS_PA_APSET_G9_G11 0x0E
|
||||
#define RF_MODE1 0x10 /* */
|
||||
#define RF_MODE2 0x11 /* */
|
||||
#define RF_CHNLBW 0x18 /* RF channel and BW switch */
|
||||
#define RF_RCK_OS 0x30 /* RF TX PA control */
|
||||
#define RF_TXPA_G1 0x31 /* RF TX PA control */
|
||||
#define RF_TXPA_G2 0x32 /* RF TX PA control */
|
||||
#define RF_TXPA_G3 0x33 /* RF TX PA control */
|
||||
#define RF_0x52 0x52
|
||||
#define RF_WE_LUT 0xEF
|
||||
|
||||
#define RF_TX_GAIN_OFFSET_8812A(_val) ((abs((_val)) << 1) | (((_val) > 0) ? BIT0 : 0))
|
||||
#define RF_TX_GAIN_OFFSET_8821A(_val) ((abs((_val)) << 1) | (((_val) > 0) ? BIT0 : 0))
|
||||
|
||||
/*
|
||||
* Bit Mask
|
||||
*
|
||||
* 1. Page1(0x100) */
|
||||
#define bBBResetB 0x100 /* Useless now? */
|
||||
#define bGlobalResetB 0x200
|
||||
#define bOFDMTxStart 0x4
|
||||
#define bCCKTxStart 0x8
|
||||
#define bCRC32Debug 0x100
|
||||
#define bPMACLoopback 0x10
|
||||
#define bTxLSIG 0xffffff
|
||||
#define bOFDMTxRate 0xf
|
||||
#define bOFDMTxReserved 0x10
|
||||
#define bOFDMTxLength 0x1ffe0
|
||||
#define bOFDMTxParity 0x20000
|
||||
#define bTxHTSIG1 0xffffff
|
||||
#define bTxHTMCSRate 0x7f
|
||||
#define bTxHTBW 0x80
|
||||
#define bTxHTLength 0xffff00
|
||||
#define bTxHTSIG2 0xffffff
|
||||
#define bTxHTSmoothing 0x1
|
||||
#define bTxHTSounding 0x2
|
||||
#define bTxHTReserved 0x4
|
||||
#define bTxHTAggreation 0x8
|
||||
#define bTxHTSTBC 0x30
|
||||
#define bTxHTAdvanceCoding 0x40
|
||||
#define bTxHTShortGI 0x80
|
||||
#define bTxHTNumberHT_LTF 0x300
|
||||
#define bTxHTCRC8 0x3fc00
|
||||
#define bCounterReset 0x10000
|
||||
#define bNumOfOFDMTx 0xffff
|
||||
#define bNumOfCCKTx 0xffff0000
|
||||
#define bTxIdleInterval 0xffff
|
||||
#define bOFDMService 0xffff0000
|
||||
#define bTxMACHeader 0xffffffff
|
||||
#define bTxDataInit 0xff
|
||||
#define bTxHTMode 0x100
|
||||
#define bTxDataType 0x30000
|
||||
#define bTxRandomSeed 0xffffffff
|
||||
#define bCCKTxPreamble 0x1
|
||||
#define bCCKTxSFD 0xffff0000
|
||||
#define bCCKTxSIG 0xff
|
||||
#define bCCKTxService 0xff00
|
||||
#define bCCKLengthExt 0x8000
|
||||
#define bCCKTxLength 0xffff0000
|
||||
#define bCCKTxCRC16 0xffff
|
||||
#define bCCKTxStatus 0x1
|
||||
#define bOFDMTxStatus 0x2
|
||||
|
||||
|
||||
/*
|
||||
* 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
|
||||
* 1. Page1(0x100)
|
||||
* */
|
||||
#define rPMAC_Reset 0x100
|
||||
#define rPMAC_TxStart 0x104
|
||||
#define rPMAC_TxLegacySIG 0x108
|
||||
#define rPMAC_TxHTSIG1 0x10c
|
||||
#define rPMAC_TxHTSIG2 0x110
|
||||
#define rPMAC_PHYDebug 0x114
|
||||
#define rPMAC_TxPacketNum 0x118
|
||||
#define rPMAC_TxIdle 0x11c
|
||||
#define rPMAC_TxMACHeader0 0x120
|
||||
#define rPMAC_TxMACHeader1 0x124
|
||||
#define rPMAC_TxMACHeader2 0x128
|
||||
#define rPMAC_TxMACHeader3 0x12c
|
||||
#define rPMAC_TxMACHeader4 0x130
|
||||
#define rPMAC_TxMACHeader5 0x134
|
||||
#define rPMAC_TxDataType 0x138
|
||||
#define rPMAC_TxRandomSeed 0x13c
|
||||
#define rPMAC_CCKPLCPPreamble 0x140
|
||||
#define rPMAC_CCKPLCPHeader 0x144
|
||||
#define rPMAC_CCKCRC16 0x148
|
||||
#define rPMAC_OFDMRxCRC32OK 0x170
|
||||
#define rPMAC_OFDMRxCRC32Er 0x174
|
||||
#define rPMAC_OFDMRxParityEr 0x178
|
||||
#define rPMAC_OFDMRxCRC8Er 0x17c
|
||||
#define rPMAC_CCKCRxRC16Er 0x180
|
||||
#define rPMAC_CCKCRxRC32Er 0x184
|
||||
#define rPMAC_CCKCRxRC32OK 0x188
|
||||
#define rPMAC_TxStatus 0x18c
|
||||
|
||||
/*
|
||||
* 3. Page8(0x800)
|
||||
* */
|
||||
#define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC */ /* RF BW Setting?? */
|
||||
|
||||
#define rFPGA0_TxInfo 0x804 /* Status report?? */
|
||||
#define rFPGA0_PSDFunction 0x808
|
||||
#define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */
|
||||
|
||||
#define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */
|
||||
#define rFPGA0_XA_HSSIParameter2 0x824
|
||||
#define rFPGA0_XB_HSSIParameter1 0x828
|
||||
#define rFPGA0_XB_HSSIParameter2 0x82c
|
||||
|
||||
#define rFPGA0_XAB_SwitchControl 0x858 /* RF Channel switch */
|
||||
#define rFPGA0_XCD_SwitchControl 0x85c
|
||||
|
||||
#define rFPGA0_XAB_RFParameter 0x878 /* RF Parameter */
|
||||
#define rFPGA0_XCD_RFParameter 0x87c
|
||||
|
||||
#define rFPGA0_AnalogParameter1 0x880 /* Crystal cap setting RF-R/W protection for parameter4?? */
|
||||
#define rFPGA0_AnalogParameter2 0x884
|
||||
#define rFPGA0_AnalogParameter3 0x888
|
||||
#define rFPGA0_AdDaClockEn 0x888 /* enable ad/da clock1 for dual-phy */
|
||||
#define rFPGA0_AnalogParameter4 0x88c
|
||||
#define rFPGA0_XB_LSSIReadBack 0x8a4
|
||||
#define rFPGA0_XCD_RFPara 0x8b4
|
||||
|
||||
/*
|
||||
* 4. Page9(0x900)
|
||||
* */
|
||||
#define rFPGA1_RFMOD 0x900 /* RF mode & OFDM TxSC */ /* RF BW Setting?? */
|
||||
|
||||
#define rFPGA1_TxBlock 0x904 /* Useless now */
|
||||
#define rFPGA1_DebugSelect 0x908 /* Useless now */
|
||||
#define rFPGA1_TxInfo 0x90c /* Useless now */ /* Status report?? */
|
||||
|
||||
/*
|
||||
* PageA(0xA00)
|
||||
* */
|
||||
#define rCCK0_System 0xa00
|
||||
#define rCCK0_AFESetting 0xa04 /* Disable init gain now */ /* Select RX path by RSSI */
|
||||
#define rCCK0_DSPParameter2 0xa1c /* SQ threshold */
|
||||
#define rCCK0_TxFilter1 0xa20
|
||||
#define rCCK0_TxFilter2 0xa24
|
||||
#define rCCK0_DebugPort 0xa28 /* debug port and Tx filter3 */
|
||||
#define rCCK0_FalseAlarmReport 0xa2c /* 0xa2d useless now 0xa30-a4f channel report */
|
||||
|
||||
/*
|
||||
* PageB(0xB00)
|
||||
* */
|
||||
#define rPdp_AntA 0xb00
|
||||
#define rPdp_AntA_4 0xb04
|
||||
#define rConfig_Pmpd_AntA 0xb28
|
||||
#define rConfig_AntA 0xb68
|
||||
#define rConfig_AntB 0xb6c
|
||||
#define rPdp_AntB 0xb70
|
||||
#define rPdp_AntB_4 0xb74
|
||||
#define rConfig_Pmpd_AntB 0xb98
|
||||
#define rAPK 0xbd8
|
||||
|
||||
/*
|
||||
* 6. PageC(0xC00)
|
||||
* */
|
||||
#define rOFDM0_LSTF 0xc00
|
||||
|
||||
#define rOFDM0_TRxPathEnable 0xc04
|
||||
#define rOFDM0_TRMuxPar 0xc08
|
||||
#define rOFDM0_TRSWIsolation 0xc0c
|
||||
|
||||
#define rOFDM0_XARxAFE 0xc10 /* RxIQ DC offset, Rx digital filter, DC notch filter */
|
||||
#define rOFDM0_XARxIQImbalance 0xc14 /* RxIQ imblance matrix */
|
||||
#define rOFDM0_XBRxAFE 0xc18
|
||||
#define rOFDM0_XBRxIQImbalance 0xc1c
|
||||
#define rOFDM0_XCRxAFE 0xc20
|
||||
#define rOFDM0_XCRxIQImbalance 0xc24
|
||||
#define rOFDM0_XDRxAFE 0xc28
|
||||
#define rOFDM0_XDRxIQImbalance 0xc2c
|
||||
|
||||
#define rOFDM0_RxDetector1 0xc30 /* PD, BW & SBD */ /* DM tune init gain */
|
||||
#define rOFDM0_RxDetector2 0xc34 /* SBD & Fame Sync. */
|
||||
#define rOFDM0_RxDetector3 0xc38 /* Frame Sync. */
|
||||
#define rOFDM0_RxDetector4 0xc3c /* PD, SBD, Frame Sync & Short-GI */
|
||||
|
||||
#define rOFDM0_RxDSP 0xc40 /* Rx Sync Path */
|
||||
#define rOFDM0_CFOandDAGC 0xc44 /* CFO & DAGC */
|
||||
#define rOFDM0_CCADropThreshold 0xc48 /* CCA Drop threshold */
|
||||
#define rOFDM0_ECCAThreshold 0xc4c /* energy CCA */
|
||||
|
||||
#define rOFDM0_XAAGCCore1 0xc50 /* DIG */
|
||||
#define rOFDM0_XAAGCCore2 0xc54
|
||||
#define rOFDM0_XBAGCCore1 0xc58
|
||||
#define rOFDM0_XBAGCCore2 0xc5c
|
||||
#define rOFDM0_XCAGCCore1 0xc60
|
||||
#define rOFDM0_XCAGCCore2 0xc64
|
||||
#define rOFDM0_XDAGCCore1 0xc68
|
||||
#define rOFDM0_XDAGCCore2 0xc6c
|
||||
|
||||
#define rOFDM0_AGCParameter1 0xc70
|
||||
#define rOFDM0_AGCParameter2 0xc74
|
||||
#define rOFDM0_AGCRSSITable 0xc78
|
||||
#define rOFDM0_HTSTFAGC 0xc7c
|
||||
|
||||
#define rOFDM0_XATxIQImbalance 0xc80 /* TX PWR TRACK and DIG */
|
||||
#define rOFDM0_XATxAFE 0xc84
|
||||
#define rOFDM0_XBTxIQImbalance 0xc88
|
||||
#define rOFDM0_XBTxAFE 0xc8c
|
||||
#define rOFDM0_XCTxIQImbalance 0xc90
|
||||
#define rOFDM0_XCTxAFE 0xc94
|
||||
#define rOFDM0_XDTxIQImbalance 0xc98
|
||||
#define rOFDM0_XDTxAFE 0xc9c
|
||||
|
||||
#define rOFDM0_RxIQExtAnta 0xca0
|
||||
#define rOFDM0_TxCoeff1 0xca4
|
||||
#define rOFDM0_TxCoeff2 0xca8
|
||||
#define rOFDM0_TxCoeff3 0xcac
|
||||
#define rOFDM0_TxCoeff4 0xcb0
|
||||
#define rOFDM0_TxCoeff5 0xcb4
|
||||
#define rOFDM0_TxCoeff6 0xcb8
|
||||
#define rOFDM0_RxHPParameter 0xce0
|
||||
#define rOFDM0_TxPseudoNoiseWgt 0xce4
|
||||
#define rOFDM0_FrameSync 0xcf0
|
||||
#define rOFDM0_DFSReport 0xcf4
|
||||
|
||||
/*
|
||||
* 7. PageD(0xD00)
|
||||
* */
|
||||
#define rOFDM1_LSTF 0xd00
|
||||
#define rOFDM1_TRxPathEnable 0xd04
|
||||
|
||||
/*
|
||||
* 8. PageE(0xE00)
|
||||
* */
|
||||
#define rTxAGC_A_Rate18_06 0xe00
|
||||
#define rTxAGC_A_Rate54_24 0xe04
|
||||
#define rTxAGC_A_CCK1_Mcs32 0xe08
|
||||
#define rTxAGC_A_Mcs03_Mcs00 0xe10
|
||||
#define rTxAGC_A_Mcs07_Mcs04 0xe14
|
||||
#define rTxAGC_A_Mcs11_Mcs08 0xe18
|
||||
#define rTxAGC_A_Mcs15_Mcs12 0xe1c
|
||||
|
||||
#define rTxAGC_B_Rate18_06 0x830
|
||||
#define rTxAGC_B_Rate54_24 0x834
|
||||
#define rTxAGC_B_CCK1_55_Mcs32 0x838
|
||||
#define rTxAGC_B_Mcs03_Mcs00 0x83c
|
||||
#define rTxAGC_B_Mcs07_Mcs04 0x848
|
||||
#define rTxAGC_B_Mcs11_Mcs08 0x84c
|
||||
#define rTxAGC_B_Mcs15_Mcs12 0x868
|
||||
#define rTxAGC_B_CCK11_A_CCK2_11 0x86c
|
||||
|
||||
#define rFPGA0_IQK 0xe28
|
||||
#define rTx_IQK_Tone_A 0xe30
|
||||
#define rRx_IQK_Tone_A 0xe34
|
||||
#define rTx_IQK_PI_A 0xe38
|
||||
#define rRx_IQK_PI_A 0xe3c
|
||||
|
||||
#define rTx_IQK 0xe40
|
||||
#define rRx_IQK 0xe44
|
||||
#define rIQK_AGC_Pts 0xe48
|
||||
#define rIQK_AGC_Rsp 0xe4c
|
||||
#define rTx_IQK_Tone_B 0xe50
|
||||
#define rRx_IQK_Tone_B 0xe54
|
||||
#define rTx_IQK_PI_B 0xe58
|
||||
#define rRx_IQK_PI_B 0xe5c
|
||||
#define rIQK_AGC_Cont 0xe60
|
||||
|
||||
#define rBlue_Tooth 0xe6c
|
||||
#define rRx_Wait_CCA 0xe70
|
||||
#define rTx_CCK_RFON 0xe74
|
||||
#define rTx_CCK_BBON 0xe78
|
||||
#define rTx_OFDM_RFON 0xe7c
|
||||
#define rTx_OFDM_BBON 0xe80
|
||||
#define rTx_To_Rx 0xe84
|
||||
#define rTx_To_Tx 0xe88
|
||||
#define rRx_CCK 0xe8c
|
||||
|
||||
#define rTx_Power_Before_IQK_A 0xe94
|
||||
#define rTx_Power_After_IQK_A 0xe9c
|
||||
|
||||
#define rRx_Power_Before_IQK_A 0xea0
|
||||
#define rRx_Power_Before_IQK_A_2 0xea4
|
||||
#define rRx_Power_After_IQK_A 0xea8
|
||||
#define rRx_Power_After_IQK_A_2 0xeac
|
||||
|
||||
#define rTx_Power_Before_IQK_B 0xeb4
|
||||
#define rTx_Power_After_IQK_B 0xebc
|
||||
|
||||
#define rRx_Power_Before_IQK_B 0xec0
|
||||
#define rRx_Power_Before_IQK_B_2 0xec4
|
||||
#define rRx_Power_After_IQK_B 0xec8
|
||||
#define rRx_Power_After_IQK_B_2 0xecc
|
||||
|
||||
#define rRx_OFDM 0xed0
|
||||
#define rRx_Wait_RIFS 0xed4
|
||||
#define rRx_TO_Rx 0xed8
|
||||
#define rStandby 0xedc
|
||||
#define rSleep 0xee0
|
||||
#define rPMPD_ANAEN 0xeec
|
||||
|
||||
|
||||
/* 2. Page8(0x800) */
|
||||
#define bRFMOD 0x1 /* Reg 0x800 rFPGA0_RFMOD */
|
||||
#define bJapanMode 0x2
|
||||
#define bCCKTxSC 0x30
|
||||
#define bCCKEn 0x1000000
|
||||
#define bOFDMEn 0x2000000
|
||||
#define bXBTxAGC 0xf00 /* Reg 80c rFPGA0_TxGainStage */
|
||||
#define bXCTxAGC 0xf000
|
||||
#define bXDTxAGC 0xf0000
|
||||
|
||||
/* 4. PageA(0xA00) */
|
||||
#define bCCKBBMode 0x3 /* Useless */
|
||||
#define bCCKTxPowerSaving 0x80
|
||||
#define bCCKRxPowerSaving 0x40
|
||||
|
||||
#define bCCKSideBand 0x10 /* Reg 0xa00 rCCK0_System 20/40 switch */
|
||||
|
||||
#define bCCKScramble 0x8 /* Useless */
|
||||
#define bCCKAntDiversity 0x8000
|
||||
#define bCCKCarrierRecovery 0x4000
|
||||
#define bCCKTxRate 0x3000
|
||||
#define bCCKDCCancel 0x0800
|
||||
#define bCCKISICancel 0x0400
|
||||
#define bCCKMatchFilter 0x0200
|
||||
#define bCCKEqualizer 0x0100
|
||||
#define bCCKPreambleDetect 0x800000
|
||||
#define bCCKFastFalseCCA 0x400000
|
||||
#define bCCKChEstStart 0x300000
|
||||
#define bCCKCCACount 0x080000
|
||||
#define bCCKcs_lim 0x070000
|
||||
#define bCCKBistMode 0x80000000
|
||||
#define bCCKCCAMask 0x40000000
|
||||
#define bCCKTxDACPhase 0x4
|
||||
#define bCCKRxADCPhase 0x20000000 /* r_rx_clk */
|
||||
#define bCCKr_cp_mode0 0x0100
|
||||
#define bCCKTxDCOffset 0xf0
|
||||
#define bCCKRxDCOffset 0xf
|
||||
#define bCCKCCAMode 0xc000
|
||||
#define bCCKFalseCS_lim 0x3f00
|
||||
#define bCCKCS_ratio 0xc00000
|
||||
#define bCCKCorgBit_sel 0x300000
|
||||
#define bCCKPD_lim 0x0f0000
|
||||
#define bCCKNewCCA 0x80000000
|
||||
#define bCCKRxHPofIG 0x8000
|
||||
#define bCCKRxIG 0x7f00
|
||||
#define bCCKLNAPolarity 0x800000
|
||||
#define bCCKRx1stGain 0x7f0000
|
||||
#define bCCKRFExtend 0x20000000 /* CCK Rx Iinital gain polarity */
|
||||
#define bCCKRxAGCSatLevel 0x1f000000
|
||||
#define bCCKRxAGCSatCount 0xe0
|
||||
#define bCCKRxRFSettle 0x1f /* AGCsamp_dly */
|
||||
#define bCCKFixedRxAGC 0x8000
|
||||
/* #define bCCKRxAGCFormat 0x4000 */ /* remove to HSSI register 0x824 */
|
||||
#define bCCKAntennaPolarity 0x2000
|
||||
#define bCCKTxFilterType 0x0c00
|
||||
#define bCCKRxAGCReportType 0x0300
|
||||
#define bCCKRxDAGCEn 0x80000000
|
||||
#define bCCKRxDAGCPeriod 0x20000000
|
||||
#define bCCKRxDAGCSatLevel 0x1f000000
|
||||
#define bCCKTimingRecovery 0x800000
|
||||
#define bCCKTxC0 0x3f0000
|
||||
#define bCCKTxC1 0x3f000000
|
||||
#define bCCKTxC2 0x3f
|
||||
#define bCCKTxC3 0x3f00
|
||||
#define bCCKTxC4 0x3f0000
|
||||
#define bCCKTxC5 0x3f000000
|
||||
#define bCCKTxC6 0x3f
|
||||
#define bCCKTxC7 0x3f00
|
||||
#define bCCKDebugPort 0xff0000
|
||||
#define bCCKDACDebug 0x0f000000
|
||||
#define bCCKFalseAlarmEnable 0x8000
|
||||
#define bCCKFalseAlarmRead 0x4000
|
||||
#define bCCKTRSSI 0x7f
|
||||
#define bCCKRxAGCReport 0xfe
|
||||
#define bCCKRxReport_AntSel 0x80000000
|
||||
#define bCCKRxReport_MFOff 0x40000000
|
||||
#define bCCKRxRxReport_SQLoss 0x20000000
|
||||
#define bCCKRxReport_Pktloss 0x10000000
|
||||
#define bCCKRxReport_Lockedbit 0x08000000
|
||||
#define bCCKRxReport_RateError 0x04000000
|
||||
#define bCCKRxReport_RxRate 0x03000000
|
||||
#define bCCKRxFACounterLower 0xff
|
||||
#define bCCKRxFACounterUpper 0xff000000
|
||||
#define bCCKRxHPAGCStart 0xe000
|
||||
#define bCCKRxHPAGCFinal 0x1c00
|
||||
#define bCCKRxFalseAlarmEnable 0x8000
|
||||
#define bCCKFACounterFreeze 0x4000
|
||||
#define bCCKTxPathSel 0x10000000
|
||||
#define bCCKDefaultRxPath 0xc000000
|
||||
#define bCCKOptionRxPath 0x3000000
|
||||
|
||||
/* 6. PageE(0xE00) */
|
||||
#define bSTBCEn 0x4 /* Useless */
|
||||
#define bAntennaMapping 0x10
|
||||
#define bNss 0x20
|
||||
#define bCFOAntSumD 0x200
|
||||
#define bPHYCounterReset 0x8000000
|
||||
#define bCFOReportGet 0x4000000
|
||||
#define bOFDMContinueTx 0x10000000
|
||||
#define bOFDMSingleCarrier 0x20000000
|
||||
#define bOFDMSingleTone 0x40000000
|
||||
|
||||
|
||||
/*
|
||||
* Other Definition
|
||||
* */
|
||||
|
||||
#define bEnable 0x1 /* Useless */
|
||||
#define bDisable 0x0
|
||||
|
||||
/* byte endable for srwrite */
|
||||
#define bByte0 0x1 /* Useless */
|
||||
#define bByte1 0x2
|
||||
#define bByte2 0x4
|
||||
#define bByte3 0x8
|
||||
#define bWord0 0x3
|
||||
#define bWord1 0xc
|
||||
#define bDWord 0xf
|
||||
|
||||
/* for PutRegsetting & GetRegSetting BitMask */
|
||||
#define bMaskByte0 0xff /* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */
|
||||
#define bMaskByte1 0xff00
|
||||
#define bMaskByte2 0xff0000
|
||||
#define bMaskByte3 0xff000000
|
||||
#define bMaskHWord 0xffff0000
|
||||
#define bMaskLWord 0x0000ffff
|
||||
#define bMaskDWord 0xffffffff
|
||||
#define bMaskH3Bytes 0xffffff00
|
||||
#define bMask12Bits 0xfff
|
||||
#define bMaskH4Bits 0xf0000000
|
||||
#define bMaskOFDM_D 0xffc00000
|
||||
#define bMaskCCK 0x3f3f3f3f
|
||||
|
||||
|
||||
/*--------------------------Define Parameters-------------------------------*/
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,83 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#include "Hal8812PwrSeq.h"
|
||||
#include <rtl8812a_hal.h>
|
||||
|
||||
/*
|
||||
drivers should parse below arrays and do the corresponding actions
|
||||
*/
|
||||
/* 3 Power on Array */
|
||||
WLAN_PWR_CFG rtl8812_power_on_flow[RTL8812_TRANS_CARDEMU_TO_ACT_STEPS + RTL8812_TRANS_END_STEPS] = {
|
||||
RTL8812_TRANS_CARDEMU_TO_ACT
|
||||
RTL8812_TRANS_END
|
||||
};
|
||||
|
||||
/* 3Radio off GPIO Array */
|
||||
WLAN_PWR_CFG rtl8812_radio_off_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS + RTL8812_TRANS_END_STEPS] = {
|
||||
RTL8812_TRANS_ACT_TO_CARDEMU
|
||||
RTL8812_TRANS_END
|
||||
};
|
||||
|
||||
/* 3Card Disable Array */
|
||||
WLAN_PWR_CFG rtl8812_card_disable_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS + RTL8812_TRANS_CARDEMU_TO_PDN_STEPS + RTL8812_TRANS_END_STEPS] = {
|
||||
RTL8812_TRANS_ACT_TO_CARDEMU
|
||||
RTL8812_TRANS_CARDEMU_TO_CARDDIS
|
||||
RTL8812_TRANS_END
|
||||
};
|
||||
|
||||
/* 3 Card Enable Array */
|
||||
WLAN_PWR_CFG rtl8812_card_enable_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS + RTL8812_TRANS_CARDEMU_TO_PDN_STEPS + RTL8812_TRANS_END_STEPS] = {
|
||||
RTL8812_TRANS_CARDDIS_TO_CARDEMU
|
||||
RTL8812_TRANS_CARDEMU_TO_ACT
|
||||
RTL8812_TRANS_END
|
||||
};
|
||||
|
||||
/* 3Suspend Array */
|
||||
WLAN_PWR_CFG rtl8812_suspend_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS + RTL8812_TRANS_CARDEMU_TO_SUS_STEPS + RTL8812_TRANS_END_STEPS] = {
|
||||
RTL8812_TRANS_ACT_TO_CARDEMU
|
||||
RTL8812_TRANS_CARDEMU_TO_SUS
|
||||
RTL8812_TRANS_END
|
||||
};
|
||||
|
||||
/* 3 Resume Array */
|
||||
WLAN_PWR_CFG rtl8812_resume_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS + RTL8812_TRANS_CARDEMU_TO_SUS_STEPS + RTL8812_TRANS_END_STEPS] = {
|
||||
RTL8812_TRANS_SUS_TO_CARDEMU
|
||||
RTL8812_TRANS_CARDEMU_TO_ACT
|
||||
RTL8812_TRANS_END
|
||||
};
|
||||
|
||||
|
||||
|
||||
/* 3HWPDN Array */
|
||||
WLAN_PWR_CFG rtl8812_hwpdn_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS + RTL8812_TRANS_CARDEMU_TO_PDN_STEPS + RTL8812_TRANS_END_STEPS] = {
|
||||
RTL8812_TRANS_ACT_TO_CARDEMU
|
||||
RTL8812_TRANS_CARDEMU_TO_PDN
|
||||
RTL8812_TRANS_END
|
||||
};
|
||||
|
||||
/* 3 Enter LPS */
|
||||
WLAN_PWR_CFG rtl8812_enter_lps_flow[RTL8812_TRANS_ACT_TO_LPS_STEPS + RTL8812_TRANS_END_STEPS] = {
|
||||
/* FW behavior */
|
||||
RTL8812_TRANS_ACT_TO_LPS
|
||||
RTL8812_TRANS_END
|
||||
};
|
||||
|
||||
/* 3 Leave LPS */
|
||||
WLAN_PWR_CFG rtl8812_leave_lps_flow[RTL8812_TRANS_LPS_TO_ACT_STEPS + RTL8812_TRANS_END_STEPS] = {
|
||||
/* FW behavior */
|
||||
RTL8812_TRANS_LPS_TO_ACT
|
||||
RTL8812_TRANS_END
|
||||
};
|
||||
@@ -0,0 +1,208 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
|
||||
#ifndef __HAL8812PWRSEQ_H__
|
||||
#define __HAL8812PWRSEQ_H__
|
||||
|
||||
#include "HalPwrSeqCmd.h"
|
||||
|
||||
/*
|
||||
Check document WB-110628-DZ-RTL8195 (Jaguar) Power Architecture-R04.pdf
|
||||
There are 6 HW Power States:
|
||||
0: POFF--Power Off
|
||||
1: PDN--Power Down
|
||||
2: CARDEMU--Card Emulation
|
||||
3: ACT--Active Mode
|
||||
4: LPS--Low Power State
|
||||
5: SUS--Suspend
|
||||
|
||||
The transision from different states are defined below
|
||||
TRANS_CARDEMU_TO_ACT
|
||||
TRANS_ACT_TO_CARDEMU
|
||||
TRANS_CARDEMU_TO_SUS
|
||||
TRANS_SUS_TO_CARDEMU
|
||||
TRANS_CARDEMU_TO_PDN
|
||||
TRANS_ACT_TO_LPS
|
||||
TRANS_LPS_TO_ACT
|
||||
|
||||
TRANS_END
|
||||
*/
|
||||
#define RTL8812_TRANS_CARDEMU_TO_ACT_STEPS 15
|
||||
#define RTL8812_TRANS_ACT_TO_CARDEMU_STEPS 15
|
||||
#define RTL8812_TRANS_CARDEMU_TO_SUS_STEPS 15
|
||||
#define RTL8812_TRANS_SUS_TO_CARDEMU_STEPS 15
|
||||
#define RTL8812_TRANS_CARDEMU_TO_PDN_STEPS 15
|
||||
#define RTL8812_TRANS_PDN_TO_CARDEMU_STEPS 15
|
||||
#define RTL8812_TRANS_ACT_TO_LPS_STEPS 15
|
||||
#define RTL8812_TRANS_LPS_TO_ACT_STEPS 15
|
||||
#define RTL8812_TRANS_END_STEPS 1
|
||||
|
||||
|
||||
#define RTL8812_TRANS_CARDEMU_TO_ACT \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/* disable SW LPS 0x04[10]=0*/ \
|
||||
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \
|
||||
/*{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0}, disable HWPDN 0x04[15]=0*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0},/* disable WL suspend*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},/**/ \
|
||||
{0x0024, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0}, /* 0x24[1] Choose the type of buffer after xosc: nand*/ \
|
||||
{0x0028, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3, 0}, /* 0x28[33] Choose the type of buffer after xosc: nand*/
|
||||
|
||||
#define RTL8812_TRANS_ACT_TO_CARDEMU \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0c00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xc00[7:0] = 4 turn off 3-wire */ \
|
||||
{0x0e00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xe00[7:0] = 4 turn off 3-wire */ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /* 0x2[0] = 0 RESET BB, CLOSE RF */ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /* Whole BB is reset*/ \
|
||||
/*{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},//0x1F[7:0] = 0 turn off RF*/ \
|
||||
/*{0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},//0x4C[23] = 0x4E[7] = 0, switch DPDT_SEL_P output from register 0x65[2] */ \
|
||||
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x2A}, /* 0x07[7:0] = 0x28 sps pwm mode 0x2a for BT coex*/ \
|
||||
{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x02, 0},/*0x8[1] = 0 ANA clk = 500k */ \
|
||||
/*{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 | BIT1, 0}, // 0x02[1:0] = 0 reset BB */ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/
|
||||
|
||||
#define RTL8812_TRANS_CARDEMU_TO_SUS \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xcc},\
|
||||
{0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xEC},\
|
||||
{0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x07},/* gpio11 input mode, gpio10~8 output mode */ \
|
||||
{0x0045, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio 0~7 output same value as input ?? */ \
|
||||
{0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xff},/* gpio0~7 output mode */ \
|
||||
{0x0047, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/* 0x47[7:0] = 00 gpio mode */ \
|
||||
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/* suspend option all off */ \
|
||||
{0x0014, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x80, BIT7},/*0x14[7] = 1 turn on ZCD */ \
|
||||
{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, BIT0},/* 0x15[0] =1 trun on ZCD */ \
|
||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, BIT4},/*0x23[4] = 1 hpon LDO sleep mode */ \
|
||||
{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x02, 0},/*0x8[1] = 0 ANA clk = 500k */ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3}, /*0x04[11] = 2b'11 enable WL suspend for PCIe*/
|
||||
|
||||
#define RTL8812_TRANS_SUS_TO_CARDEMU \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0}, /*0x04[11] = 2b'01enable WL suspend*/ \
|
||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, 0},/*0x23[4] = 0 hpon LDO sleep mode leave */ \
|
||||
{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, 0},/* 0x15[0] =0 trun off ZCD */ \
|
||||
{0x0014, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x80, 0},/*0x14[7] = 0 turn off ZCD */ \
|
||||
{0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio0~7 input mode */ \
|
||||
{0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio11 input mode, gpio10~8 input mode */
|
||||
|
||||
#define RTL8812_TRANS_CARDEMU_TO_CARDDIS \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
/**{0x0194, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, //0x194[0]=0 , disable 32K clock*/ \
|
||||
/**{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x94}, //0x93 = 0x94 , 90[30] =0 enable 500k ANA clock .switch clock from 12M to 500K , 90 [26] =0 disable EEprom loader clock*/ \
|
||||
{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0}, /*0x03[2] = 0, reset 8051*/ \
|
||||
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x05}, /*0x80 = 05h if reload fw, fill the default value of host_CPU handshake field*/ \
|
||||
{0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xcc},\
|
||||
{0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xEC},\
|
||||
{0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x07},/* gpio11 input mode, gpio10~8 output mode */ \
|
||||
{0x0045, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio 0~7 output same value as input ?? */ \
|
||||
{0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xff},/* gpio0~7 output mode */ \
|
||||
{0x0047, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/* 0x47[7:0] = 00 gpio mode */ \
|
||||
{0x0014, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x80, BIT7},/*0x14[7] = 1 turn on ZCD */ \
|
||||
{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, BIT0},/* 0x15[0] =1 trun on ZCD */ \
|
||||
{0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, 0},/*0x12[0] = 0 force PFM mode */ \
|
||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, BIT4},/*0x23[4] = 1 hpon LDO sleep mode */ \
|
||||
{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x02, 0},/*0x8[1] = 0 ANA clk = 500k */ \
|
||||
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07 = 0x20 , SOP option to disable BG/MB*/ \
|
||||
{0x001f, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /*0x01f[1]=0 , disable RFC_0 control REG_RF_CTRL_8812 */ \
|
||||
{0x0076, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /*0x076[1]=0 , disable RFC_1 control REG_OPT_CTRL_8812 +2 */ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3}, /*0x04[11] = 2b'01 enable WL suspend*/
|
||||
|
||||
#define RTL8812_TRANS_CARDDIS_TO_CARDEMU \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*0x12[0] = 1 force PWM mode */ \
|
||||
{0x0014, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x80, 0},/*0x14[7] = 0 turn off ZCD */ \
|
||||
{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, 0},/* 0x15[0] =0 trun off ZCD */ \
|
||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, 0},/*0x23[4] = 0 hpon LDO leave sleep mode */ \
|
||||
{0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio0~7 input mode */ \
|
||||
{0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio11 input mode, gpio10~8 input mode */ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0}, /*0x04[10] = 0, enable SW LPS PCIE only*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0}, /*0x04[11] = 2b'01enable WL suspend*/ \
|
||||
{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2}, /*0x03[2] = 1, enable 8051*/ \
|
||||
{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/ \
|
||||
{0x0024, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /* 0x24[1] Choose the type of buffer after xosc: schmitt trigger*/ \
|
||||
{0x0028, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3, BIT3}, /* 0x28[33] Choose the type of buffer after xosc: schmitt trigger*/
|
||||
|
||||
|
||||
#define RTL8812_TRANS_CARDEMU_TO_PDN \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
|
||||
|
||||
#define RTL8812_TRANS_PDN_TO_CARDEMU \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
|
||||
|
||||
#define RTL8812_TRANS_ACT_TO_LPS \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/ \
|
||||
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/ \
|
||||
{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
|
||||
{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
|
||||
{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
|
||||
{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
|
||||
{0x0c00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xc00[7:0] = 4 turn off 3-wire */ \
|
||||
{0x0e00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xe00[7:0] = 4 turn off 3-wire */ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated, and RF closed*/ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /* Whole BB is reset*/ \
|
||||
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/ \
|
||||
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \
|
||||
{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/
|
||||
|
||||
|
||||
#define RTL8812_TRANS_LPS_TO_ACT \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/ \
|
||||
{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/ \
|
||||
{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/ \
|
||||
{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*. 0x08[4] = 0 switch TSF to 40M*/ \
|
||||
{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0 TSF in 40M*/ \
|
||||
{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6 | BIT7, 0}, /*. 0x29[7:6] = 2b'00 enable BB clock*/ \
|
||||
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1*/ \
|
||||
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1 | BIT0, BIT1 | BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/ \
|
||||
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/
|
||||
|
||||
#define RTL8812_TRANS_END \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, PWR_CMD_END, 0, 0},
|
||||
|
||||
|
||||
extern WLAN_PWR_CFG rtl8812_power_on_flow[RTL8812_TRANS_CARDEMU_TO_ACT_STEPS + RTL8812_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8812_radio_off_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS + RTL8812_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8812_card_disable_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS + RTL8812_TRANS_CARDEMU_TO_PDN_STEPS + RTL8812_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8812_card_enable_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS + RTL8812_TRANS_CARDEMU_TO_PDN_STEPS + RTL8812_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8812_suspend_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS + RTL8812_TRANS_CARDEMU_TO_SUS_STEPS + RTL8812_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8812_resume_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS + RTL8812_TRANS_CARDEMU_TO_SUS_STEPS + RTL8812_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8812_hwpdn_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS + RTL8812_TRANS_CARDEMU_TO_PDN_STEPS + RTL8812_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8812_enter_lps_flow[RTL8812_TRANS_ACT_TO_LPS_STEPS + RTL8812_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8812_leave_lps_flow[RTL8812_TRANS_LPS_TO_ACT_STEPS + RTL8812_TRANS_END_STEPS];
|
||||
|
||||
#endif /* __HAL8812PWRSEQ_H__ */
|
||||
@@ -0,0 +1,71 @@
|
||||
#ifndef HAL_8812A_PHY_REG_PG_H
|
||||
#define HAL_8812A_PHY_REG_PG_H
|
||||
|
||||
#include <cstdint>
|
||||
|
||||
/* Verbatim copy of `array_mp_8812a_phy_reg_pg` from
|
||||
* aircrack-ng/rtl8812au@v5.6.4.2_35491.20191025
|
||||
* hal/phydm/rtl8812a/halhwimg8812a_bb.c:1012-1058.
|
||||
*
|
||||
* Per-rate TX-power table. Each row is 6 entries:
|
||||
* {band, rfpath, tx_num, addr, bitmask, data}
|
||||
* - band: 0 = 2.4G, 1 = 5G
|
||||
* - rfpath: 0 = A, 1 = B
|
||||
* - tx_num: 0 = 1T, 1 = 2T
|
||||
* - addr: target BB register (e.g. 0xc24 = OFDM 18/6 power),
|
||||
* each byte of `data` is the raw power index for one rate
|
||||
* - bitmask: 0xffffffff for the full 4-byte target
|
||||
* - data: 4 packed bytes — per-rate target value, parsed by
|
||||
* `EepromManager::LoadTxPowerByRate` into
|
||||
* `TxPwrByRateOffset[band][path][rate]`. */
|
||||
|
||||
static const uint32_t kHal8812aPhyRegPg[] = {
|
||||
0, 0, 0, 0x00000c20, 0xffffffff, 0x34363840,
|
||||
0, 0, 0, 0x00000c24, 0xffffffff, 0x42424444,
|
||||
0, 0, 0, 0x00000c28, 0xffffffff, 0x30323638,
|
||||
0, 0, 0, 0x00000c2c, 0xffffffff, 0x40424444,
|
||||
0, 0, 0, 0x00000c30, 0xffffffff, 0x28303236,
|
||||
0, 0, 1, 0x00000c34, 0xffffffff, 0x38404242,
|
||||
0, 0, 1, 0x00000c38, 0xffffffff, 0x26283034,
|
||||
0, 0, 0, 0x00000c3c, 0xffffffff, 0x40424444,
|
||||
0, 0, 0, 0x00000c40, 0xffffffff, 0x28303236,
|
||||
0, 0, 0, 0x00000c44, 0xffffffff, 0x42422426,
|
||||
0, 0, 1, 0x00000c48, 0xffffffff, 0x30343840,
|
||||
0, 0, 1, 0x00000c4c, 0xffffffff, 0x22242628,
|
||||
0, 1, 0, 0x00000e20, 0xffffffff, 0x34363840,
|
||||
0, 1, 0, 0x00000e24, 0xffffffff, 0x42424444,
|
||||
0, 1, 0, 0x00000e28, 0xffffffff, 0x30323638,
|
||||
0, 1, 0, 0x00000e2c, 0xffffffff, 0x40424444,
|
||||
0, 1, 0, 0x00000e30, 0xffffffff, 0x28303236,
|
||||
0, 1, 1, 0x00000e34, 0xffffffff, 0x38404242,
|
||||
0, 1, 1, 0x00000e38, 0xffffffff, 0x26283034,
|
||||
0, 1, 0, 0x00000e3c, 0xffffffff, 0x40424444,
|
||||
0, 1, 0, 0x00000e40, 0xffffffff, 0x28303236,
|
||||
0, 1, 0, 0x00000e44, 0xffffffff, 0x42422426,
|
||||
0, 1, 1, 0x00000e48, 0xffffffff, 0x30343840,
|
||||
0, 1, 1, 0x00000e4c, 0xffffffff, 0x22242628,
|
||||
1, 0, 0, 0x00000c24, 0xffffffff, 0x42424444,
|
||||
1, 0, 0, 0x00000c28, 0xffffffff, 0x30323640,
|
||||
1, 0, 0, 0x00000c2c, 0xffffffff, 0x40424444,
|
||||
1, 0, 0, 0x00000c30, 0xffffffff, 0x28303236,
|
||||
1, 0, 1, 0x00000c34, 0xffffffff, 0x38404242,
|
||||
1, 0, 1, 0x00000c38, 0xffffffff, 0x26283034,
|
||||
1, 0, 0, 0x00000c3c, 0xffffffff, 0x40424444,
|
||||
1, 0, 0, 0x00000c40, 0xffffffff, 0x28303236,
|
||||
1, 0, 0, 0x00000c44, 0xffffffff, 0x42422426,
|
||||
1, 0, 1, 0x00000c48, 0xffffffff, 0x30343840,
|
||||
1, 0, 1, 0x00000c4c, 0xffffffff, 0x22242628,
|
||||
1, 1, 0, 0x00000e24, 0xffffffff, 0x42424444,
|
||||
1, 1, 0, 0x00000e28, 0xffffffff, 0x30323640,
|
||||
1, 1, 0, 0x00000e2c, 0xffffffff, 0x40424444,
|
||||
1, 1, 0, 0x00000e30, 0xffffffff, 0x28303236,
|
||||
1, 1, 1, 0x00000e34, 0xffffffff, 0x38404242,
|
||||
1, 1, 1, 0x00000e38, 0xffffffff, 0x26283034,
|
||||
1, 1, 0, 0x00000e3c, 0xffffffff, 0x40424444,
|
||||
1, 1, 0, 0x00000e40, 0xffffffff, 0x28303236,
|
||||
1, 1, 0, 0x00000e44, 0xffffffff, 0x42422426,
|
||||
1, 1, 1, 0x00000e48, 0xffffffff, 0x30343840,
|
||||
1, 1, 1, 0x00000e4c, 0xffffffff, 0x22242628
|
||||
};
|
||||
|
||||
#endif /* HAL_8812A_PHY_REG_PG_H */
|
||||
@@ -0,0 +1,105 @@
|
||||
/* Verbatim copy of `g_delta_swing_table_idx_mp_*_txpowertrack_usb_8812a` +
|
||||
* `tx_scaling_table_jaguar` from `aircrack-ng/rtl8812au` —
|
||||
* `hal/phydm/rtl8812a/halhwimg8812a_rf.c:1310..1339` and
|
||||
* `hal/phydm/halrf/halrf_powertracking_ce.c:538`. Do not hand-edit; if
|
||||
* upstream changes these tables, regenerate from the canonical source.
|
||||
*/
|
||||
#include "Hal8812a_TxPwrTrack.h"
|
||||
|
||||
const uint8_t kDeltaSwingTable2gaP[kDeltaSwingIdxSize] = {
|
||||
0, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 6, 7, 7,
|
||||
7, 7, 7, 7, 7, 7, 7, 7, 7, 7};
|
||||
const uint8_t kDeltaSwingTable2gaN[kDeltaSwingIdxSize] = {
|
||||
0, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 6, 7, 7,
|
||||
7, 8, 8, 9, 10, 10, 10, 10, 10, 10};
|
||||
const uint8_t kDeltaSwingTable2gbP[kDeltaSwingIdxSize] = {
|
||||
0, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7,
|
||||
7, 7, 7, 7, 7, 7, 7, 7, 7, 7};
|
||||
const uint8_t kDeltaSwingTable2gbN[kDeltaSwingIdxSize] = {
|
||||
0, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 8, 8,
|
||||
9, 9, 10, 10, 11, 11, 11, 11, 11, 11};
|
||||
const uint8_t kDeltaSwingTable2gCckAP[kDeltaSwingIdxSize] = {
|
||||
0, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 6, 7, 7,
|
||||
7, 7, 7, 7, 7, 7, 7, 7, 7, 7};
|
||||
const uint8_t kDeltaSwingTable2gCckAN[kDeltaSwingIdxSize] = {
|
||||
0, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 6, 7, 7,
|
||||
7, 8, 8, 9, 10, 10, 10, 10, 10, 10};
|
||||
const uint8_t kDeltaSwingTable2gCckBP[kDeltaSwingIdxSize] = {
|
||||
0, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7,
|
||||
7, 7, 7, 7, 7, 7, 7, 7, 7, 7};
|
||||
const uint8_t kDeltaSwingTable2gCckBN[kDeltaSwingIdxSize] = {
|
||||
0, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 8, 8,
|
||||
9, 9, 10, 10, 11, 11, 11, 11, 11, 11};
|
||||
|
||||
const uint8_t kDeltaSwingTable5gaP[kFiveGBandNum][kDeltaSwingIdxSize] = {
|
||||
{0, 1, 1, 2, 2, 3, 4, 5, 6, 7, 7, 8, 8, 9, 10, 11, 11, 11, 11, 11,
|
||||
11, 11, 11, 11, 11, 11, 11, 11, 11, 11},
|
||||
{0, 1, 1, 2, 3, 3, 4, 5, 6, 7, 7, 8, 8, 9, 10, 11, 11, 11, 11, 11,
|
||||
11, 11, 11, 11, 11, 11, 11, 11, 11, 11},
|
||||
{0, 1, 1, 2, 3, 3, 4, 5, 6, 7, 7, 8, 8, 9, 10, 11, 11, 12, 12, 11,
|
||||
11, 11, 11, 11, 11, 11, 11, 11, 11, 11},
|
||||
};
|
||||
const uint8_t kDeltaSwingTable5gaN[kFiveGBandNum][kDeltaSwingIdxSize] = {
|
||||
{0, 1, 1, 2, 2, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11,
|
||||
12, 12, 13, 13, 14, 15, 15, 15, 15, 15},
|
||||
{0, 1, 1, 2, 2, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11,
|
||||
12, 12, 13, 13, 14, 15, 15, 15, 15, 15},
|
||||
{0, 1, 1, 2, 2, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11,
|
||||
12, 12, 13, 13, 14, 15, 15, 15, 15, 15},
|
||||
};
|
||||
const uint8_t kDeltaSwingTable5gbP[kFiveGBandNum][kDeltaSwingIdxSize] = {
|
||||
{0, 1, 1, 2, 2, 3, 3, 4, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11,
|
||||
11, 11, 11, 11, 11, 11, 11, 11, 11, 11},
|
||||
{0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11,
|
||||
11, 11, 11, 11, 11, 11, 11, 11, 11, 11},
|
||||
{0, 1, 1, 2, 3, 3, 4, 5, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 11, 11,
|
||||
11, 11, 11, 11, 11, 11, 11, 11, 11, 11},
|
||||
};
|
||||
const uint8_t kDeltaSwingTable5gbN[kFiveGBandNum][kDeltaSwingIdxSize] = {
|
||||
{0, 1, 1, 2, 2, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11,
|
||||
12, 12, 13, 13, 14, 14, 14, 14, 14, 14},
|
||||
{0, 1, 1, 2, 2, 3, 4, 4, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11,
|
||||
12, 12, 13, 13, 14, 14, 14, 14, 14, 14},
|
||||
{0, 1, 1, 2, 2, 3, 4, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12,
|
||||
13, 13, 14, 14, 15, 16, 16, 16, 16, 16},
|
||||
};
|
||||
|
||||
const uint32_t kTxScalingTableJaguar[kTxScaleTableSize] = {
|
||||
0x081, /* 0, -12.0 dB */
|
||||
0x088, /* 1, -11.5 dB */
|
||||
0x090, /* 2, -11.0 dB */
|
||||
0x099, /* 3, -10.5 dB */
|
||||
0x0A2, /* 4, -10.0 dB */
|
||||
0x0AC, /* 5, -9.5 dB */
|
||||
0x0B6, /* 6, -9.0 dB */
|
||||
0x0C0, /* 7, -8.5 dB */
|
||||
0x0CC, /* 8, -8.0 dB */
|
||||
0x0D8, /* 9, -7.5 dB */
|
||||
0x0E5, /* 10, -7.0 dB */
|
||||
0x0F2, /* 11, -6.5 dB */
|
||||
0x101, /* 12, -6.0 dB */
|
||||
0x110, /* 13, -5.5 dB */
|
||||
0x120, /* 14, -5.0 dB */
|
||||
0x131, /* 15, -4.5 dB */
|
||||
0x143, /* 16, -4.0 dB */
|
||||
0x156, /* 17, -3.5 dB */
|
||||
0x16A, /* 18, -3.0 dB */
|
||||
0x180, /* 19, -2.5 dB */
|
||||
0x197, /* 20, -2.0 dB */
|
||||
0x1AF, /* 21, -1.5 dB */
|
||||
0x1C8, /* 22, -1.0 dB */
|
||||
0x1E3, /* 23, -0.5 dB */
|
||||
0x200, /* 24, +0.0 dB */
|
||||
0x21E, /* 25, +0.5 dB */
|
||||
0x23E, /* 26, +1.0 dB */
|
||||
0x261, /* 27, +1.5 dB */
|
||||
0x285, /* 28, +2.0 dB */
|
||||
0x2AB, /* 29, +2.5 dB */
|
||||
0x2D3, /* 30, +3.0 dB */
|
||||
0x2FE, /* 31, +3.5 dB */
|
||||
0x32B, /* 32, +4.0 dB */
|
||||
0x35C, /* 33, +4.5 dB */
|
||||
0x38E, /* 34, +5.0 dB */
|
||||
0x3C4, /* 35, +5.5 dB */
|
||||
0x3FE, /* 36, +6.0 dB */
|
||||
};
|
||||
@@ -0,0 +1,52 @@
|
||||
#ifndef HAL_8812A_TX_PWR_TRACK_H
|
||||
#define HAL_8812A_TX_PWR_TRACK_H
|
||||
|
||||
#include <cstdint>
|
||||
|
||||
/* Verbatim copy of `g_delta_swing_table_idx_mp_*_txpowertrack_usb_8812a` from
|
||||
* `aircrack-ng/rtl8812au/hal/phydm/rtl8812a/halhwimg8812a_rf.c:1310..1339`.
|
||||
*
|
||||
* These are phydm's per-band, per-RF-path, per-temperature-direction
|
||||
* lookup tables for the TX BB-swing thermal compensation loop. Indexed
|
||||
* by `|thermal_value - eeprom_thermal|` (clamped to 29). The value
|
||||
* returned is `absolute_ofdm_swing_idx[p]` — added to
|
||||
* `default_ofdm_index` (= 24 for 8812A, i.e. table-index 0x200/0dB)
|
||||
* to produce the final `tx_scaling_table_jaguar[]` index that
|
||||
* `odm_tx_pwr_track_set_pwr8812a` writes to BB 0xc1c[31:21]
|
||||
* (path A) or 0xe1c[31:21] (path B).
|
||||
*
|
||||
* Dimensions: `5g*_p/n` are [3][30] — three sub-band buckets (ch36..64,
|
||||
* ch100..144, ch149..177) × 30 temperature deltas. The 2G arrays
|
||||
* collapse to [30] (single band).
|
||||
*
|
||||
* "_p" suffix = thermal_value > eeprom_thermal (chip warmer than PG),
|
||||
* "_n" suffix = chip cooler (negate the delta before applying).
|
||||
*
|
||||
* Source tag: aircrack-ng/rtl8812au@5.6.4.2_35491.20191025
|
||||
*/
|
||||
|
||||
constexpr int kDeltaSwingIdxSize = 30;
|
||||
constexpr int kFiveGBandNum = 3;
|
||||
|
||||
extern const uint8_t kDeltaSwingTable2gaP[kDeltaSwingIdxSize];
|
||||
extern const uint8_t kDeltaSwingTable2gaN[kDeltaSwingIdxSize];
|
||||
extern const uint8_t kDeltaSwingTable2gbP[kDeltaSwingIdxSize];
|
||||
extern const uint8_t kDeltaSwingTable2gbN[kDeltaSwingIdxSize];
|
||||
extern const uint8_t kDeltaSwingTable2gCckAP[kDeltaSwingIdxSize];
|
||||
extern const uint8_t kDeltaSwingTable2gCckAN[kDeltaSwingIdxSize];
|
||||
extern const uint8_t kDeltaSwingTable2gCckBP[kDeltaSwingIdxSize];
|
||||
extern const uint8_t kDeltaSwingTable2gCckBN[kDeltaSwingIdxSize];
|
||||
extern const uint8_t kDeltaSwingTable5gaP[kFiveGBandNum][kDeltaSwingIdxSize];
|
||||
extern const uint8_t kDeltaSwingTable5gaN[kFiveGBandNum][kDeltaSwingIdxSize];
|
||||
extern const uint8_t kDeltaSwingTable5gbP[kFiveGBandNum][kDeltaSwingIdxSize];
|
||||
extern const uint8_t kDeltaSwingTable5gbN[kFiveGBandNum][kDeltaSwingIdxSize];
|
||||
|
||||
/* phydm's TX BB-swing table for the Jaguar family, indexed by ofdm-swing
|
||||
* index. Verbatim from `tx_scaling_table_jaguar` in
|
||||
* `halrf_powertracking_ce.c:538`. Index 24 = 0x200 (0 dB), index 26 =
|
||||
* 0x23E (+1.0 dB), table size 37 entries spanning -12 dB to +6 dB in
|
||||
* 0.5 dB steps. */
|
||||
constexpr int kTxScaleTableSize = 37;
|
||||
extern const uint32_t kTxScalingTableJaguar[kTxScaleTableSize];
|
||||
|
||||
#endif /* HAL_8812A_TX_PWR_TRACK_H */
|
||||
@@ -0,0 +1,585 @@
|
||||
#ifndef HAL_8812A_TXPWR_LMT_H
|
||||
#define HAL_8812A_TXPWR_LMT_H
|
||||
|
||||
/* Verbatim copy of `array_mp_8812a_txpwr_lmt` from
|
||||
* aircrack-ng/rtl8812au@v5.6.4.2_35491.20191025
|
||||
* hal/phydm/rtl8812a/halhwimg8812a_rf.c:1371-1937.
|
||||
*
|
||||
* Per-region (FCC/ETSI/MKK) regulatory TX-power limit table. Each row is
|
||||
* 7 entries: regulation, band, bandwidth, rate_section, ntx, channel,
|
||||
* power_index_limit. Parsed by `EepromManager::LoadTxPowerLimit` which
|
||||
* builds the 5D lookup `TxPwrLimit[regulation][band][bw][rs][ntx][ch]`
|
||||
* used by `GetTxPowerIndexBase` to cap `by_rate_diff` per regulatory
|
||||
* region — port of upstream `PHY_GetTxPowerLimit` from hal_com_phycfg.c. */
|
||||
|
||||
static const char *kHal8812aTxpwrLmt[] = {
|
||||
|
||||
"FCC", "2.4G", "20M", "CCK", "1T", "01", "36",
|
||||
"ETSI", "2.4G", "20M", "CCK", "1T", "01", "32",
|
||||
"MKK", "2.4G", "20M", "CCK", "1T", "01", "32",
|
||||
"FCC", "2.4G", "20M", "CCK", "1T", "02", "36",
|
||||
"ETSI", "2.4G", "20M", "CCK", "1T", "02", "32",
|
||||
"MKK", "2.4G", "20M", "CCK", "1T", "02", "32",
|
||||
"FCC", "2.4G", "20M", "CCK", "1T", "03", "36",
|
||||
"ETSI", "2.4G", "20M", "CCK", "1T", "03", "32",
|
||||
"MKK", "2.4G", "20M", "CCK", "1T", "03", "32",
|
||||
"FCC", "2.4G", "20M", "CCK", "1T", "04", "36",
|
||||
"ETSI", "2.4G", "20M", "CCK", "1T", "04", "32",
|
||||
"MKK", "2.4G", "20M", "CCK", "1T", "04", "32",
|
||||
"FCC", "2.4G", "20M", "CCK", "1T", "05", "36",
|
||||
"ETSI", "2.4G", "20M", "CCK", "1T", "05", "32",
|
||||
"MKK", "2.4G", "20M", "CCK", "1T", "05", "32",
|
||||
"FCC", "2.4G", "20M", "CCK", "1T", "06", "36",
|
||||
"ETSI", "2.4G", "20M", "CCK", "1T", "06", "32",
|
||||
"MKK", "2.4G", "20M", "CCK", "1T", "06", "32",
|
||||
"FCC", "2.4G", "20M", "CCK", "1T", "07", "36",
|
||||
"ETSI", "2.4G", "20M", "CCK", "1T", "07", "32",
|
||||
"MKK", "2.4G", "20M", "CCK", "1T", "07", "32",
|
||||
"FCC", "2.4G", "20M", "CCK", "1T", "08", "36",
|
||||
"ETSI", "2.4G", "20M", "CCK", "1T", "08", "32",
|
||||
"MKK", "2.4G", "20M", "CCK", "1T", "08", "32",
|
||||
"FCC", "2.4G", "20M", "CCK", "1T", "09", "36",
|
||||
"ETSI", "2.4G", "20M", "CCK", "1T", "09", "32",
|
||||
"MKK", "2.4G", "20M", "CCK", "1T", "09", "32",
|
||||
"FCC", "2.4G", "20M", "CCK", "1T", "10", "36",
|
||||
"ETSI", "2.4G", "20M", "CCK", "1T", "10", "32",
|
||||
"MKK", "2.4G", "20M", "CCK", "1T", "10", "32",
|
||||
"FCC", "2.4G", "20M", "CCK", "1T", "11", "36",
|
||||
"ETSI", "2.4G", "20M", "CCK", "1T", "11", "32",
|
||||
"MKK", "2.4G", "20M", "CCK", "1T", "11", "32",
|
||||
"FCC", "2.4G", "20M", "CCK", "1T", "12", "63",
|
||||
"ETSI", "2.4G", "20M", "CCK", "1T", "12", "32",
|
||||
"MKK", "2.4G", "20M", "CCK", "1T", "12", "32",
|
||||
"FCC", "2.4G", "20M", "CCK", "1T", "13", "63",
|
||||
"ETSI", "2.4G", "20M", "CCK", "1T", "13", "32",
|
||||
"MKK", "2.4G", "20M", "CCK", "1T", "13", "32",
|
||||
"FCC", "2.4G", "20M", "CCK", "1T", "14", "63",
|
||||
"ETSI", "2.4G", "20M", "CCK", "1T", "14", "63",
|
||||
"MKK", "2.4G", "20M", "CCK", "1T", "14", "32",
|
||||
"FCC", "2.4G", "20M", "OFDM", "1T", "01", "34",
|
||||
"ETSI", "2.4G", "20M", "OFDM", "1T", "01", "32",
|
||||
"MKK", "2.4G", "20M", "OFDM", "1T", "01", "32",
|
||||
"FCC", "2.4G", "20M", "OFDM", "1T", "02", "36",
|
||||
"ETSI", "2.4G", "20M", "OFDM", "1T", "02", "32",
|
||||
"MKK", "2.4G", "20M", "OFDM", "1T", "02", "32",
|
||||
"FCC", "2.4G", "20M", "OFDM", "1T", "03", "36",
|
||||
"ETSI", "2.4G", "20M", "OFDM", "1T", "03", "32",
|
||||
"MKK", "2.4G", "20M", "OFDM", "1T", "03", "32",
|
||||
"FCC", "2.4G", "20M", "OFDM", "1T", "04", "36",
|
||||
"ETSI", "2.4G", "20M", "OFDM", "1T", "04", "32",
|
||||
"MKK", "2.4G", "20M", "OFDM", "1T", "04", "32",
|
||||
"FCC", "2.4G", "20M", "OFDM", "1T", "05", "36",
|
||||
"ETSI", "2.4G", "20M", "OFDM", "1T", "05", "32",
|
||||
"MKK", "2.4G", "20M", "OFDM", "1T", "05", "32",
|
||||
"FCC", "2.4G", "20M", "OFDM", "1T", "06", "36",
|
||||
"ETSI", "2.4G", "20M", "OFDM", "1T", "06", "32",
|
||||
"MKK", "2.4G", "20M", "OFDM", "1T", "06", "32",
|
||||
"FCC", "2.4G", "20M", "OFDM", "1T", "07", "36",
|
||||
"ETSI", "2.4G", "20M", "OFDM", "1T", "07", "32",
|
||||
"MKK", "2.4G", "20M", "OFDM", "1T", "07", "32",
|
||||
"FCC", "2.4G", "20M", "OFDM", "1T", "08", "36",
|
||||
"ETSI", "2.4G", "20M", "OFDM", "1T", "08", "32",
|
||||
"MKK", "2.4G", "20M", "OFDM", "1T", "08", "32",
|
||||
"FCC", "2.4G", "20M", "OFDM", "1T", "09", "36",
|
||||
"ETSI", "2.4G", "20M", "OFDM", "1T", "09", "32",
|
||||
"MKK", "2.4G", "20M", "OFDM", "1T", "09", "32",
|
||||
"FCC", "2.4G", "20M", "OFDM", "1T", "10", "36",
|
||||
"ETSI", "2.4G", "20M", "OFDM", "1T", "10", "32",
|
||||
"MKK", "2.4G", "20M", "OFDM", "1T", "10", "32",
|
||||
"FCC", "2.4G", "20M", "OFDM", "1T", "11", "32",
|
||||
"ETSI", "2.4G", "20M", "OFDM", "1T", "11", "32",
|
||||
"MKK", "2.4G", "20M", "OFDM", "1T", "11", "32",
|
||||
"FCC", "2.4G", "20M", "OFDM", "1T", "12", "63",
|
||||
"ETSI", "2.4G", "20M", "OFDM", "1T", "12", "32",
|
||||
"MKK", "2.4G", "20M", "OFDM", "1T", "12", "32",
|
||||
"FCC", "2.4G", "20M", "OFDM", "1T", "13", "63",
|
||||
"ETSI", "2.4G", "20M", "OFDM", "1T", "13", "32",
|
||||
"MKK", "2.4G", "20M", "OFDM", "1T", "13", "32",
|
||||
"FCC", "2.4G", "20M", "OFDM", "1T", "14", "63",
|
||||
"ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63",
|
||||
"MKK", "2.4G", "20M", "OFDM", "1T", "14", "63",
|
||||
"FCC", "2.4G", "20M", "HT", "1T", "01", "34",
|
||||
"ETSI", "2.4G", "20M", "HT", "1T", "01", "32",
|
||||
"MKK", "2.4G", "20M", "HT", "1T", "01", "32",
|
||||
"FCC", "2.4G", "20M", "HT", "1T", "02", "36",
|
||||
"ETSI", "2.4G", "20M", "HT", "1T", "02", "32",
|
||||
"MKK", "2.4G", "20M", "HT", "1T", "02", "32",
|
||||
"FCC", "2.4G", "20M", "HT", "1T", "03", "36",
|
||||
"ETSI", "2.4G", "20M", "HT", "1T", "03", "32",
|
||||
"MKK", "2.4G", "20M", "HT", "1T", "03", "32",
|
||||
"FCC", "2.4G", "20M", "HT", "1T", "04", "36",
|
||||
"ETSI", "2.4G", "20M", "HT", "1T", "04", "32",
|
||||
"MKK", "2.4G", "20M", "HT", "1T", "04", "32",
|
||||
"FCC", "2.4G", "20M", "HT", "1T", "05", "36",
|
||||
"ETSI", "2.4G", "20M", "HT", "1T", "05", "32",
|
||||
"MKK", "2.4G", "20M", "HT", "1T", "05", "32",
|
||||
"FCC", "2.4G", "20M", "HT", "1T", "06", "36",
|
||||
"ETSI", "2.4G", "20M", "HT", "1T", "06", "32",
|
||||
"MKK", "2.4G", "20M", "HT", "1T", "06", "32",
|
||||
"FCC", "2.4G", "20M", "HT", "1T", "07", "36",
|
||||
"ETSI", "2.4G", "20M", "HT", "1T", "07", "32",
|
||||
"MKK", "2.4G", "20M", "HT", "1T", "07", "32",
|
||||
"FCC", "2.4G", "20M", "HT", "1T", "08", "36",
|
||||
"ETSI", "2.4G", "20M", "HT", "1T", "08", "32",
|
||||
"MKK", "2.4G", "20M", "HT", "1T", "08", "32",
|
||||
"FCC", "2.4G", "20M", "HT", "1T", "09", "36",
|
||||
"ETSI", "2.4G", "20M", "HT", "1T", "09", "32",
|
||||
"MKK", "2.4G", "20M", "HT", "1T", "09", "32",
|
||||
"FCC", "2.4G", "20M", "HT", "1T", "10", "36",
|
||||
"ETSI", "2.4G", "20M", "HT", "1T", "10", "32",
|
||||
"MKK", "2.4G", "20M", "HT", "1T", "10", "32",
|
||||
"FCC", "2.4G", "20M", "HT", "1T", "11", "32",
|
||||
"ETSI", "2.4G", "20M", "HT", "1T", "11", "32",
|
||||
"MKK", "2.4G", "20M", "HT", "1T", "11", "32",
|
||||
"FCC", "2.4G", "20M", "HT", "1T", "12", "63",
|
||||
"ETSI", "2.4G", "20M", "HT", "1T", "12", "32",
|
||||
"MKK", "2.4G", "20M", "HT", "1T", "12", "32",
|
||||
"FCC", "2.4G", "20M", "HT", "1T", "13", "63",
|
||||
"ETSI", "2.4G", "20M", "HT", "1T", "13", "32",
|
||||
"MKK", "2.4G", "20M", "HT", "1T", "13", "32",
|
||||
"FCC", "2.4G", "20M", "HT", "1T", "14", "63",
|
||||
"ETSI", "2.4G", "20M", "HT", "1T", "14", "63",
|
||||
"MKK", "2.4G", "20M", "HT", "1T", "14", "63",
|
||||
"FCC", "2.4G", "20M", "HT", "2T", "01", "32",
|
||||
"ETSI", "2.4G", "20M", "HT", "2T", "01", "32",
|
||||
"MKK", "2.4G", "20M", "HT", "2T", "01", "32",
|
||||
"FCC", "2.4G", "20M", "HT", "2T", "02", "34",
|
||||
"ETSI", "2.4G", "20M", "HT", "2T", "02", "32",
|
||||
"MKK", "2.4G", "20M", "HT", "2T", "02", "32",
|
||||
"FCC", "2.4G", "20M", "HT", "2T", "03", "34",
|
||||
"ETSI", "2.4G", "20M", "HT", "2T", "03", "32",
|
||||
"MKK", "2.4G", "20M", "HT", "2T", "03", "32",
|
||||
"FCC", "2.4G", "20M", "HT", "2T", "04", "34",
|
||||
"ETSI", "2.4G", "20M", "HT", "2T", "04", "32",
|
||||
"MKK", "2.4G", "20M", "HT", "2T", "04", "32",
|
||||
"FCC", "2.4G", "20M", "HT", "2T", "05", "34",
|
||||
"ETSI", "2.4G", "20M", "HT", "2T", "05", "32",
|
||||
"MKK", "2.4G", "20M", "HT", "2T", "05", "32",
|
||||
"FCC", "2.4G", "20M", "HT", "2T", "06", "34",
|
||||
"ETSI", "2.4G", "20M", "HT", "2T", "06", "32",
|
||||
"MKK", "2.4G", "20M", "HT", "2T", "06", "32",
|
||||
"FCC", "2.4G", "20M", "HT", "2T", "07", "34",
|
||||
"ETSI", "2.4G", "20M", "HT", "2T", "07", "32",
|
||||
"MKK", "2.4G", "20M", "HT", "2T", "07", "32",
|
||||
"FCC", "2.4G", "20M", "HT", "2T", "08", "34",
|
||||
"ETSI", "2.4G", "20M", "HT", "2T", "08", "32",
|
||||
"MKK", "2.4G", "20M", "HT", "2T", "08", "32",
|
||||
"FCC", "2.4G", "20M", "HT", "2T", "09", "34",
|
||||
"ETSI", "2.4G", "20M", "HT", "2T", "09", "32",
|
||||
"MKK", "2.4G", "20M", "HT", "2T", "09", "32",
|
||||
"FCC", "2.4G", "20M", "HT", "2T", "10", "34",
|
||||
"ETSI", "2.4G", "20M", "HT", "2T", "10", "32",
|
||||
"MKK", "2.4G", "20M", "HT", "2T", "10", "32",
|
||||
"FCC", "2.4G", "20M", "HT", "2T", "11", "30",
|
||||
"ETSI", "2.4G", "20M", "HT", "2T", "11", "32",
|
||||
"MKK", "2.4G", "20M", "HT", "2T", "11", "32",
|
||||
"FCC", "2.4G", "20M", "HT", "2T", "12", "63",
|
||||
"ETSI", "2.4G", "20M", "HT", "2T", "12", "32",
|
||||
"MKK", "2.4G", "20M", "HT", "2T", "12", "32",
|
||||
"FCC", "2.4G", "20M", "HT", "2T", "13", "63",
|
||||
"ETSI", "2.4G", "20M", "HT", "2T", "13", "32",
|
||||
"MKK", "2.4G", "20M", "HT", "2T", "13", "32",
|
||||
"FCC", "2.4G", "20M", "HT", "2T", "14", "63",
|
||||
"ETSI", "2.4G", "20M", "HT", "2T", "14", "63",
|
||||
"MKK", "2.4G", "20M", "HT", "2T", "14", "63",
|
||||
"FCC", "2.4G", "40M", "HT", "1T", "01", "63",
|
||||
"ETSI", "2.4G", "40M", "HT", "1T", "01", "63",
|
||||
"MKK", "2.4G", "40M", "HT", "1T", "01", "63",
|
||||
"FCC", "2.4G", "40M", "HT", "1T", "02", "63",
|
||||
"ETSI", "2.4G", "40M", "HT", "1T", "02", "63",
|
||||
"MKK", "2.4G", "40M", "HT", "1T", "02", "63",
|
||||
"FCC", "2.4G", "40M", "HT", "1T", "03", "32",
|
||||
"ETSI", "2.4G", "40M", "HT", "1T", "03", "32",
|
||||
"MKK", "2.4G", "40M", "HT", "1T", "03", "32",
|
||||
"FCC", "2.4G", "40M", "HT", "1T", "04", "36",
|
||||
"ETSI", "2.4G", "40M", "HT", "1T", "04", "32",
|
||||
"MKK", "2.4G", "40M", "HT", "1T", "04", "32",
|
||||
"FCC", "2.4G", "40M", "HT", "1T", "05", "36",
|
||||
"ETSI", "2.4G", "40M", "HT", "1T", "05", "32",
|
||||
"MKK", "2.4G", "40M", "HT", "1T", "05", "32",
|
||||
"FCC", "2.4G", "40M", "HT", "1T", "06", "36",
|
||||
"ETSI", "2.4G", "40M", "HT", "1T", "06", "32",
|
||||
"MKK", "2.4G", "40M", "HT", "1T", "06", "32",
|
||||
"FCC", "2.4G", "40M", "HT", "1T", "07", "36",
|
||||
"ETSI", "2.4G", "40M", "HT", "1T", "07", "32",
|
||||
"MKK", "2.4G", "40M", "HT", "1T", "07", "32",
|
||||
"FCC", "2.4G", "40M", "HT", "1T", "08", "36",
|
||||
"ETSI", "2.4G", "40M", "HT", "1T", "08", "32",
|
||||
"MKK", "2.4G", "40M", "HT", "1T", "08", "32",
|
||||
"FCC", "2.4G", "40M", "HT", "1T", "09", "36",
|
||||
"ETSI", "2.4G", "40M", "HT", "1T", "09", "32",
|
||||
"MKK", "2.4G", "40M", "HT", "1T", "09", "32",
|
||||
"FCC", "2.4G", "40M", "HT", "1T", "10", "36",
|
||||
"ETSI", "2.4G", "40M", "HT", "1T", "10", "32",
|
||||
"MKK", "2.4G", "40M", "HT", "1T", "10", "32",
|
||||
"FCC", "2.4G", "40M", "HT", "1T", "11", "32",
|
||||
"ETSI", "2.4G", "40M", "HT", "1T", "11", "32",
|
||||
"MKK", "2.4G", "40M", "HT", "1T", "11", "32",
|
||||
"FCC", "2.4G", "40M", "HT", "1T", "12", "63",
|
||||
"ETSI", "2.4G", "40M", "HT", "1T", "12", "32",
|
||||
"MKK", "2.4G", "40M", "HT", "1T", "12", "32",
|
||||
"FCC", "2.4G", "40M", "HT", "1T", "13", "63",
|
||||
"ETSI", "2.4G", "40M", "HT", "1T", "13", "32",
|
||||
"MKK", "2.4G", "40M", "HT", "1T", "13", "32",
|
||||
"FCC", "2.4G", "40M", "HT", "1T", "14", "63",
|
||||
"ETSI", "2.4G", "40M", "HT", "1T", "14", "63",
|
||||
"MKK", "2.4G", "40M", "HT", "1T", "14", "63",
|
||||
"FCC", "2.4G", "40M", "HT", "2T", "01", "63",
|
||||
"ETSI", "2.4G", "40M", "HT", "2T", "01", "63",
|
||||
"MKK", "2.4G", "40M", "HT", "2T", "01", "63",
|
||||
"FCC", "2.4G", "40M", "HT", "2T", "02", "63",
|
||||
"ETSI", "2.4G", "40M", "HT", "2T", "02", "63",
|
||||
"MKK", "2.4G", "40M", "HT", "2T", "02", "63",
|
||||
"FCC", "2.4G", "40M", "HT", "2T", "03", "30",
|
||||
"ETSI", "2.4G", "40M", "HT", "2T", "03", "30",
|
||||
"MKK", "2.4G", "40M", "HT", "2T", "03", "30",
|
||||
"FCC", "2.4G", "40M", "HT", "2T", "04", "34",
|
||||
"ETSI", "2.4G", "40M", "HT", "2T", "04", "30",
|
||||
"MKK", "2.4G", "40M", "HT", "2T", "04", "30",
|
||||
"FCC", "2.4G", "40M", "HT", "2T", "05", "34",
|
||||
"ETSI", "2.4G", "40M", "HT", "2T", "05", "30",
|
||||
"MKK", "2.4G", "40M", "HT", "2T", "05", "30",
|
||||
"FCC", "2.4G", "40M", "HT", "2T", "06", "34",
|
||||
"ETSI", "2.4G", "40M", "HT", "2T", "06", "30",
|
||||
"MKK", "2.4G", "40M", "HT", "2T", "06", "30",
|
||||
"FCC", "2.4G", "40M", "HT", "2T", "07", "34",
|
||||
"ETSI", "2.4G", "40M", "HT", "2T", "07", "30",
|
||||
"MKK", "2.4G", "40M", "HT", "2T", "07", "30",
|
||||
"FCC", "2.4G", "40M", "HT", "2T", "08", "34",
|
||||
"ETSI", "2.4G", "40M", "HT", "2T", "08", "30",
|
||||
"MKK", "2.4G", "40M", "HT", "2T", "08", "30",
|
||||
"FCC", "2.4G", "40M", "HT", "2T", "09", "34",
|
||||
"ETSI", "2.4G", "40M", "HT", "2T", "09", "30",
|
||||
"MKK", "2.4G", "40M", "HT", "2T", "09", "30",
|
||||
"FCC", "2.4G", "40M", "HT", "2T", "10", "34",
|
||||
"ETSI", "2.4G", "40M", "HT", "2T", "10", "30",
|
||||
"MKK", "2.4G", "40M", "HT", "2T", "10", "30",
|
||||
"FCC", "2.4G", "40M", "HT", "2T", "11", "30",
|
||||
"ETSI", "2.4G", "40M", "HT", "2T", "11", "30",
|
||||
"MKK", "2.4G", "40M", "HT", "2T", "11", "30",
|
||||
"FCC", "2.4G", "40M", "HT", "2T", "12", "63",
|
||||
"ETSI", "2.4G", "40M", "HT", "2T", "12", "32",
|
||||
"MKK", "2.4G", "40M", "HT", "2T", "12", "32",
|
||||
"FCC", "2.4G", "40M", "HT", "2T", "13", "63",
|
||||
"ETSI", "2.4G", "40M", "HT", "2T", "13", "32",
|
||||
"MKK", "2.4G", "40M", "HT", "2T", "13", "32",
|
||||
"FCC", "2.4G", "40M", "HT", "2T", "14", "63",
|
||||
"ETSI", "2.4G", "40M", "HT", "2T", "14", "63",
|
||||
"MKK", "2.4G", "40M", "HT", "2T", "14", "63",
|
||||
"FCC", "5G", "20M", "OFDM", "1T", "36", "30",
|
||||
"ETSI", "5G", "20M", "OFDM", "1T", "36", "32",
|
||||
"MKK", "5G", "20M", "OFDM", "1T", "36", "32",
|
||||
"FCC", "5G", "20M", "OFDM", "1T", "40", "30",
|
||||
"ETSI", "5G", "20M", "OFDM", "1T", "40", "32",
|
||||
"MKK", "5G", "20M", "OFDM", "1T", "40", "32",
|
||||
"FCC", "5G", "20M", "OFDM", "1T", "44", "30",
|
||||
"ETSI", "5G", "20M", "OFDM", "1T", "44", "32",
|
||||
"MKK", "5G", "20M", "OFDM", "1T", "44", "32",
|
||||
"FCC", "5G", "20M", "OFDM", "1T", "48", "30",
|
||||
"ETSI", "5G", "20M", "OFDM", "1T", "48", "32",
|
||||
"MKK", "5G", "20M", "OFDM", "1T", "48", "32",
|
||||
"FCC", "5G", "20M", "OFDM", "1T", "52", "36",
|
||||
"ETSI", "5G", "20M", "OFDM", "1T", "52", "32",
|
||||
"MKK", "5G", "20M", "OFDM", "1T", "52", "32",
|
||||
"FCC", "5G", "20M", "OFDM", "1T", "56", "34",
|
||||
"ETSI", "5G", "20M", "OFDM", "1T", "56", "32",
|
||||
"MKK", "5G", "20M", "OFDM", "1T", "56", "32",
|
||||
"FCC", "5G", "20M", "OFDM", "1T", "60", "32",
|
||||
"ETSI", "5G", "20M", "OFDM", "1T", "60", "32",
|
||||
"MKK", "5G", "20M", "OFDM", "1T", "60", "32",
|
||||
"FCC", "5G", "20M", "OFDM", "1T", "64", "28",
|
||||
"ETSI", "5G", "20M", "OFDM", "1T", "64", "32",
|
||||
"MKK", "5G", "20M", "OFDM", "1T", "64", "32",
|
||||
"FCC", "5G", "20M", "OFDM", "1T", "100", "30",
|
||||
"ETSI", "5G", "20M", "OFDM", "1T", "100", "32",
|
||||
"MKK", "5G", "20M", "OFDM", "1T", "100", "32",
|
||||
"FCC", "5G", "20M", "OFDM", "1T", "104", "30",
|
||||
"ETSI", "5G", "20M", "OFDM", "1T", "104", "32",
|
||||
"MKK", "5G", "20M", "OFDM", "1T", "104", "32",
|
||||
"FCC", "5G", "20M", "OFDM", "1T", "108", "32",
|
||||
"ETSI", "5G", "20M", "OFDM", "1T", "108", "32",
|
||||
"MKK", "5G", "20M", "OFDM", "1T", "108", "32",
|
||||
"FCC", "5G", "20M", "OFDM", "1T", "112", "34",
|
||||
"ETSI", "5G", "20M", "OFDM", "1T", "112", "32",
|
||||
"MKK", "5G", "20M", "OFDM", "1T", "112", "32",
|
||||
"FCC", "5G", "20M", "OFDM", "1T", "116", "34",
|
||||
"ETSI", "5G", "20M", "OFDM", "1T", "116", "32",
|
||||
"MKK", "5G", "20M", "OFDM", "1T", "116", "32",
|
||||
"FCC", "5G", "20M", "OFDM", "1T", "120", "36",
|
||||
"ETSI", "5G", "20M", "OFDM", "1T", "120", "32",
|
||||
"MKK", "5G", "20M", "OFDM", "1T", "120", "32",
|
||||
"FCC", "5G", "20M", "OFDM", "1T", "124", "34",
|
||||
"ETSI", "5G", "20M", "OFDM", "1T", "124", "32",
|
||||
"MKK", "5G", "20M", "OFDM", "1T", "124", "32",
|
||||
"FCC", "5G", "20M", "OFDM", "1T", "128", "32",
|
||||
"ETSI", "5G", "20M", "OFDM", "1T", "128", "32",
|
||||
"MKK", "5G", "20M", "OFDM", "1T", "128", "32",
|
||||
"FCC", "5G", "20M", "OFDM", "1T", "132", "30",
|
||||
"ETSI", "5G", "20M", "OFDM", "1T", "132", "32",
|
||||
"MKK", "5G", "20M", "OFDM", "1T", "132", "32",
|
||||
"FCC", "5G", "20M", "OFDM", "1T", "136", "30",
|
||||
"ETSI", "5G", "20M", "OFDM", "1T", "136", "32",
|
||||
"MKK", "5G", "20M", "OFDM", "1T", "136", "32",
|
||||
"FCC", "5G", "20M", "OFDM", "1T", "140", "28",
|
||||
"ETSI", "5G", "20M", "OFDM", "1T", "140", "32",
|
||||
"MKK", "5G", "20M", "OFDM", "1T", "140", "32",
|
||||
"FCC", "5G", "20M", "OFDM", "1T", "149", "36",
|
||||
"ETSI", "5G", "20M", "OFDM", "1T", "149", "32",
|
||||
"MKK", "5G", "20M", "OFDM", "1T", "149", "63",
|
||||
"FCC", "5G", "20M", "OFDM", "1T", "153", "36",
|
||||
"ETSI", "5G", "20M", "OFDM", "1T", "153", "32",
|
||||
"MKK", "5G", "20M", "OFDM", "1T", "153", "63",
|
||||
"FCC", "5G", "20M", "OFDM", "1T", "157", "36",
|
||||
"ETSI", "5G", "20M", "OFDM", "1T", "157", "32",
|
||||
"MKK", "5G", "20M", "OFDM", "1T", "157", "63",
|
||||
"FCC", "5G", "20M", "OFDM", "1T", "161", "36",
|
||||
"ETSI", "5G", "20M", "OFDM", "1T", "161", "32",
|
||||
"MKK", "5G", "20M", "OFDM", "1T", "161", "63",
|
||||
"FCC", "5G", "20M", "OFDM", "1T", "165", "36",
|
||||
"ETSI", "5G", "20M", "OFDM", "1T", "165", "32",
|
||||
"MKK", "5G", "20M", "OFDM", "1T", "165", "63",
|
||||
"FCC", "5G", "20M", "HT", "1T", "36", "30",
|
||||
"ETSI", "5G", "20M", "HT", "1T", "36", "32",
|
||||
"MKK", "5G", "20M", "HT", "1T", "36", "32",
|
||||
"FCC", "5G", "20M", "HT", "1T", "40", "30",
|
||||
"ETSI", "5G", "20M", "HT", "1T", "40", "32",
|
||||
"MKK", "5G", "20M", "HT", "1T", "40", "32",
|
||||
"FCC", "5G", "20M", "HT", "1T", "44", "30",
|
||||
"ETSI", "5G", "20M", "HT", "1T", "44", "32",
|
||||
"MKK", "5G", "20M", "HT", "1T", "44", "32",
|
||||
"FCC", "5G", "20M", "HT", "1T", "48", "30",
|
||||
"ETSI", "5G", "20M", "HT", "1T", "48", "32",
|
||||
"MKK", "5G", "20M", "HT", "1T", "48", "32",
|
||||
"FCC", "5G", "20M", "HT", "1T", "52", "36",
|
||||
"ETSI", "5G", "20M", "HT", "1T", "52", "32",
|
||||
"MKK", "5G", "20M", "HT", "1T", "52", "32",
|
||||
"FCC", "5G", "20M", "HT", "1T", "56", "34",
|
||||
"ETSI", "5G", "20M", "HT", "1T", "56", "32",
|
||||
"MKK", "5G", "20M", "HT", "1T", "56", "32",
|
||||
"FCC", "5G", "20M", "HT", "1T", "60", "32",
|
||||
"ETSI", "5G", "20M", "HT", "1T", "60", "32",
|
||||
"MKK", "5G", "20M", "HT", "1T", "60", "32",
|
||||
"FCC", "5G", "20M", "HT", "1T", "64", "28",
|
||||
"ETSI", "5G", "20M", "HT", "1T", "64", "32",
|
||||
"MKK", "5G", "20M", "HT", "1T", "64", "32",
|
||||
"FCC", "5G", "20M", "HT", "1T", "100", "30",
|
||||
"ETSI", "5G", "20M", "HT", "1T", "100", "32",
|
||||
"MKK", "5G", "20M", "HT", "1T", "100", "32",
|
||||
"FCC", "5G", "20M", "HT", "1T", "104", "30",
|
||||
"ETSI", "5G", "20M", "HT", "1T", "104", "32",
|
||||
"MKK", "5G", "20M", "HT", "1T", "104", "32",
|
||||
"FCC", "5G", "20M", "HT", "1T", "108", "32",
|
||||
"ETSI", "5G", "20M", "HT", "1T", "108", "32",
|
||||
"MKK", "5G", "20M", "HT", "1T", "108", "32",
|
||||
"FCC", "5G", "20M", "HT", "1T", "112", "34",
|
||||
"ETSI", "5G", "20M", "HT", "1T", "112", "32",
|
||||
"MKK", "5G", "20M", "HT", "1T", "112", "32",
|
||||
"FCC", "5G", "20M", "HT", "1T", "116", "34",
|
||||
"ETSI", "5G", "20M", "HT", "1T", "116", "32",
|
||||
"MKK", "5G", "20M", "HT", "1T", "116", "32",
|
||||
"FCC", "5G", "20M", "HT", "1T", "120", "36",
|
||||
"ETSI", "5G", "20M", "HT", "1T", "120", "32",
|
||||
"MKK", "5G", "20M", "HT", "1T", "120", "32",
|
||||
"FCC", "5G", "20M", "HT", "1T", "124", "34",
|
||||
"ETSI", "5G", "20M", "HT", "1T", "124", "32",
|
||||
"MKK", "5G", "20M", "HT", "1T", "124", "32",
|
||||
"FCC", "5G", "20M", "HT", "1T", "128", "32",
|
||||
"ETSI", "5G", "20M", "HT", "1T", "128", "32",
|
||||
"MKK", "5G", "20M", "HT", "1T", "128", "32",
|
||||
"FCC", "5G", "20M", "HT", "1T", "132", "30",
|
||||
"ETSI", "5G", "20M", "HT", "1T", "132", "32",
|
||||
"MKK", "5G", "20M", "HT", "1T", "132", "32",
|
||||
"FCC", "5G", "20M", "HT", "1T", "136", "30",
|
||||
"ETSI", "5G", "20M", "HT", "1T", "136", "32",
|
||||
"MKK", "5G", "20M", "HT", "1T", "136", "32",
|
||||
"FCC", "5G", "20M", "HT", "1T", "140", "28",
|
||||
"ETSI", "5G", "20M", "HT", "1T", "140", "32",
|
||||
"MKK", "5G", "20M", "HT", "1T", "140", "32",
|
||||
"FCC", "5G", "20M", "HT", "1T", "149", "36",
|
||||
"ETSI", "5G", "20M", "HT", "1T", "149", "32",
|
||||
"MKK", "5G", "20M", "HT", "1T", "149", "63",
|
||||
"FCC", "5G", "20M", "HT", "1T", "153", "36",
|
||||
"ETSI", "5G", "20M", "HT", "1T", "153", "32",
|
||||
"MKK", "5G", "20M", "HT", "1T", "153", "63",
|
||||
"FCC", "5G", "20M", "HT", "1T", "157", "36",
|
||||
"ETSI", "5G", "20M", "HT", "1T", "157", "32",
|
||||
"MKK", "5G", "20M", "HT", "1T", "157", "63",
|
||||
"FCC", "5G", "20M", "HT", "1T", "161", "36",
|
||||
"ETSI", "5G", "20M", "HT", "1T", "161", "32",
|
||||
"MKK", "5G", "20M", "HT", "1T", "161", "63",
|
||||
"FCC", "5G", "20M", "HT", "1T", "165", "36",
|
||||
"ETSI", "5G", "20M", "HT", "1T", "165", "32",
|
||||
"MKK", "5G", "20M", "HT", "1T", "165", "63",
|
||||
"FCC", "5G", "20M", "HT", "2T", "36", "28",
|
||||
"ETSI", "5G", "20M", "HT", "2T", "36", "30",
|
||||
"MKK", "5G", "20M", "HT", "2T", "36", "30",
|
||||
"FCC", "5G", "20M", "HT", "2T", "40", "28",
|
||||
"ETSI", "5G", "20M", "HT", "2T", "40", "30",
|
||||
"MKK", "5G", "20M", "HT", "2T", "40", "30",
|
||||
"FCC", "5G", "20M", "HT", "2T", "44", "28",
|
||||
"ETSI", "5G", "20M", "HT", "2T", "44", "30",
|
||||
"MKK", "5G", "20M", "HT", "2T", "44", "30",
|
||||
"FCC", "5G", "20M", "HT", "2T", "48", "28",
|
||||
"ETSI", "5G", "20M", "HT", "2T", "48", "30",
|
||||
"MKK", "5G", "20M", "HT", "2T", "48", "30",
|
||||
"FCC", "5G", "20M", "HT", "2T", "52", "34",
|
||||
"ETSI", "5G", "20M", "HT", "2T", "52", "30",
|
||||
"MKK", "5G", "20M", "HT", "2T", "52", "30",
|
||||
"FCC", "5G", "20M", "HT", "2T", "56", "32",
|
||||
"ETSI", "5G", "20M", "HT", "2T", "56", "30",
|
||||
"MKK", "5G", "20M", "HT", "2T", "56", "30",
|
||||
"FCC", "5G", "20M", "HT", "2T", "60", "30",
|
||||
"ETSI", "5G", "20M", "HT", "2T", "60", "30",
|
||||
"MKK", "5G", "20M", "HT", "2T", "60", "30",
|
||||
"FCC", "5G", "20M", "HT", "2T", "64", "26",
|
||||
"ETSI", "5G", "20M", "HT", "2T", "64", "30",
|
||||
"MKK", "5G", "20M", "HT", "2T", "64", "30",
|
||||
"FCC", "5G", "20M", "HT", "2T", "100", "28",
|
||||
"ETSI", "5G", "20M", "HT", "2T", "100", "30",
|
||||
"MKK", "5G", "20M", "HT", "2T", "100", "30",
|
||||
"FCC", "5G", "20M", "HT", "2T", "104", "28",
|
||||
"ETSI", "5G", "20M", "HT", "2T", "104", "30",
|
||||
"MKK", "5G", "20M", "HT", "2T", "104", "30",
|
||||
"FCC", "5G", "20M", "HT", "2T", "108", "30",
|
||||
"ETSI", "5G", "20M", "HT", "2T", "108", "30",
|
||||
"MKK", "5G", "20M", "HT", "2T", "108", "30",
|
||||
"FCC", "5G", "20M", "HT", "2T", "112", "32",
|
||||
"ETSI", "5G", "20M", "HT", "2T", "112", "30",
|
||||
"MKK", "5G", "20M", "HT", "2T", "112", "30",
|
||||
"FCC", "5G", "20M", "HT", "2T", "116", "32",
|
||||
"ETSI", "5G", "20M", "HT", "2T", "116", "30",
|
||||
"MKK", "5G", "20M", "HT", "2T", "116", "30",
|
||||
"FCC", "5G", "20M", "HT", "2T", "120", "34",
|
||||
"ETSI", "5G", "20M", "HT", "2T", "120", "30",
|
||||
"MKK", "5G", "20M", "HT", "2T", "120", "30",
|
||||
"FCC", "5G", "20M", "HT", "2T", "124", "32",
|
||||
"ETSI", "5G", "20M", "HT", "2T", "124", "30",
|
||||
"MKK", "5G", "20M", "HT", "2T", "124", "30",
|
||||
"FCC", "5G", "20M", "HT", "2T", "128", "30",
|
||||
"ETSI", "5G", "20M", "HT", "2T", "128", "30",
|
||||
"MKK", "5G", "20M", "HT", "2T", "128", "30",
|
||||
"FCC", "5G", "20M", "HT", "2T", "132", "28",
|
||||
"ETSI", "5G", "20M", "HT", "2T", "132", "30",
|
||||
"MKK", "5G", "20M", "HT", "2T", "132", "30",
|
||||
"FCC", "5G", "20M", "HT", "2T", "136", "28",
|
||||
"ETSI", "5G", "20M", "HT", "2T", "136", "30",
|
||||
"MKK", "5G", "20M", "HT", "2T", "136", "30",
|
||||
"FCC", "5G", "20M", "HT", "2T", "140", "26",
|
||||
"ETSI", "5G", "20M", "HT", "2T", "140", "30",
|
||||
"MKK", "5G", "20M", "HT", "2T", "140", "30",
|
||||
"FCC", "5G", "20M", "HT", "2T", "149", "34",
|
||||
"ETSI", "5G", "20M", "HT", "2T", "149", "30",
|
||||
"MKK", "5G", "20M", "HT", "2T", "149", "63",
|
||||
"FCC", "5G", "20M", "HT", "2T", "153", "34",
|
||||
"ETSI", "5G", "20M", "HT", "2T", "153", "30",
|
||||
"MKK", "5G", "20M", "HT", "2T", "153", "63",
|
||||
"FCC", "5G", "20M", "HT", "2T", "157", "34",
|
||||
"ETSI", "5G", "20M", "HT", "2T", "157", "30",
|
||||
"MKK", "5G", "20M", "HT", "2T", "157", "63",
|
||||
"FCC", "5G", "20M", "HT", "2T", "161", "34",
|
||||
"ETSI", "5G", "20M", "HT", "2T", "161", "30",
|
||||
"MKK", "5G", "20M", "HT", "2T", "161", "63",
|
||||
"FCC", "5G", "20M", "HT", "2T", "165", "34",
|
||||
"ETSI", "5G", "20M", "HT", "2T", "165", "30",
|
||||
"MKK", "5G", "20M", "HT", "2T", "165", "63",
|
||||
"FCC", "5G", "40M", "HT", "1T", "38", "30",
|
||||
"ETSI", "5G", "40M", "HT", "1T", "38", "32",
|
||||
"MKK", "5G", "40M", "HT", "1T", "38", "32",
|
||||
"FCC", "5G", "40M", "HT", "1T", "46", "30",
|
||||
"ETSI", "5G", "40M", "HT", "1T", "46", "32",
|
||||
"MKK", "5G", "40M", "HT", "1T", "46", "32",
|
||||
"FCC", "5G", "40M", "HT", "1T", "54", "32",
|
||||
"ETSI", "5G", "40M", "HT", "1T", "54", "32",
|
||||
"MKK", "5G", "40M", "HT", "1T", "54", "32",
|
||||
"FCC", "5G", "40M", "HT", "1T", "62", "32",
|
||||
"ETSI", "5G", "40M", "HT", "1T", "62", "32",
|
||||
"MKK", "5G", "40M", "HT", "1T", "62", "32",
|
||||
"FCC", "5G", "40M", "HT", "1T", "102", "28",
|
||||
"ETSI", "5G", "40M", "HT", "1T", "102", "32",
|
||||
"MKK", "5G", "40M", "HT", "1T", "102", "32",
|
||||
"FCC", "5G", "40M", "HT", "1T", "110", "32",
|
||||
"ETSI", "5G", "40M", "HT", "1T", "110", "32",
|
||||
"MKK", "5G", "40M", "HT", "1T", "110", "32",
|
||||
"FCC", "5G", "40M", "HT", "1T", "118", "36",
|
||||
"ETSI", "5G", "40M", "HT", "1T", "118", "32",
|
||||
"MKK", "5G", "40M", "HT", "1T", "118", "32",
|
||||
"FCC", "5G", "40M", "HT", "1T", "126", "34",
|
||||
"ETSI", "5G", "40M", "HT", "1T", "126", "32",
|
||||
"MKK", "5G", "40M", "HT", "1T", "126", "32",
|
||||
"FCC", "5G", "40M", "HT", "1T", "134", "32",
|
||||
"ETSI", "5G", "40M", "HT", "1T", "134", "32",
|
||||
"MKK", "5G", "40M", "HT", "1T", "134", "32",
|
||||
"FCC", "5G", "40M", "HT", "1T", "151", "36",
|
||||
"ETSI", "5G", "40M", "HT", "1T", "151", "32",
|
||||
"MKK", "5G", "40M", "HT", "1T", "151", "63",
|
||||
"FCC", "5G", "40M", "HT", "1T", "159", "36",
|
||||
"ETSI", "5G", "40M", "HT", "1T", "159", "32",
|
||||
"MKK", "5G", "40M", "HT", "1T", "159", "63",
|
||||
"FCC", "5G", "40M", "HT", "2T", "38", "28",
|
||||
"ETSI", "5G", "40M", "HT", "2T", "38", "30",
|
||||
"MKK", "5G", "40M", "HT", "2T", "38", "30",
|
||||
"FCC", "5G", "40M", "HT", "2T", "46", "28",
|
||||
"ETSI", "5G", "40M", "HT", "2T", "46", "30",
|
||||
"MKK", "5G", "40M", "HT", "2T", "46", "30",
|
||||
"FCC", "5G", "40M", "HT", "2T", "54", "30",
|
||||
"ETSI", "5G", "40M", "HT", "2T", "54", "30",
|
||||
"MKK", "5G", "40M", "HT", "2T", "54", "30",
|
||||
"FCC", "5G", "40M", "HT", "2T", "62", "30",
|
||||
"ETSI", "5G", "40M", "HT", "2T", "62", "30",
|
||||
"MKK", "5G", "40M", "HT", "2T", "62", "30",
|
||||
"FCC", "5G", "40M", "HT", "2T", "102", "26",
|
||||
"ETSI", "5G", "40M", "HT", "2T", "102", "30",
|
||||
"MKK", "5G", "40M", "HT", "2T", "102", "30",
|
||||
"FCC", "5G", "40M", "HT", "2T", "110", "30",
|
||||
"ETSI", "5G", "40M", "HT", "2T", "110", "30",
|
||||
"MKK", "5G", "40M", "HT", "2T", "110", "30",
|
||||
"FCC", "5G", "40M", "HT", "2T", "118", "34",
|
||||
"ETSI", "5G", "40M", "HT", "2T", "118", "30",
|
||||
"MKK", "5G", "40M", "HT", "2T", "118", "30",
|
||||
"FCC", "5G", "40M", "HT", "2T", "126", "32",
|
||||
"ETSI", "5G", "40M", "HT", "2T", "126", "30",
|
||||
"MKK", "5G", "40M", "HT", "2T", "126", "30",
|
||||
"FCC", "5G", "40M", "HT", "2T", "134", "30",
|
||||
"ETSI", "5G", "40M", "HT", "2T", "134", "30",
|
||||
"MKK", "5G", "40M", "HT", "2T", "134", "30",
|
||||
"FCC", "5G", "40M", "HT", "2T", "151", "34",
|
||||
"ETSI", "5G", "40M", "HT", "2T", "151", "30",
|
||||
"MKK", "5G", "40M", "HT", "2T", "151", "63",
|
||||
"FCC", "5G", "40M", "HT", "2T", "159", "34",
|
||||
"ETSI", "5G", "40M", "HT", "2T", "159", "30",
|
||||
"MKK", "5G", "40M", "HT", "2T", "159", "63",
|
||||
"FCC", "5G", "80M", "VHT", "1T", "42", "30",
|
||||
"ETSI", "5G", "80M", "VHT", "1T", "42", "32",
|
||||
"MKK", "5G", "80M", "VHT", "1T", "42", "32",
|
||||
"FCC", "5G", "80M", "VHT", "1T", "58", "28",
|
||||
"ETSI", "5G", "80M", "VHT", "1T", "58", "32",
|
||||
"MKK", "5G", "80M", "VHT", "1T", "58", "32",
|
||||
"FCC", "5G", "80M", "VHT", "1T", "106", "30",
|
||||
"ETSI", "5G", "80M", "VHT", "1T", "106", "32",
|
||||
"MKK", "5G", "80M", "VHT", "1T", "106", "32",
|
||||
"FCC", "5G", "80M", "VHT", "1T", "122", "34",
|
||||
"ETSI", "5G", "80M", "VHT", "1T", "122", "32",
|
||||
"MKK", "5G", "80M", "VHT", "1T", "122", "32",
|
||||
"FCC", "5G", "80M", "VHT", "1T", "155", "36",
|
||||
"ETSI", "5G", "80M", "VHT", "1T", "155", "32",
|
||||
"MKK", "5G", "80M", "VHT", "1T", "155", "63",
|
||||
"FCC", "5G", "80M", "VHT", "2T", "42", "28",
|
||||
"ETSI", "5G", "80M", "VHT", "2T", "42", "30",
|
||||
"MKK", "5G", "80M", "VHT", "2T", "42", "30",
|
||||
"FCC", "5G", "80M", "VHT", "2T", "58", "26",
|
||||
"ETSI", "5G", "80M", "VHT", "2T", "58", "30",
|
||||
"MKK", "5G", "80M", "VHT", "2T", "58", "30",
|
||||
"FCC", "5G", "80M", "VHT", "2T", "106", "28",
|
||||
"ETSI", "5G", "80M", "VHT", "2T", "106", "30",
|
||||
"MKK", "5G", "80M", "VHT", "2T", "106", "30",
|
||||
"FCC", "5G", "80M", "VHT", "2T", "122", "32",
|
||||
"ETSI", "5G", "80M", "VHT", "2T", "122", "30",
|
||||
"MKK", "5G", "80M", "VHT", "2T", "122", "30",
|
||||
"FCC", "5G", "80M", "VHT", "2T", "155", "34",
|
||||
"ETSI", "5G", "80M", "VHT", "2T", "155", "30",
|
||||
"MKK", "5G", "80M", "VHT", "2T", "155", "63"
|
||||
|
||||
|
||||
};
|
||||
|
||||
#endif /* HAL_8812A_TXPWR_LMT_H */
|
||||
@@ -0,0 +1,250 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __INC_HAL8814PHYCFG_H__
|
||||
#define __INC_HAL8814PHYCFG_H__
|
||||
|
||||
|
||||
/*--------------------------Define Parameters-------------------------------*/
|
||||
#define LOOP_LIMIT 5
|
||||
#define MAX_STALL_TIME 50 /* us */
|
||||
#define AntennaDiversityValue 0x80 /* (Adapter->bSoftwareAntennaDiversity ? 0x00 : 0x80) */
|
||||
#define MAX_TXPWR_IDX_NMODE_92S 63
|
||||
#define Reset_Cnt_Limit 3
|
||||
|
||||
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
#define MAX_AGGR_NUM 0x0B
|
||||
#else
|
||||
#define MAX_AGGR_NUM 0x07
|
||||
#endif /* CONFIG_PCI_HCI */
|
||||
|
||||
|
||||
/*--------------------------Define Parameters-------------------------------*/
|
||||
|
||||
/*------------------------------Define structure----------------------------*/
|
||||
|
||||
|
||||
/* BB/RF related */
|
||||
|
||||
#define SIC_ENABLE 0
|
||||
|
||||
/*------------------------------Define structure----------------------------*/
|
||||
|
||||
|
||||
/*------------------------Export global variable----------------------------*/
|
||||
/*------------------------Export global variable----------------------------*/
|
||||
|
||||
|
||||
/*------------------------Export Marco Definition---------------------------*/
|
||||
/*------------------------Export Marco Definition---------------------------*/
|
||||
|
||||
|
||||
/*--------------------------Exported Function prototype---------------------*/
|
||||
/* 1. BB register R/W API */
|
||||
|
||||
extern u32
|
||||
PHY_QueryBBReg8814A(PADAPTER Adapter,
|
||||
u32 RegAddr,
|
||||
u32 BitMask);
|
||||
|
||||
|
||||
void
|
||||
PHY_SetBBReg8814A(PADAPTER Adapter,
|
||||
u32 RegAddr,
|
||||
u32 BitMask,
|
||||
u32 Data);
|
||||
|
||||
|
||||
extern u32
|
||||
PHY_QueryRFReg8814A(PADAPTER Adapter,
|
||||
enum rf_path eRFPath,
|
||||
u32 RegAddr,
|
||||
u32 BitMask);
|
||||
|
||||
|
||||
void
|
||||
PHY_SetRFReg8814A(PADAPTER Adapter,
|
||||
enum rf_path eRFPath,
|
||||
u32 RegAddr,
|
||||
u32 BitMask,
|
||||
u32 Data);
|
||||
|
||||
/* 1 3. Initial BB/RF config by reading MAC/BB/RF txt. */
|
||||
s32
|
||||
phy_BB8814A_Config_ParaFile(
|
||||
PADAPTER Adapter
|
||||
);
|
||||
|
||||
void
|
||||
PHY_ConfigBB_8814A(
|
||||
PADAPTER Adapter
|
||||
);
|
||||
|
||||
|
||||
void
|
||||
phy_ADC_CLK_8814A(
|
||||
PADAPTER Adapter
|
||||
);
|
||||
|
||||
s32
|
||||
PHY_RFConfig8814A(
|
||||
PADAPTER Adapter
|
||||
);
|
||||
|
||||
/*
|
||||
* RF Power setting
|
||||
*
|
||||
* BOOLEAN PHY_SetRFPowerState8814A(PADAPTER Adapter, rt_rf_power_state eRFPowerState); */
|
||||
|
||||
/* 1 5. Tx Power setting API */
|
||||
|
||||
void
|
||||
PHY_SetTxPowerLevel8814(
|
||||
PADAPTER Adapter,
|
||||
u8 Channel
|
||||
);
|
||||
|
||||
u8
|
||||
phy_get_tx_power_index_8814a(
|
||||
PADAPTER Adapter,
|
||||
enum rf_path RFPath,
|
||||
u8 Rate,
|
||||
enum channel_width BandWidth,
|
||||
u8 Channel
|
||||
);
|
||||
|
||||
u8
|
||||
PHY_GetTxPowerIndex8814A(
|
||||
PADAPTER Adapter,
|
||||
enum rf_path RFPath,
|
||||
u8 Rate,
|
||||
u8 BandWidth,
|
||||
u8 Channel,
|
||||
struct txpwr_idx_comp *tic
|
||||
);
|
||||
|
||||
void
|
||||
PHY_SetTxPowerIndex_8814A(
|
||||
PADAPTER Adapter,
|
||||
u32 PowerIndex,
|
||||
enum rf_path RFPath,
|
||||
u8 Rate
|
||||
);
|
||||
|
||||
u32
|
||||
PHY_GetTxBBSwing_8814A(
|
||||
PADAPTER Adapter,
|
||||
BAND_TYPE Band,
|
||||
enum rf_path RFPath
|
||||
);
|
||||
|
||||
|
||||
|
||||
/* 1 6. Channel setting API */
|
||||
#if 0
|
||||
void
|
||||
PHY_SwChnlTimerCallback8814A(
|
||||
struct timer_list *p_timer
|
||||
);
|
||||
#endif
|
||||
void
|
||||
PHY_SwChnlWorkItemCallback8814A(
|
||||
void *pContext
|
||||
);
|
||||
|
||||
|
||||
void
|
||||
HAL_HandleSwChnl8814A(
|
||||
PADAPTER pAdapter,
|
||||
u8 channel
|
||||
);
|
||||
|
||||
void
|
||||
PHY_SwChnlSynchronously8814A(PADAPTER pAdapter,
|
||||
u8 channel);
|
||||
|
||||
void
|
||||
PHY_SwChnlAndSetBWModeCallback8814A(void *pContext);
|
||||
|
||||
|
||||
void
|
||||
PHY_HandleSwChnlAndSetBW8814A(
|
||||
PADAPTER Adapter,
|
||||
BOOLEAN bSwitchChannel,
|
||||
BOOLEAN bSetBandWidth,
|
||||
u8 ChannelNum,
|
||||
enum channel_width ChnlWidth,
|
||||
u8 ChnlOffsetOf40MHz,
|
||||
u8 ChnlOffsetOf80MHz,
|
||||
u8 CenterFrequencyIndex1
|
||||
);
|
||||
|
||||
|
||||
BOOLEAN
|
||||
PHY_QueryRFPathSwitch_8814A(PADAPTER pAdapter);
|
||||
|
||||
|
||||
|
||||
#if (USE_WORKITEM)
|
||||
void
|
||||
RtCheckForHangWorkItemCallback8814A(
|
||||
void *pContext
|
||||
);
|
||||
#endif
|
||||
|
||||
BOOLEAN
|
||||
SetAntennaConfig8814A(
|
||||
PADAPTER Adapter,
|
||||
u8 DefaultAnt
|
||||
);
|
||||
|
||||
void
|
||||
PHY_SetRFEReg8814A(
|
||||
PADAPTER Adapter,
|
||||
BOOLEAN bInit,
|
||||
u8 Band
|
||||
);
|
||||
|
||||
|
||||
s32
|
||||
PHY_SwitchWirelessBand8814A(
|
||||
PADAPTER Adapter,
|
||||
u8 Band
|
||||
);
|
||||
|
||||
void
|
||||
PHY_SetIO_8814A(
|
||||
PADAPTER pAdapter
|
||||
);
|
||||
|
||||
void
|
||||
PHY_SetSwChnlBWMode8814(
|
||||
PADAPTER Adapter,
|
||||
u8 channel,
|
||||
enum channel_width Bandwidth,
|
||||
u8 Offset40,
|
||||
u8 Offset80
|
||||
);
|
||||
|
||||
s32 PHY_MACConfig8814(PADAPTER Adapter);
|
||||
int PHY_BBConfig8814(PADAPTER Adapter);
|
||||
void PHY_Set_SecCCATH_by_RXANT_8814A(PADAPTER pAdapter, u32 ulAntennaRx);
|
||||
|
||||
|
||||
|
||||
/*--------------------------Exported Function prototype---------------------*/
|
||||
|
||||
/*--------------------------Exported Function prototype---------------------*/
|
||||
#endif /* __INC_HAL8192CPHYCFG_H */
|
||||
@@ -0,0 +1,863 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __INC_HAL8814PHYREG_H__
|
||||
#define __INC_HAL8814PHYREG_H__
|
||||
/*--------------------------Define Parameters-------------------------------*/
|
||||
/*
|
||||
* BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
|
||||
* 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
|
||||
* 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
|
||||
* 3. RF register 0x00-2E
|
||||
* 4. Bit Mask for BB/RF register
|
||||
* 5. Other defintion for BB/RF R/W
|
||||
* */
|
||||
|
||||
|
||||
/* BB Register Definition */
|
||||
|
||||
#define rCCAonSec_Jaguar 0x838
|
||||
#define rPwed_TH_Jaguar 0x830
|
||||
#define rL1_Weight_Jaguar 0x840
|
||||
#define r_L1_SBD_start_time 0x844
|
||||
|
||||
/* BW and sideband setting */
|
||||
#define rBWIndication_Jaguar 0x834
|
||||
#define rL1PeakTH_Jaguar 0x848
|
||||
#define rRFMOD_Jaguar 0x8ac /* RF mode */
|
||||
#define rADC_Buf_Clk_Jaguar 0x8c4
|
||||
#define rADC_Buf_40_Clk_Jaguar2 0x8c8
|
||||
#define rRFECTRL_Jaguar 0x900
|
||||
#define bRFMOD_Jaguar 0xc3
|
||||
#define rCCK_System_Jaguar 0xa00 /* for cck sideband */
|
||||
#define bCCK_System_Jaguar 0x10
|
||||
|
||||
/* Block & Path enable */
|
||||
#define rOFDMCCKEN_Jaguar 0x808 /* OFDM/CCK block enable */
|
||||
#define bOFDMEN_Jaguar 0x20000000
|
||||
#define bCCKEN_Jaguar 0x10000000
|
||||
#define rRxPath_Jaguar 0x808 /* Rx antenna */
|
||||
#define bRxPath_Jaguar 0xff
|
||||
#define rTxPath_Jaguar 0x80c /* Tx antenna */
|
||||
#define bTxPath_Jaguar 0x0fffffff
|
||||
#define rCCK_RX_Jaguar 0xa04 /* for cck rx path selection */
|
||||
#define bCCK_RX_Jaguar 0x0c000000
|
||||
#define rVhtlen_Use_Lsig_Jaguar 0x8c3 /* Use LSIG for VHT length */
|
||||
|
||||
#define rRxPath_Jaguar2 0xa04 /* Rx antenna */
|
||||
#define rTxAnt_1Nsts_Jaguar2 0x93c /* Tx antenna for 1Nsts */
|
||||
#define rTxAnt_23Nsts_Jaguar2 0x940 /* Tx antenna for 2Nsts and 3Nsts */
|
||||
|
||||
|
||||
/* RF read/write-related */
|
||||
#define rHSSIRead_Jaguar 0x8b0 /* RF read addr */
|
||||
#define bHSSIRead_addr_Jaguar 0xff
|
||||
#define bHSSIRead_trigger_Jaguar 0x100
|
||||
#define rA_PIRead_Jaguar 0xd04 /* RF readback with PI */
|
||||
#define rB_PIRead_Jaguar 0xd44 /* RF readback with PI */
|
||||
#define rA_SIRead_Jaguar 0xd08 /* RF readback with SI */
|
||||
#define rB_SIRead_Jaguar 0xd48 /* RF readback with SI */
|
||||
#define rRead_data_Jaguar 0xfffff
|
||||
#define rA_LSSIWrite_Jaguar 0xc90 /* RF write addr */
|
||||
#define rB_LSSIWrite_Jaguar 0xe90 /* RF write addr */
|
||||
#define bLSSIWrite_data_Jaguar 0x000fffff
|
||||
#define bLSSIWrite_addr_Jaguar 0x0ff00000
|
||||
|
||||
#define rC_PIRead_Jaguar2 0xd84 /* RF readback with PI */
|
||||
#define rD_PIRead_Jaguar2 0xdC4 /* RF readback with PI */
|
||||
#define rC_SIRead_Jaguar2 0xd88 /* RF readback with SI */
|
||||
#define rD_SIRead_Jaguar2 0xdC8 /* RF readback with SI */
|
||||
#define rC_LSSIWrite_Jaguar2 0x1890 /* RF write addr */
|
||||
#define rD_LSSIWrite_Jaguar2 0x1A90 /* RF write addr */
|
||||
|
||||
|
||||
/* YN: mask the following register definition temporarily */
|
||||
#define rFPGA0_XA_RFInterfaceOE 0x860 /* RF Channel switch */
|
||||
#define rFPGA0_XB_RFInterfaceOE 0x864
|
||||
|
||||
#define rFPGA0_XAB_RFInterfaceSW 0x870 /* RF Interface Software Control */
|
||||
#define rFPGA0_XCD_RFInterfaceSW 0x874
|
||||
|
||||
/* #define rFPGA0_XAB_RFParameter 0x878 */ /* RF Parameter
|
||||
* #define rFPGA0_XCD_RFParameter 0x87c */
|
||||
|
||||
/* #define rFPGA0_AnalogParameter1 0x880 */ /* Crystal cap setting RF-R/W protection for parameter4??
|
||||
* #define rFPGA0_AnalogParameter2 0x884
|
||||
* #define rFPGA0_AnalogParameter3 0x888
|
||||
* #define rFPGA0_AdDaClockEn 0x888 */ /* enable ad/da clock1 for dual-phy
|
||||
* #define rFPGA0_AnalogParameter4 0x88c */
|
||||
|
||||
|
||||
/* CCK TX scaling */
|
||||
#define rCCK_TxFilter1_Jaguar 0xa20
|
||||
#define bCCK_TxFilter1_C0_Jaguar 0x00ff0000
|
||||
#define bCCK_TxFilter1_C1_Jaguar 0xff000000
|
||||
#define rCCK_TxFilter2_Jaguar 0xa24
|
||||
#define bCCK_TxFilter2_C2_Jaguar 0x000000ff
|
||||
#define bCCK_TxFilter2_C3_Jaguar 0x0000ff00
|
||||
#define bCCK_TxFilter2_C4_Jaguar 0x00ff0000
|
||||
#define bCCK_TxFilter2_C5_Jaguar 0xff000000
|
||||
#define rCCK_TxFilter3_Jaguar 0xa28
|
||||
#define bCCK_TxFilter3_C6_Jaguar 0x000000ff
|
||||
#define bCCK_TxFilter3_C7_Jaguar 0x0000ff00
|
||||
/* NBI & CSI Mask setting */
|
||||
#define rCSI_Mask_Setting1_Jaguar 0x874
|
||||
#define rCSI_Fix_Mask0_Jaguar 0x880
|
||||
#define rCSI_Fix_Mask1_Jaguar 0x884
|
||||
#define rCSI_Fix_Mask2_Jaguar 0x888
|
||||
#define rCSI_Fix_Mask3_Jaguar 0x88c
|
||||
#define rCSI_Fix_Mask4_Jaguar 0x890
|
||||
#define rCSI_Fix_Mask5_Jaguar 0x894
|
||||
#define rCSI_Fix_Mask6_Jaguar 0x898
|
||||
#define rCSI_Fix_Mask7_Jaguar 0x89c
|
||||
#define rNBI_Setting_Jaguar 0x87c
|
||||
|
||||
|
||||
/* YN: mask the following register definition temporarily
|
||||
* #define rPdp_AntA 0xb00
|
||||
* #define rPdp_AntA_4 0xb04
|
||||
* #define rConfig_Pmpd_AntA 0xb28
|
||||
* #define rConfig_AntA 0xb68
|
||||
* #define rConfig_AntB 0xb6c
|
||||
* #define rPdp_AntB 0xb70
|
||||
* #define rPdp_AntB_4 0xb74
|
||||
* #define rConfig_Pmpd_AntB 0xb98
|
||||
* #define rAPK 0xbd8 */
|
||||
|
||||
/* RXIQC */
|
||||
#define rA_RxIQC_AB_Jaguar 0xc10 /* RxIQ imblance matrix coeff. A & B */
|
||||
#define rA_RxIQC_CD_Jaguar 0xc14 /* RxIQ imblance matrix coeff. C & D */
|
||||
#define rA_TxScale_Jaguar 0xc1c /* Pah_A TX scaling factor */
|
||||
#define rB_TxScale_Jaguar 0xe1c /* Path_B TX scaling factor */
|
||||
#define rB_RxIQC_AB_Jaguar 0xe10 /* RxIQ imblance matrix coeff. A & B */
|
||||
#define rB_RxIQC_CD_Jaguar 0xe14 /* RxIQ imblance matrix coeff. C & D */
|
||||
#define b_RxIQC_AC_Jaguar 0x02ff /* bit mask for IQC matrix element A & C */
|
||||
#define b_RxIQC_BD_Jaguar 0x02ff0000 /* bit mask for IQC matrix element A & C */
|
||||
|
||||
#define rC_TxScale_Jaguar2 0x181c /* Pah_C TX scaling factor */
|
||||
#define rD_TxScale_Jaguar2 0x1A1c /* Path_D TX scaling factor */
|
||||
#define rRF_TxGainOffset 0x55
|
||||
|
||||
/* DIG-related */
|
||||
#define rA_IGI_Jaguar 0xc50 /* Initial Gain for path-A */
|
||||
#define rB_IGI_Jaguar 0xe50 /* Initial Gain for path-B */
|
||||
#define rC_IGI_Jaguar2 0x1850 /* Initial Gain for path-C */
|
||||
#define rD_IGI_Jaguar2 0x1A50 /* Initial Gain for path-D */
|
||||
|
||||
#define rOFDM_FalseAlarm1_Jaguar 0xf48 /* counter for break */
|
||||
#define rOFDM_FalseAlarm2_Jaguar 0xf4c /* counter for spoofing */
|
||||
#define rCCK_FalseAlarm_Jaguar 0xa5c /* counter for cck false alarm */
|
||||
#define b_FalseAlarm_Jaguar 0xffff
|
||||
#define rCCK_CCA_Jaguar 0xa08 /* cca threshold */
|
||||
#define bCCK_CCA_Jaguar 0x00ff0000
|
||||
|
||||
/* Tx Power Ttraining-related */
|
||||
#define rA_TxPwrTraing_Jaguar 0xc54
|
||||
#define rB_TxPwrTraing_Jaguar 0xe54
|
||||
|
||||
/* Report-related */
|
||||
#define rOFDM_ShortCFOAB_Jaguar 0xf60
|
||||
#define rOFDM_LongCFOAB_Jaguar 0xf64
|
||||
#define rOFDM_EndCFOAB_Jaguar 0xf70
|
||||
#define rOFDM_AGCReport_Jaguar 0xf84
|
||||
#define rOFDM_RxSNR_Jaguar 0xf88
|
||||
#define rOFDM_RxEVMCSI_Jaguar 0xf8c
|
||||
#define rOFDM_SIGReport_Jaguar 0xf90
|
||||
|
||||
/* Misc functions */
|
||||
#define rEDCCA_Jaguar 0x8a4 /* EDCCA */
|
||||
#define bEDCCA_Jaguar 0xffff
|
||||
#define rAGC_table_Jaguar 0x82c /* AGC tabel select */
|
||||
#define bAGC_table_Jaguar 0x3
|
||||
#define b_sel5g_Jaguar 0x1000 /* sel5g */
|
||||
#define b_LNA_sw_Jaguar 0x8000 /* HW/WS control for LNA */
|
||||
#define rFc_area_Jaguar 0x860 /* fc_area */
|
||||
#define bFc_area_Jaguar 0x1ffe000
|
||||
#define rSingleTone_ContTx_Jaguar 0x914
|
||||
|
||||
#define rAGC_table_Jaguar2 0x958 /* AGC tabel select */
|
||||
#define rDMA_trigger_Jaguar2 0x95C /* ADC sample mode */
|
||||
|
||||
|
||||
/* RFE */
|
||||
#define rA_RFE_Pinmux_Jaguar 0xcb0 /* Path_A RFE cotrol pinmux */
|
||||
#define rB_RFE_Pinmux_Jaguar 0xeb0 /* Path_B RFE control pinmux */
|
||||
#define rA_RFE_Inv_Jaguar 0xcb4 /* Path_A RFE cotrol */
|
||||
#define rB_RFE_Inv_Jaguar 0xeb4 /* Path_B RFE control */
|
||||
#define rA_RFE_Jaguar 0xcb8 /* Path_A RFE cotrol */
|
||||
#define rB_RFE_Jaguar 0xeb8 /* Path_B RFE control */
|
||||
#define rA_RFE_Inverse_Jaguar 0xCBC /* Path_A RFE control inverse */
|
||||
#define rB_RFE_Inverse_Jaguar 0xEBC /* Path_B RFE control inverse */
|
||||
#define r_ANTSEL_SW_Jaguar 0x900 /* ANTSEL SW Control */
|
||||
#define bMask_RFEInv_Jaguar 0x3ff00000
|
||||
#define bMask_AntselPathFollow_Jaguar 0x00030000
|
||||
|
||||
#define rC_RFE_Pinmux_Jaguar 0x18B4 /* Path_C RFE cotrol pinmux */
|
||||
#define rD_RFE_Pinmux_Jaguar 0x1AB4 /* Path_D RFE cotrol pinmux */
|
||||
#define rA_RFE_Sel_Jaguar2 0x1990
|
||||
|
||||
|
||||
|
||||
/* TX AGC */
|
||||
#define rTxAGC_A_CCK11_CCK1_JAguar 0xc20
|
||||
#define rTxAGC_A_Ofdm18_Ofdm6_JAguar 0xc24
|
||||
#define rTxAGC_A_Ofdm54_Ofdm24_JAguar 0xc28
|
||||
#define rTxAGC_A_MCS3_MCS0_JAguar 0xc2c
|
||||
#define rTxAGC_A_MCS7_MCS4_JAguar 0xc30
|
||||
#define rTxAGC_A_MCS11_MCS8_JAguar 0xc34
|
||||
#define rTxAGC_A_MCS15_MCS12_JAguar 0xc38
|
||||
#define rTxAGC_A_Nss1Index3_Nss1Index0_JAguar 0xc3c
|
||||
#define rTxAGC_A_Nss1Index7_Nss1Index4_JAguar 0xc40
|
||||
#define rTxAGC_A_Nss2Index1_Nss1Index8_JAguar 0xc44
|
||||
#define rTxAGC_A_Nss2Index5_Nss2Index2_JAguar 0xc48
|
||||
#define rTxAGC_A_Nss2Index9_Nss2Index6_JAguar 0xc4c
|
||||
#define rTxAGC_B_CCK11_CCK1_JAguar 0xe20
|
||||
#define rTxAGC_B_Ofdm18_Ofdm6_JAguar 0xe24
|
||||
#define rTxAGC_B_Ofdm54_Ofdm24_JAguar 0xe28
|
||||
#define rTxAGC_B_MCS3_MCS0_JAguar 0xe2c
|
||||
#define rTxAGC_B_MCS7_MCS4_JAguar 0xe30
|
||||
#define rTxAGC_B_MCS11_MCS8_JAguar 0xe34
|
||||
#define rTxAGC_B_MCS15_MCS12_JAguar 0xe38
|
||||
#define rTxAGC_B_Nss1Index3_Nss1Index0_JAguar 0xe3c
|
||||
#define rTxAGC_B_Nss1Index7_Nss1Index4_JAguar 0xe40
|
||||
#define rTxAGC_B_Nss2Index1_Nss1Index8_JAguar 0xe44
|
||||
#define rTxAGC_B_Nss2Index5_Nss2Index2_JAguar 0xe48
|
||||
#define rTxAGC_B_Nss2Index9_Nss2Index6_JAguar 0xe4c
|
||||
#define bTxAGC_byte0_Jaguar 0xff
|
||||
#define bTxAGC_byte1_Jaguar 0xff00
|
||||
#define bTxAGC_byte2_Jaguar 0xff0000
|
||||
#define bTxAGC_byte3_Jaguar 0xff000000
|
||||
|
||||
|
||||
/* TX AGC */
|
||||
#define rTxAGC_A_CCK11_CCK1_Jaguar2 0xc20
|
||||
#define rTxAGC_A_Ofdm18_Ofdm6_Jaguar2 0xc24
|
||||
#define rTxAGC_A_Ofdm54_Ofdm24_Jaguar2 0xc28
|
||||
#define rTxAGC_A_MCS3_MCS0_Jaguar2 0xc2c
|
||||
#define rTxAGC_A_MCS7_MCS4_Jaguar2 0xc30
|
||||
#define rTxAGC_A_MCS11_MCS8_Jaguar2 0xc34
|
||||
#define rTxAGC_A_MCS15_MCS12_Jaguar2 0xc38
|
||||
#define rTxAGC_A_MCS19_MCS16_Jaguar2 0xcd8
|
||||
#define rTxAGC_A_MCS23_MCS20_Jaguar2 0xcdc
|
||||
#define rTxAGC_A_Nss1Index3_Nss1Index0_Jaguar2 0xc3c
|
||||
#define rTxAGC_A_Nss1Index7_Nss1Index4_Jaguar2 0xc40
|
||||
#define rTxAGC_A_Nss2Index1_Nss1Index8_Jaguar2 0xc44
|
||||
#define rTxAGC_A_Nss2Index5_Nss2Index2_Jaguar2 0xc48
|
||||
#define rTxAGC_A_Nss2Index9_Nss2Index6_Jaguar2 0xc4c
|
||||
#define rTxAGC_A_Nss3Index3_Nss3Index0_Jaguar2 0xce0
|
||||
#define rTxAGC_A_Nss3Index7_Nss3Index4_Jaguar2 0xce4
|
||||
#define rTxAGC_A_Nss3Index9_Nss3Index8_Jaguar2 0xce8
|
||||
#define rTxAGC_B_CCK11_CCK1_Jaguar2 0xe20
|
||||
#define rTxAGC_B_Ofdm18_Ofdm6_Jaguar2 0xe24
|
||||
#define rTxAGC_B_Ofdm54_Ofdm24_Jaguar2 0xe28
|
||||
#define rTxAGC_B_MCS3_MCS0_Jaguar2 0xe2c
|
||||
#define rTxAGC_B_MCS7_MCS4_Jaguar2 0xe30
|
||||
#define rTxAGC_B_MCS11_MCS8_Jaguar2 0xe34
|
||||
#define rTxAGC_B_MCS15_MCS12_Jaguar2 0xe38
|
||||
#define rTxAGC_B_MCS19_MCS16_Jaguar2 0xed8
|
||||
#define rTxAGC_B_MCS23_MCS20_Jaguar2 0xedc
|
||||
#define rTxAGC_B_Nss1Index3_Nss1Index0_Jaguar2 0xe3c
|
||||
#define rTxAGC_B_Nss1Index7_Nss1Index4_Jaguar2 0xe40
|
||||
#define rTxAGC_B_Nss2Index1_Nss1Index8_Jaguar2 0xe44
|
||||
#define rTxAGC_B_Nss2Index5_Nss2Index2_Jaguar2 0xe48
|
||||
#define rTxAGC_B_Nss2Index9_Nss2Index6_Jaguar2 0xe4c
|
||||
#define rTxAGC_B_Nss3Index3_Nss3Index0_Jaguar2 0xee0
|
||||
#define rTxAGC_B_Nss3Index7_Nss3Index4_Jaguar2 0xee4
|
||||
#define rTxAGC_B_Nss3Index9_Nss3Index8_Jaguar2 0xee8
|
||||
#define rTxAGC_C_CCK11_CCK1_Jaguar2 0x1820
|
||||
#define rTxAGC_C_Ofdm18_Ofdm6_Jaguar2 0x1824
|
||||
#define rTxAGC_C_Ofdm54_Ofdm24_Jaguar2 0x1828
|
||||
#define rTxAGC_C_MCS3_MCS0_Jaguar2 0x182c
|
||||
#define rTxAGC_C_MCS7_MCS4_Jaguar2 0x1830
|
||||
#define rTxAGC_C_MCS11_MCS8_Jaguar2 0x1834
|
||||
#define rTxAGC_C_MCS15_MCS12_Jaguar2 0x1838
|
||||
#define rTxAGC_C_MCS19_MCS16_Jaguar2 0x18d8
|
||||
#define rTxAGC_C_MCS23_MCS20_Jaguar2 0x18dc
|
||||
#define rTxAGC_C_Nss1Index3_Nss1Index0_Jaguar2 0x183c
|
||||
#define rTxAGC_C_Nss1Index7_Nss1Index4_Jaguar2 0x1840
|
||||
#define rTxAGC_C_Nss2Index1_Nss1Index8_Jaguar2 0x1844
|
||||
#define rTxAGC_C_Nss2Index5_Nss2Index2_Jaguar2 0x1848
|
||||
#define rTxAGC_C_Nss2Index9_Nss2Index6_Jaguar2 0x184c
|
||||
#define rTxAGC_C_Nss3Index3_Nss3Index0_Jaguar2 0x18e0
|
||||
#define rTxAGC_C_Nss3Index7_Nss3Index4_Jaguar2 0x18e4
|
||||
#define rTxAGC_C_Nss3Index9_Nss3Index8_Jaguar2 0x18e8
|
||||
#define rTxAGC_D_CCK11_CCK1_Jaguar2 0x1a20
|
||||
#define rTxAGC_D_Ofdm18_Ofdm6_Jaguar2 0x1a24
|
||||
#define rTxAGC_D_Ofdm54_Ofdm24_Jaguar2 0x1a28
|
||||
#define rTxAGC_D_MCS3_MCS0_Jaguar2 0x1a2c
|
||||
#define rTxAGC_D_MCS7_MCS4_Jaguar2 0x1a30
|
||||
#define rTxAGC_D_MCS11_MCS8_Jaguar2 0x1a34
|
||||
#define rTxAGC_D_MCS15_MCS12_Jaguar2 0x1a38
|
||||
#define rTxAGC_D_MCS19_MCS16_Jaguar2 0x1ad8
|
||||
#define rTxAGC_D_MCS23_MCS20_Jaguar2 0x1adc
|
||||
#define rTxAGC_D_Nss1Index3_Nss1Index0_Jaguar2 0x1a3c
|
||||
#define rTxAGC_D_Nss1Index7_Nss1Index4_Jaguar2 0x1a40
|
||||
#define rTxAGC_D_Nss2Index1_Nss1Index8_Jaguar2 0x1a44
|
||||
#define rTxAGC_D_Nss2Index5_Nss2Index2_Jaguar2 0x1a48
|
||||
#define rTxAGC_D_Nss2Index9_Nss2Index6_Jaguar2 0x1a4c
|
||||
#define rTxAGC_D_Nss3Index3_Nss3Index0_Jaguar2 0x1ae0
|
||||
#define rTxAGC_D_Nss3Index7_Nss3Index4_Jaguar2 0x1ae4
|
||||
#define rTxAGC_D_Nss3Index9_Nss3Index8_Jaguar2 0x1ae8
|
||||
/* IQK YN: temporaily mask this part
|
||||
* #define rFPGA0_IQK 0xe28
|
||||
* #define rTx_IQK_Tone_A 0xe30
|
||||
* #define rRx_IQK_Tone_A 0xe34
|
||||
* #define rTx_IQK_PI_A 0xe38
|
||||
* #define rRx_IQK_PI_A 0xe3c */
|
||||
|
||||
/* #define rTx_IQK 0xe40 */
|
||||
/* #define rRx_IQK 0xe44 */
|
||||
/* #define rIQK_AGC_Pts 0xe48 */
|
||||
/* #define rIQK_AGC_Rsp 0xe4c */
|
||||
/* #define rTx_IQK_Tone_B 0xe50 */
|
||||
/* #define rRx_IQK_Tone_B 0xe54 */
|
||||
/* #define rTx_IQK_PI_B 0xe58 */
|
||||
/* #define rRx_IQK_PI_B 0xe5c */
|
||||
/* #define rIQK_AGC_Cont 0xe60 */
|
||||
|
||||
|
||||
/* AFE-related */
|
||||
#define rA_AFEPwr1_Jaguar 0xc60 /* dynamic AFE power control */
|
||||
#define rA_AFEPwr2_Jaguar 0xc64 /* dynamic AFE power control */
|
||||
#define rA_Rx_WaitCCA_Tx_CCKRFON_Jaguar 0xc68
|
||||
#define rA_Tx_CCKBBON_OFDMRFON_Jaguar 0xc6c
|
||||
#define rA_Tx_OFDMBBON_Tx2Rx_Jaguar 0xc70
|
||||
#define rA_Tx2Tx_RXCCK_Jaguar 0xc74
|
||||
#define rA_Rx_OFDM_WaitRIFS_Jaguar 0xc78
|
||||
#define rA_Rx2Rx_BT_Jaguar 0xc7c
|
||||
#define rA_sleep_nav_Jaguar 0xc80
|
||||
#define rA_pmpd_Jaguar 0xc84
|
||||
#define rB_AFEPwr1_Jaguar 0xe60 /* dynamic AFE power control */
|
||||
#define rB_AFEPwr2_Jaguar 0xe64 /* dynamic AFE power control */
|
||||
#define rB_Rx_WaitCCA_Tx_CCKRFON_Jaguar 0xe68
|
||||
#define rB_Tx_CCKBBON_OFDMRFON_Jaguar 0xe6c
|
||||
#define rB_Tx_OFDMBBON_Tx2Rx_Jaguar 0xe70
|
||||
#define rB_Tx2Tx_RXCCK_Jaguar 0xe74
|
||||
#define rB_Rx_OFDM_WaitRIFS_Jaguar 0xe78
|
||||
#define rB_Rx2Rx_BT_Jaguar 0xe7c
|
||||
#define rB_sleep_nav_Jaguar 0xe80
|
||||
#define rB_pmpd_Jaguar 0xe84
|
||||
|
||||
|
||||
/* YN: mask these registers temporaily
|
||||
* #define rTx_Power_Before_IQK_A 0xe94
|
||||
* #define rTx_Power_After_IQK_A 0xe9c */
|
||||
|
||||
/* #define rRx_Power_Before_IQK_A 0xea0 */
|
||||
/* #define rRx_Power_Before_IQK_A_2 0xea4 */
|
||||
/* #define rRx_Power_After_IQK_A 0xea8 */
|
||||
/* #define rRx_Power_After_IQK_A_2 0xeac */
|
||||
|
||||
/* #define rTx_Power_Before_IQK_B 0xeb4 */
|
||||
/* #define rTx_Power_After_IQK_B 0xebc */
|
||||
|
||||
/* #define rRx_Power_Before_IQK_B 0xec0 */
|
||||
/* #define rRx_Power_Before_IQK_B_2 0xec4 */
|
||||
/* #define rRx_Power_After_IQK_B 0xec8 */
|
||||
/* #define rRx_Power_After_IQK_B_2 0xecc */
|
||||
|
||||
|
||||
/* RSSI Dump */
|
||||
#define rA_RSSIDump_Jaguar 0xBF0
|
||||
#define rB_RSSIDump_Jaguar 0xBF1
|
||||
#define rS1_RXevmDump_Jaguar 0xBF4
|
||||
#define rS2_RXevmDump_Jaguar 0xBF5
|
||||
#define rA_RXsnrDump_Jaguar 0xBF6
|
||||
#define rB_RXsnrDump_Jaguar 0xBF7
|
||||
#define rA_CfoShortDump_Jaguar 0xBF8
|
||||
#define rB_CfoShortDump_Jaguar 0xBFA
|
||||
#define rA_CfoLongDump_Jaguar 0xBEC
|
||||
#define rB_CfoLongDump_Jaguar 0xBEE
|
||||
|
||||
|
||||
/* RF Register
|
||||
* */
|
||||
#define RF_AC_Jaguar 0x00 /* */
|
||||
#define RF_RF_Top_Jaguar 0x07 /* */
|
||||
#define RF_TXLOK_Jaguar 0x08 /* */
|
||||
#define RF_TXAPK_Jaguar 0x0B
|
||||
#define RF_CHNLBW_Jaguar 0x18 /* RF channel and BW switch */
|
||||
#define RF_RCK1_Jaguar 0x1c /* */
|
||||
#define RF_RCK2_Jaguar 0x1d
|
||||
#define RF_RCK3_Jaguar 0x1e
|
||||
#define RF_ModeTableAddr 0x30
|
||||
#define RF_ModeTableData0 0x31
|
||||
#define RF_ModeTableData1 0x32
|
||||
#define RF_TxLCTank_Jaguar 0x54
|
||||
#define RF_APK_Jaguar 0x63
|
||||
#define RF_LCK 0xB4
|
||||
#define RF_WeLut_Jaguar 0xEF
|
||||
|
||||
#define bRF_CHNLBW_MOD_AG_Jaguar 0x70300
|
||||
#define bRF_CHNLBW_BW 0xc00
|
||||
|
||||
|
||||
/*
|
||||
* RL6052 Register definition
|
||||
* */
|
||||
#define RF_AC 0x00 /* */
|
||||
#define RF_IPA_A 0x0C /* */
|
||||
#define RF_TXBIAS_A 0x0D
|
||||
#define RF_BS_PA_APSET_G9_G11 0x0E
|
||||
#define RF_MODE1 0x10 /* */
|
||||
#define RF_MODE2 0x11 /* */
|
||||
#define RF_CHNLBW 0x18 /* RF channel and BW switch */
|
||||
#define RF_RCK_OS 0x30 /* RF TX PA control */
|
||||
#define RF_TXPA_G1 0x31 /* RF TX PA control */
|
||||
#define RF_TXPA_G2 0x32 /* RF TX PA control */
|
||||
#define RF_TXPA_G3 0x33 /* RF TX PA control */
|
||||
#define RF_0x52 0x52
|
||||
#define RF_WE_LUT 0xEF
|
||||
|
||||
/*
|
||||
* Bit Mask
|
||||
*
|
||||
* 1. Page1(0x100) */
|
||||
#define bBBResetB 0x100 /* Useless now? */
|
||||
#define bGlobalResetB 0x200
|
||||
#define bOFDMTxStart 0x4
|
||||
#define bCCKTxStart 0x8
|
||||
#define bCRC32Debug 0x100
|
||||
#define bPMACLoopback 0x10
|
||||
#define bTxLSIG 0xffffff
|
||||
#define bOFDMTxRate 0xf
|
||||
#define bOFDMTxReserved 0x10
|
||||
#define bOFDMTxLength 0x1ffe0
|
||||
#define bOFDMTxParity 0x20000
|
||||
#define bTxHTSIG1 0xffffff
|
||||
#define bTxHTMCSRate 0x7f
|
||||
#define bTxHTBW 0x80
|
||||
#define bTxHTLength 0xffff00
|
||||
#define bTxHTSIG2 0xffffff
|
||||
#define bTxHTSmoothing 0x1
|
||||
#define bTxHTSounding 0x2
|
||||
#define bTxHTReserved 0x4
|
||||
#define bTxHTAggreation 0x8
|
||||
#define bTxHTSTBC 0x30
|
||||
#define bTxHTAdvanceCoding 0x40
|
||||
#define bTxHTShortGI 0x80
|
||||
#define bTxHTNumberHT_LTF 0x300
|
||||
#define bTxHTCRC8 0x3fc00
|
||||
#define bCounterReset 0x10000
|
||||
#define bNumOfOFDMTx 0xffff
|
||||
#define bNumOfCCKTx 0xffff0000
|
||||
#define bTxIdleInterval 0xffff
|
||||
#define bOFDMService 0xffff0000
|
||||
#define bTxMACHeader 0xffffffff
|
||||
#define bTxDataInit 0xff
|
||||
#define bTxHTMode 0x100
|
||||
#define bTxDataType 0x30000
|
||||
#define bTxRandomSeed 0xffffffff
|
||||
#define bCCKTxPreamble 0x1
|
||||
#define bCCKTxSFD 0xffff0000
|
||||
#define bCCKTxSIG 0xff
|
||||
#define bCCKTxService 0xff00
|
||||
#define bCCKLengthExt 0x8000
|
||||
#define bCCKTxLength 0xffff0000
|
||||
#define bCCKTxCRC16 0xffff
|
||||
#define bCCKTxStatus 0x1
|
||||
#define bOFDMTxStatus 0x2
|
||||
|
||||
|
||||
/*
|
||||
* 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
|
||||
* 1. Page1(0x100)
|
||||
* */
|
||||
#define rPMAC_Reset 0x100
|
||||
#define rPMAC_TxStart 0x104
|
||||
#define rPMAC_TxLegacySIG 0x108
|
||||
#define rPMAC_TxHTSIG1 0x10c
|
||||
#define rPMAC_TxHTSIG2 0x110
|
||||
#define rPMAC_PHYDebug 0x114
|
||||
#define rPMAC_TxPacketNum 0x118
|
||||
#define rPMAC_TxIdle 0x11c
|
||||
#define rPMAC_TxMACHeader0 0x120
|
||||
#define rPMAC_TxMACHeader1 0x124
|
||||
#define rPMAC_TxMACHeader2 0x128
|
||||
#define rPMAC_TxMACHeader3 0x12c
|
||||
#define rPMAC_TxMACHeader4 0x130
|
||||
#define rPMAC_TxMACHeader5 0x134
|
||||
#define rPMAC_TxDataType 0x138
|
||||
#define rPMAC_TxRandomSeed 0x13c
|
||||
#define rPMAC_CCKPLCPPreamble 0x140
|
||||
#define rPMAC_CCKPLCPHeader 0x144
|
||||
#define rPMAC_CCKCRC16 0x148
|
||||
#define rPMAC_OFDMRxCRC32OK 0x170
|
||||
#define rPMAC_OFDMRxCRC32Er 0x174
|
||||
#define rPMAC_OFDMRxParityEr 0x178
|
||||
#define rPMAC_OFDMRxCRC8Er 0x17c
|
||||
#define rPMAC_CCKCRxRC16Er 0x180
|
||||
#define rPMAC_CCKCRxRC32Er 0x184
|
||||
#define rPMAC_CCKCRxRC32OK 0x188
|
||||
#define rPMAC_TxStatus 0x18c
|
||||
|
||||
/*
|
||||
* 3. Page8(0x800)
|
||||
* */
|
||||
#define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC */ /* RF BW Setting?? */
|
||||
|
||||
#define rFPGA0_TxInfo 0x804 /* Status report?? */
|
||||
#define rFPGA0_PSDFunction 0x808
|
||||
#define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */
|
||||
|
||||
#define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */
|
||||
#define rFPGA0_XA_HSSIParameter2 0x824
|
||||
#define rFPGA0_XB_HSSIParameter1 0x828
|
||||
#define rFPGA0_XB_HSSIParameter2 0x82c
|
||||
|
||||
#define rFPGA0_XA_LSSIParameter 0x840
|
||||
#define rFPGA0_XB_LSSIParameter 0x844
|
||||
|
||||
#define rFPGA0_XAB_SwitchControl 0x858 /* RF Channel switch */
|
||||
#define rFPGA0_XCD_SwitchControl 0x85c
|
||||
|
||||
#define rFPGA0_XAB_RFParameter 0x878 /* RF Parameter */
|
||||
#define rFPGA0_XCD_RFParameter 0x87c
|
||||
|
||||
#define rFPGA0_AnalogParameter1 0x880 /* Crystal cap setting RF-R/W protection for parameter4?? */
|
||||
#define rFPGA0_AnalogParameter2 0x884
|
||||
#define rFPGA0_AnalogParameter3 0x888
|
||||
#define rFPGA0_AdDaClockEn 0x888 /* enable ad/da clock1 for dual-phy */
|
||||
#define rFPGA0_AnalogParameter4 0x88c
|
||||
|
||||
#define rFPGA0_XA_LSSIReadBack 0x8a0 /* Tranceiver LSSI Readback */
|
||||
#define rFPGA0_XB_LSSIReadBack 0x8a4
|
||||
#define rFPGA0_XC_LSSIReadBack 0x8a8
|
||||
#define rFPGA0_XD_LSSIReadBack 0x8ac
|
||||
|
||||
#define rFPGA0_XCD_RFPara 0x8b4
|
||||
#define rFPGA0_PSDReport 0x8b4 /* Useless now */
|
||||
#define TransceiverA_HSPI_Readback 0x8b8 /* Transceiver A HSPI Readback */
|
||||
#define TransceiverB_HSPI_Readback 0x8bc /* Transceiver B HSPI Readback */
|
||||
#define rFPGA0_XAB_RFInterfaceRB 0x8e0 /* Useless now */ /* RF Interface Readback Value */
|
||||
#define rFPGA0_XCD_RFInterfaceRB 0x8e4 /* Useless now */
|
||||
|
||||
/*
|
||||
* 4. Page9(0x900)
|
||||
* */
|
||||
#define rFPGA1_RFMOD 0x900 /* RF mode & OFDM TxSC */ /* RF BW Setting?? */
|
||||
#define REG_BB_TX_PATH_SEL_1_8814A 0x93c
|
||||
#define REG_BB_TX_PATH_SEL_2_8814A 0x940
|
||||
#define rFPGA1_TxBlock 0x904 /* Useless now */
|
||||
#define rFPGA1_DebugSelect 0x908 /* Useless now */
|
||||
#define rFPGA1_TxInfo 0x90c /* Useless now */ /* Status report?? */
|
||||
/*Page 19 for TxBF*/
|
||||
#define REG_BB_TXBF_ANT_SET_BF1_8814A 0x19ac
|
||||
#define REG_BB_TXBF_ANT_SET_BF0_8814A 0x19b4
|
||||
/*
|
||||
* PageA(0xA00)
|
||||
* */
|
||||
#define rCCK0_System 0xa00
|
||||
#define rCCK0_AFESetting 0xa04 /* Disable init gain now */ /* Select RX path by RSSI */
|
||||
#define rCCK0_DSPParameter2 0xa1c /* SQ threshold */
|
||||
#define rCCK0_TxFilter1 0xa20
|
||||
#define rCCK0_TxFilter2 0xa24
|
||||
#define rCCK0_DebugPort 0xa28 /* debug port and Tx filter3 */
|
||||
#define rCCK0_FalseAlarmReport 0xa2c /* 0xa2d useless now 0xa30-a4f channel report */
|
||||
|
||||
/*
|
||||
* PageB(0xB00)
|
||||
* */
|
||||
#define rPdp_AntA 0xb00
|
||||
#define rPdp_AntA_4 0xb04
|
||||
#define rConfig_Pmpd_AntA 0xb28
|
||||
#define rConfig_AntA 0xb68
|
||||
#define rConfig_AntB 0xb6c
|
||||
#define rPdp_AntB 0xb70
|
||||
#define rPdp_AntB_4 0xb74
|
||||
#define rConfig_Pmpd_AntB 0xb98
|
||||
#define rAPK 0xbd8
|
||||
|
||||
/*
|
||||
* 6. PageC(0xC00)
|
||||
* */
|
||||
#define rOFDM0_LSTF 0xc00
|
||||
|
||||
#define rOFDM0_TRxPathEnable 0xc04
|
||||
#define rOFDM0_TRMuxPar 0xc08
|
||||
#define rOFDM0_TRSWIsolation 0xc0c
|
||||
|
||||
#define rOFDM0_XARxAFE 0xc10 /* RxIQ DC offset, Rx digital filter, DC notch filter */
|
||||
#define rOFDM0_XARxIQImbalance 0xc14 /* RxIQ imblance matrix */
|
||||
#define rOFDM0_XBRxAFE 0xc18
|
||||
#define rOFDM0_XBRxIQImbalance 0xc1c
|
||||
#define rOFDM0_XCRxAFE 0xc20
|
||||
#define rOFDM0_XCRxIQImbalance 0xc24
|
||||
#define rOFDM0_XDRxAFE 0xc28
|
||||
#define rOFDM0_XDRxIQImbalance 0xc2c
|
||||
|
||||
#define rOFDM0_RxDetector1 0xc30 /* PD, BW & SBD */ /* DM tune init gain */
|
||||
#define rOFDM0_RxDetector2 0xc34 /* SBD & Fame Sync. */
|
||||
#define rOFDM0_RxDetector3 0xc38 /* Frame Sync. */
|
||||
#define rOFDM0_RxDetector4 0xc3c /* PD, SBD, Frame Sync & Short-GI */
|
||||
|
||||
#define rOFDM0_RxDSP 0xc40 /* Rx Sync Path */
|
||||
#define rOFDM0_CFOandDAGC 0xc44 /* CFO & DAGC */
|
||||
#define rOFDM0_CCADropThreshold 0xc48 /* CCA Drop threshold */
|
||||
#define rOFDM0_ECCAThreshold 0xc4c /* energy CCA */
|
||||
|
||||
#define rOFDM0_XAAGCCore1 0xc50 /* DIG */
|
||||
#define rOFDM0_XAAGCCore2 0xc54
|
||||
#define rOFDM0_XBAGCCore1 0xc58
|
||||
#define rOFDM0_XBAGCCore2 0xc5c
|
||||
#define rOFDM0_XCAGCCore1 0xc60
|
||||
#define rOFDM0_XCAGCCore2 0xc64
|
||||
#define rOFDM0_XDAGCCore1 0xc68
|
||||
#define rOFDM0_XDAGCCore2 0xc6c
|
||||
|
||||
#define rOFDM0_AGCParameter1 0xc70
|
||||
#define rOFDM0_AGCParameter2 0xc74
|
||||
#define rOFDM0_AGCRSSITable 0xc78
|
||||
#define rOFDM0_HTSTFAGC 0xc7c
|
||||
|
||||
#define rOFDM0_XATxIQImbalance 0xc80 /* TX PWR TRACK and DIG */
|
||||
#define rOFDM0_XATxAFE 0xc84
|
||||
#define rOFDM0_XBTxIQImbalance 0xc88
|
||||
#define rOFDM0_XBTxAFE 0xc8c
|
||||
#define rOFDM0_XCTxIQImbalance 0xc90
|
||||
#define rOFDM0_XCTxAFE 0xc94
|
||||
#define rOFDM0_XDTxIQImbalance 0xc98
|
||||
#define rOFDM0_XDTxAFE 0xc9c
|
||||
|
||||
#define rOFDM0_RxIQExtAnta 0xca0
|
||||
#define rOFDM0_TxCoeff1 0xca4
|
||||
#define rOFDM0_TxCoeff2 0xca8
|
||||
#define rOFDM0_TxCoeff3 0xcac
|
||||
#define rOFDM0_TxCoeff4 0xcb0
|
||||
#define rOFDM0_TxCoeff5 0xcb4
|
||||
#define rOFDM0_TxCoeff6 0xcb8
|
||||
#define rOFDM0_RxHPParameter 0xce0
|
||||
#define rOFDM0_TxPseudoNoiseWgt 0xce4
|
||||
#define rOFDM0_FrameSync 0xcf0
|
||||
#define rOFDM0_DFSReport 0xcf4
|
||||
|
||||
/*
|
||||
* 7. PageD(0xD00)
|
||||
* */
|
||||
#define rOFDM1_LSTF 0xd00
|
||||
#define rOFDM1_TRxPathEnable 0xd04
|
||||
|
||||
/*
|
||||
* 8. PageE(0xE00)
|
||||
* */
|
||||
#define rTxAGC_A_Rate18_06 0xe00
|
||||
#define rTxAGC_A_Rate54_24 0xe04
|
||||
#define rTxAGC_A_CCK1_Mcs32 0xe08
|
||||
#define rTxAGC_A_Mcs03_Mcs00 0xe10
|
||||
#define rTxAGC_A_Mcs07_Mcs04 0xe14
|
||||
#define rTxAGC_A_Mcs11_Mcs08 0xe18
|
||||
#define rTxAGC_A_Mcs15_Mcs12 0xe1c
|
||||
|
||||
#define rTxAGC_B_Rate18_06 0x830
|
||||
#define rTxAGC_B_Rate54_24 0x834
|
||||
#define rTxAGC_B_CCK1_55_Mcs32 0x838
|
||||
#define rTxAGC_B_Mcs03_Mcs00 0x83c
|
||||
#define rTxAGC_B_Mcs07_Mcs04 0x848
|
||||
#define rTxAGC_B_Mcs11_Mcs08 0x84c
|
||||
#define rTxAGC_B_Mcs15_Mcs12 0x868
|
||||
#define rTxAGC_B_CCK11_A_CCK2_11 0x86c
|
||||
|
||||
#define rFPGA0_IQK 0xe28
|
||||
#define rTx_IQK_Tone_A 0xe30
|
||||
#define rRx_IQK_Tone_A 0xe34
|
||||
#define rTx_IQK_PI_A 0xe38
|
||||
#define rRx_IQK_PI_A 0xe3c
|
||||
|
||||
#define rTx_IQK 0xe40
|
||||
#define rRx_IQK 0xe44
|
||||
#define rIQK_AGC_Pts 0xe48
|
||||
#define rIQK_AGC_Rsp 0xe4c
|
||||
#define rTx_IQK_Tone_B 0xe50
|
||||
#define rRx_IQK_Tone_B 0xe54
|
||||
#define rTx_IQK_PI_B 0xe58
|
||||
#define rRx_IQK_PI_B 0xe5c
|
||||
#define rIQK_AGC_Cont 0xe60
|
||||
|
||||
#define rBlue_Tooth 0xe6c
|
||||
#define rRx_Wait_CCA 0xe70
|
||||
#define rTx_CCK_RFON 0xe74
|
||||
#define rTx_CCK_BBON 0xe78
|
||||
#define rTx_OFDM_RFON 0xe7c
|
||||
#define rTx_OFDM_BBON 0xe80
|
||||
#define rTx_To_Rx 0xe84
|
||||
#define rTx_To_Tx 0xe88
|
||||
#define rRx_CCK 0xe8c
|
||||
|
||||
#define rTx_Power_Before_IQK_A 0xe94
|
||||
#define rTx_Power_After_IQK_A 0xe9c
|
||||
|
||||
#define rRx_Power_Before_IQK_A 0xea0
|
||||
#define rRx_Power_Before_IQK_A_2 0xea4
|
||||
#define rRx_Power_After_IQK_A 0xea8
|
||||
#define rRx_Power_After_IQK_A_2 0xeac
|
||||
|
||||
#define rTx_Power_Before_IQK_B 0xeb4
|
||||
#define rTx_Power_After_IQK_B 0xebc
|
||||
|
||||
#define rRx_Power_Before_IQK_B 0xec0
|
||||
#define rRx_Power_Before_IQK_B_2 0xec4
|
||||
#define rRx_Power_After_IQK_B 0xec8
|
||||
#define rRx_Power_After_IQK_B_2 0xecc
|
||||
|
||||
#define rRx_OFDM 0xed0
|
||||
#define rRx_Wait_RIFS 0xed4
|
||||
#define rRx_TO_Rx 0xed8
|
||||
#define rStandby 0xedc
|
||||
#define rSleep 0xee0
|
||||
#define rPMPD_ANAEN 0xeec
|
||||
|
||||
|
||||
/* 2. Page8(0x800) */
|
||||
#define bRFMOD 0x1 /* Reg 0x800 rFPGA0_RFMOD */
|
||||
#define bJapanMode 0x2
|
||||
#define bCCKTxSC 0x30
|
||||
#define bCCKEn 0x1000000
|
||||
#define bOFDMEn 0x2000000
|
||||
#define bXBTxAGC 0xf00 /* Reg 80c rFPGA0_TxGainStage */
|
||||
#define bXCTxAGC 0xf000
|
||||
#define bXDTxAGC 0xf0000
|
||||
|
||||
/* 4. PageA(0xA00) */
|
||||
#define bCCKBBMode 0x3 /* Useless */
|
||||
#define bCCKTxPowerSaving 0x80
|
||||
#define bCCKRxPowerSaving 0x40
|
||||
|
||||
#define bCCKSideBand 0x10 /* Reg 0xa00 rCCK0_System 20/40 switch */
|
||||
|
||||
#define bCCKScramble 0x8 /* Useless */
|
||||
#define bCCKAntDiversity 0x8000
|
||||
#define bCCKCarrierRecovery 0x4000
|
||||
#define bCCKTxRate 0x3000
|
||||
#define bCCKDCCancel 0x0800
|
||||
#define bCCKISICancel 0x0400
|
||||
#define bCCKMatchFilter 0x0200
|
||||
#define bCCKEqualizer 0x0100
|
||||
#define bCCKPreambleDetect 0x800000
|
||||
#define bCCKFastFalseCCA 0x400000
|
||||
#define bCCKChEstStart 0x300000
|
||||
#define bCCKCCACount 0x080000
|
||||
#define bCCKcs_lim 0x070000
|
||||
#define bCCKBistMode 0x80000000
|
||||
#define bCCKCCAMask 0x40000000
|
||||
#define bCCKTxDACPhase 0x4
|
||||
#define bCCKRxADCPhase 0x20000000 /* r_rx_clk */
|
||||
#define bCCKr_cp_mode0 0x0100
|
||||
#define bCCKTxDCOffset 0xf0
|
||||
#define bCCKRxDCOffset 0xf
|
||||
#define bCCKCCAMode 0xc000
|
||||
#define bCCKFalseCS_lim 0x3f00
|
||||
#define bCCKCS_ratio 0xc00000
|
||||
#define bCCKCorgBit_sel 0x300000
|
||||
#define bCCKPD_lim 0x0f0000
|
||||
#define bCCKNewCCA 0x80000000
|
||||
#define bCCKRxHPofIG 0x8000
|
||||
#define bCCKRxIG 0x7f00
|
||||
#define bCCKLNAPolarity 0x800000
|
||||
#define bCCKRx1stGain 0x7f0000
|
||||
#define bCCKRFExtend 0x20000000 /* CCK Rx Iinital gain polarity */
|
||||
#define bCCKRxAGCSatLevel 0x1f000000
|
||||
#define bCCKRxAGCSatCount 0xe0
|
||||
#define bCCKRxRFSettle 0x1f /* AGCsamp_dly */
|
||||
#define bCCKFixedRxAGC 0x8000
|
||||
/* #define bCCKRxAGCFormat 0x4000 */ /* remove to HSSI register 0x824 */
|
||||
#define bCCKAntennaPolarity 0x2000
|
||||
#define bCCKTxFilterType 0x0c00
|
||||
#define bCCKRxAGCReportType 0x0300
|
||||
#define bCCKRxDAGCEn 0x80000000
|
||||
#define bCCKRxDAGCPeriod 0x20000000
|
||||
#define bCCKRxDAGCSatLevel 0x1f000000
|
||||
#define bCCKTimingRecovery 0x800000
|
||||
#define bCCKTxC0 0x3f0000
|
||||
#define bCCKTxC1 0x3f000000
|
||||
#define bCCKTxC2 0x3f
|
||||
#define bCCKTxC3 0x3f00
|
||||
#define bCCKTxC4 0x3f0000
|
||||
#define bCCKTxC5 0x3f000000
|
||||
#define bCCKTxC6 0x3f
|
||||
#define bCCKTxC7 0x3f00
|
||||
#define bCCKDebugPort 0xff0000
|
||||
#define bCCKDACDebug 0x0f000000
|
||||
#define bCCKFalseAlarmEnable 0x8000
|
||||
#define bCCKFalseAlarmRead 0x4000
|
||||
#define bCCKTRSSI 0x7f
|
||||
#define bCCKRxAGCReport 0xfe
|
||||
#define bCCKRxReport_AntSel 0x80000000
|
||||
#define bCCKRxReport_MFOff 0x40000000
|
||||
#define bCCKRxRxReport_SQLoss 0x20000000
|
||||
#define bCCKRxReport_Pktloss 0x10000000
|
||||
#define bCCKRxReport_Lockedbit 0x08000000
|
||||
#define bCCKRxReport_RateError 0x04000000
|
||||
#define bCCKRxReport_RxRate 0x03000000
|
||||
#define bCCKRxFACounterLower 0xff
|
||||
#define bCCKRxFACounterUpper 0xff000000
|
||||
#define bCCKRxHPAGCStart 0xe000
|
||||
#define bCCKRxHPAGCFinal 0x1c00
|
||||
#define bCCKRxFalseAlarmEnable 0x8000
|
||||
#define bCCKFACounterFreeze 0x4000
|
||||
#define bCCKTxPathSel 0x10000000
|
||||
#define bCCKDefaultRxPath 0xc000000
|
||||
#define bCCKOptionRxPath 0x3000000
|
||||
|
||||
#define RF_T_METER_88E 0x42
|
||||
|
||||
/* 6. PageE(0xE00) */
|
||||
#define bSTBCEn 0x4 /* Useless */
|
||||
#define bAntennaMapping 0x10
|
||||
#define bNss 0x20
|
||||
#define bCFOAntSumD 0x200
|
||||
#define bPHYCounterReset 0x8000000
|
||||
#define bCFOReportGet 0x4000000
|
||||
#define bOFDMContinueTx 0x10000000
|
||||
#define bOFDMSingleCarrier 0x20000000
|
||||
#define bOFDMSingleTone 0x40000000
|
||||
|
||||
|
||||
/*
|
||||
* Other Definition
|
||||
* */
|
||||
|
||||
#define bEnable 0x1 /* Useless */
|
||||
#define bDisable 0x0
|
||||
|
||||
/* byte endable for srwrite */
|
||||
#define bByte0 0x1 /* Useless */
|
||||
#define bByte1 0x2
|
||||
#define bByte2 0x4
|
||||
#define bByte3 0x8
|
||||
#define bWord0 0x3
|
||||
#define bWord1 0xc
|
||||
#define bDWord 0xf
|
||||
|
||||
/* for PutRegsetting & GetRegSetting BitMask */
|
||||
#define bMaskByte0 0xff /* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */
|
||||
#define bMaskByte1 0xff00
|
||||
#define bMaskByte2 0xff0000
|
||||
#define bMaskByte3 0xff000000
|
||||
#define bMaskHWord 0xffff0000
|
||||
#define bMaskLWord 0x0000ffff
|
||||
#define bMaskDWord 0xffffffff
|
||||
#define bMaskH3Bytes 0xffffff00
|
||||
#define bMask12Bits 0xfff
|
||||
#define bMaskH4Bits 0xf0000000
|
||||
#define bMaskOFDM_D 0xffc00000
|
||||
#define bMaskCCK 0x3f3f3f3f
|
||||
#define bMask7bits 0x7f
|
||||
#define bMaskByte2HighNibble 0x00f00000
|
||||
#define bMaskByte3LowNibble 0x0f000000
|
||||
#define bMaskL3Bytes 0x00ffffff
|
||||
|
||||
/*--------------------------Define Parameters-------------------------------*/
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,87 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#include "Hal8814PwrSeq.h"
|
||||
/* devourer adaptation: upstream pulls rtl8814a_hal.h here for incidental
|
||||
* typedefs that this file doesn't actually use. Skipping the include avoids
|
||||
* dragging the full 8814 HAL include chain into the build for what is in
|
||||
* essence just data. The WLAN_PWR_CFG struct + RTL8814A_TRANS_* macros come
|
||||
* from Hal8814PwrSeq.h / HalPwrSeqCmd.h. */
|
||||
|
||||
/*
|
||||
drivers should parse below arrays and do the corresponding actions
|
||||
*/
|
||||
/* 3 Power on Array */
|
||||
WLAN_PWR_CFG rtl8814A_power_on_flow[RTL8814A_TRANS_CARDEMU_TO_ACT_STEPS + RTL8814A_TRANS_END_STEPS] = {
|
||||
RTL8814A_TRANS_CARDEMU_TO_ACT
|
||||
RTL8814A_TRANS_END
|
||||
};
|
||||
|
||||
/* 3Radio off GPIO Array */
|
||||
WLAN_PWR_CFG rtl8814A_radio_off_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8814A_TRANS_END_STEPS] = {
|
||||
RTL8814A_TRANS_ACT_TO_CARDEMU
|
||||
RTL8814A_TRANS_END
|
||||
};
|
||||
|
||||
/* 3Card Disable Array */
|
||||
WLAN_PWR_CFG rtl8814A_card_disable_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8814A_TRANS_CARDEMU_TO_PDN_STEPS + RTL8814A_TRANS_END_STEPS] = {
|
||||
RTL8814A_TRANS_ACT_TO_CARDEMU
|
||||
RTL8814A_TRANS_CARDEMU_TO_CARDDIS
|
||||
RTL8814A_TRANS_END
|
||||
};
|
||||
|
||||
/* 3 Card Enable Array */
|
||||
WLAN_PWR_CFG rtl8814A_card_enable_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8814A_TRANS_CARDEMU_TO_PDN_STEPS + RTL8814A_TRANS_END_STEPS] = {
|
||||
RTL8814A_TRANS_CARDDIS_TO_CARDEMU
|
||||
RTL8814A_TRANS_CARDEMU_TO_ACT
|
||||
RTL8814A_TRANS_END
|
||||
};
|
||||
|
||||
/* 3Suspend Array */
|
||||
WLAN_PWR_CFG rtl8814A_suspend_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8814A_TRANS_CARDEMU_TO_SUS_STEPS + RTL8814A_TRANS_END_STEPS] = {
|
||||
RTL8814A_TRANS_ACT_TO_CARDEMU
|
||||
RTL8814A_TRANS_CARDEMU_TO_SUS
|
||||
RTL8814A_TRANS_END
|
||||
};
|
||||
|
||||
/* 3 Resume Array */
|
||||
WLAN_PWR_CFG rtl8814A_resume_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8814A_TRANS_CARDEMU_TO_SUS_STEPS + RTL8814A_TRANS_END_STEPS] = {
|
||||
RTL8814A_TRANS_SUS_TO_CARDEMU
|
||||
RTL8814A_TRANS_CARDEMU_TO_ACT
|
||||
RTL8814A_TRANS_END
|
||||
};
|
||||
|
||||
|
||||
|
||||
/* 3HWPDN Array */
|
||||
WLAN_PWR_CFG rtl8814A_hwpdn_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8814A_TRANS_CARDEMU_TO_PDN_STEPS + RTL8814A_TRANS_END_STEPS] = {
|
||||
RTL8814A_TRANS_ACT_TO_CARDEMU
|
||||
RTL8814A_TRANS_CARDEMU_TO_PDN
|
||||
RTL8814A_TRANS_END
|
||||
};
|
||||
|
||||
/* 3 Enter LPS */
|
||||
WLAN_PWR_CFG rtl8814A_enter_lps_flow[RTL8814A_TRANS_ACT_TO_LPS_STEPS + RTL8814A_TRANS_END_STEPS] = {
|
||||
/* FW behavior */
|
||||
RTL8814A_TRANS_ACT_TO_LPS
|
||||
RTL8814A_TRANS_END
|
||||
};
|
||||
|
||||
/* 3 Leave LPS */
|
||||
WLAN_PWR_CFG rtl8814A_leave_lps_flow[RTL8814A_TRANS_LPS_TO_ACT_STEPS + RTL8814A_TRANS_END_STEPS] = {
|
||||
/* FW behavior */
|
||||
RTL8814A_TRANS_LPS_TO_ACT
|
||||
RTL8814A_TRANS_END
|
||||
};
|
||||
@@ -0,0 +1,231 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
|
||||
#ifndef __HAL8814PWRSEQ_H__
|
||||
#define __HAL8814PWRSEQ_H__
|
||||
|
||||
#include "HalPwrSeqCmd.h"
|
||||
|
||||
/*
|
||||
Check document WB-110628-DZ-RTL8195 (Jaguar) Power Architecture-R04.pdf
|
||||
There are 6 HW Power States:
|
||||
0: POFF--Power Off
|
||||
1: PDN--Power Down
|
||||
2: CARDEMU--Card Emulation
|
||||
3: ACT--Active Mode
|
||||
4: LPS--Low Power State
|
||||
5: SUS--Suspend
|
||||
|
||||
The transision from different states are defined below
|
||||
TRANS_CARDEMU_TO_ACT
|
||||
TRANS_ACT_TO_CARDEMU
|
||||
TRANS_CARDEMU_TO_SUS
|
||||
TRANS_SUS_TO_CARDEMU
|
||||
TRANS_CARDEMU_TO_PDN
|
||||
TRANS_ACT_TO_LPS
|
||||
TRANS_LPS_TO_ACT
|
||||
|
||||
TRANS_END
|
||||
*/
|
||||
#define RTL8814A_TRANS_CARDEMU_TO_ACT_STEPS 16
|
||||
#define RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS 20
|
||||
#define RTL8814A_TRANS_CARDEMU_TO_SUS_STEPS 17
|
||||
#define RTL8814A_TRANS_SUS_TO_CARDEMU_STEPS 15
|
||||
#define RTL8814A_TRANS_CARDEMU_TO_PDN_STEPS 17
|
||||
#define RTL8814A_TRANS_PDN_TO_CARDEMU_STEPS 16
|
||||
#define RTL8814A_TRANS_ACT_TO_LPS_STEPS 20
|
||||
#define RTL8814A_TRANS_LPS_TO_ACT_STEPS 15
|
||||
#define RTL8814A_TRANS_END_STEPS 1
|
||||
|
||||
|
||||
#define RTL8814A_TRANS_CARDEMU_TO_ACT \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/* disable SW LPS 0x04[10]=0*/ \
|
||||
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \
|
||||
{0x002B, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /* ??0x28[24]=1, enable pll phase select*/ \
|
||||
{0x0015, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT3 | BIT2 | BIT1), (BIT3 | BIT2 | BIT1)},/* 0x14[11:9]=3'b111, OCP current threshold = 1.5A */ \
|
||||
{0x002D, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x0E, 0x08},/* 0x2C[11:9]=3'b100, select lpf R3 */ \
|
||||
{0x002D, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x70, 0x50},/* 0x2C[14:12]=3'b101, select lpf Rs*/ \
|
||||
{0x007B, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, BIT6},/* 0x78[30]=1'b1, SDM order select*/ \
|
||||
/*{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0}, */ /* disable HWPDN 0x04[15]=0*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0},/* disable WL suspend*/ \
|
||||
{0x00F0, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* */ \
|
||||
{0x0081, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x30, 0x20},/* */ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},/**/
|
||||
|
||||
#define RTL8814A_TRANS_ACT_TO_CARDEMU \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0c00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xc00[7:0] = 4 turn off 3-wire */ \
|
||||
{0x0e00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xe00[7:0] = 4 turn off 3-wire */ \
|
||||
{0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /* 0x2[0] = 0 RESET BB, CLOSE RF */ \
|
||||
{0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US}, /*Delay 1us*/ \
|
||||
{0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /* Whole BB is reset*/ \
|
||||
{0x1002, (u8)(~PWR_CUT_TESTCHIP_MSK), PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /* 0x2[0] = 0 RESET BB, CLOSE RF */ \
|
||||
{0x0002, (u8)(~PWR_CUT_TESTCHIP_MSK), PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US}, /*Delay 1us*/ \
|
||||
{0x1002, (u8)(~PWR_CUT_TESTCHIP_MSK), PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /* Whole BB is reset*/ \
|
||||
{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*0x1F[7:0] = 0 turn off RF*/ \
|
||||
/*{0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},*/ /*0x4C[23] = 0x4E[7] = 0, switch DPDT_SEL_P output from register 0x65[2] */ \
|
||||
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x28}, /* 0x07[7:0] = 0x28 sps pwm mode 0x2a for BT coex*/ \
|
||||
{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x02, 0}, /*0x8[1] = 0 ANA clk = 500k */ \
|
||||
/*{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 | BIT1, 0},*/ /* 0x02[1:0] = 0 reset BB */ \
|
||||
{0x0066, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0}, /*0x66[7]=0, disable ckreq for gpio7 output SUS */ \
|
||||
{0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x41[4]=0, disable sic for gpio7 output SUS */ \
|
||||
{0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /*0x42[1]=0, disable ckout for gpio7 output SUS */ \
|
||||
{0x004e, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5}, /*0x4E[5]=1, disable LED2 for gpio7 output SUS */ \
|
||||
{0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*0x41[0]=0, disable uart for gpio7 output SUS */ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/
|
||||
|
||||
#define RTL8814A_TRANS_CARDEMU_TO_SUS \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0061, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x0F, 0x0c},\
|
||||
{0x0061, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x0F, 0x0E},\
|
||||
{0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x0F, 0x07},/* gpio11 input mode, gpio10~8 output mode */ \
|
||||
{0x0045, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio 0~7 output same value as input ?? */ \
|
||||
{0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xff},/* gpio0~7 output mode */ \
|
||||
{0x0047, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/* 0x47[7:0] = 00 gpio mode */ \
|
||||
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/* suspend option all off */ \
|
||||
{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*0x14[13] = 1 turn on ZCD */ \
|
||||
{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, BIT6},/* 0x14[14] =1 trun on ZCD */ \
|
||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4},/*0x23[4] = 1 hpon LDO sleep mode */ \
|
||||
{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*0x8[1] = 0 ANA clk = 500k */ \
|
||||
{0x0091, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xA0, 0xA0}, /* 0x91[7]=1 0x91[5]=1 , disable sps, ldo sleep mode */ \
|
||||
{0x0070, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3}, /* 0x70[3]=1 enable mainbias polling */ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3}, /*0x04[11] = 1 enable WL suspend */
|
||||
|
||||
#define RTL8814A_TRANS_SUS_TO_CARDEMU \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0}, /*0x04[11] = 0 enable WL suspend*/ \
|
||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, 0},/*0x23[4] = 0 hpon LDO sleep mode leave */ \
|
||||
{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, 0},/* 0x14[14] =0 trun off ZCD */ \
|
||||
{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0},/*0x14[13] = 0 turn off ZCD */ \
|
||||
{0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio0~7 input mode */ \
|
||||
{0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio11 input mode, gpio10~8 input mode */
|
||||
|
||||
#define RTL8814A_TRANS_CARDEMU_TO_CARDDIS \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
/**{0x0194, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, //0x194[0]=0 , disable 32K clock*/ \
|
||||
/**{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x94}, //0x93 = 0x94 , 90[30] =0 enable 500k ANA clock .switch clock from 12M to 500K , 90 [26] =0 disable EEprom loader clock*/ \
|
||||
{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0}, /*0x03[2] = 0, reset 3081*/ \
|
||||
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x01}, /*0x80 = 05h if reload fw, fill the default value of host_CPU handshake field*/ \
|
||||
{0x0081, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x30}, /*0x80 = 05h if reload fw, fill the default value of host_CPU handshake field*/ \
|
||||
/*{0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xcc},*/ \
|
||||
/*{0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xEC},*/ \
|
||||
/*{0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x07},*/ /* gpio11 input mode, gpio10~8 output mode */ \
|
||||
{0x0045, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio 0~7 output same value as input ?? */ \
|
||||
{0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xff},/* gpio0~7 output mode */ \
|
||||
{0x0047, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/* 0x47[7:0] = 00 gpio mode */ \
|
||||
{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, BIT6},/* 0x15[6] =1 trun on ZCD output */ \
|
||||
{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*0x15[5] = 1 turn on ZCD */ \
|
||||
{0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, 0},/*0x12[6] = 0 force PFM mode */ \
|
||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4},/*0x23[4] = 1 hpon LDO sleep mode */ \
|
||||
{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*0x8[1] = 0 ANA clk = 500k */ \
|
||||
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07 = 0x20 , SOP option to disable BG/MB*/ \
|
||||
{0x001f, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /* 0x01f[1]=0 , disable RFC_0 control REG_RF_CTRL_8814A */ \
|
||||
{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /* 0x020[1]=0 , disable RFC_1 control REG_RF_CTRL_8814A */ \
|
||||
{0x0021, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /* 0x021[1]=0 , disable RFC_2 control REG_RF_CTRL_8814A */ \
|
||||
{0x0076, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /* 0x076[1]=0 , disable RFC_3 control REG_OPT_CTRL_8814A +2 */ \
|
||||
{0x0091, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xA0, 0xA0}, /* 0x91[7]=1 0x91[5]=1 , disable sps, ldo sleep mode */ \
|
||||
{0x0070, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3}, /* 0x70[3]=1 enable mainbias polling */ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3}, /*0x04[11] = 1 enable WL suspend*/
|
||||
|
||||
#define RTL8814A_TRANS_CARDDIS_TO_CARDEMU \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, BIT6},/*0x12[6] = 1 force PWM mode */ \
|
||||
{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0},/*0x15[5] = 0 turn off ZCD */ \
|
||||
{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, 0},/* 0x15[6] =0 trun off ZCD output */ \
|
||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0},/*0x23[4] = 0 hpon LDO leave sleep mode */ \
|
||||
{0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio0~7 input mode */ \
|
||||
{0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00}, /* gpio11 input mode, gpio10~8 input mode */ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0}, /*0x04[10] = 0, enable SW LPS PCIE only*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0}, /*0x04[11] = 0, enable WL suspend*/ \
|
||||
/*{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2},*/ /*0x03[2] = 1, enable 3081*/ \
|
||||
{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/ \
|
||||
{0x0071, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/*0x70[10] = 0, CPHY_MBIAS_EN disable*/
|
||||
|
||||
|
||||
#define RTL8814A_TRANS_CARDEMU_TO_PDN \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
|
||||
|
||||
#define RTL8814A_TRANS_PDN_TO_CARDEMU \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
|
||||
|
||||
#define RTL8814A_TRANS_ACT_TO_LPS \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/ \
|
||||
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/ \
|
||||
{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
|
||||
{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
|
||||
{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
|
||||
{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
|
||||
{0x0c00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xc00[7:0] = 4 turn off 3-wire */ \
|
||||
{0x0e00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xe00[7:0] = 4 turn off 3-wire */ \
|
||||
{0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated, and RF closed*/ \
|
||||
{0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \
|
||||
{0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /* Whole BB is reset*/ \
|
||||
{0x1002, (u8)(~PWR_CUT_TESTCHIP_MSK), PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated, and RF closed*/ \
|
||||
{0x0002, (u8)(~PWR_CUT_TESTCHIP_MSK), PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \
|
||||
{0x1002, (u8)(~PWR_CUT_TESTCHIP_MSK), PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /* Whole BB is reset*/ \
|
||||
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/ \
|
||||
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \
|
||||
{0x05F1, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*Respond TxOK to scheduler*/
|
||||
|
||||
|
||||
#define RTL8814A_TRANS_LPS_TO_ACT \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/ \
|
||||
{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/ \
|
||||
{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /* Delay*/ \
|
||||
{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*. 0x08[4] = 0 switch TSF to 40M*/ \
|
||||
{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, /* Polling 0x109[7]=0 TSF in 40M*/ \
|
||||
/*{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6 | BIT7, 0}, */ /*. ??0x29[7:6] = 2b'00 enable BB clock*/ \
|
||||
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1*/ \
|
||||
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/ \
|
||||
{0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1 | BIT0, BIT1 | BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/ \
|
||||
{0x1002, (u8)(~PWR_CUT_TESTCHIP_MSK), PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1 | BIT0, BIT1 | BIT0}, /*. 0x1002[1:0] = 2b'11 enable BB macro*/ \
|
||||
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/
|
||||
|
||||
#define RTL8814A_TRANS_END \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, PWR_CMD_END, 0, 0},
|
||||
|
||||
|
||||
extern WLAN_PWR_CFG rtl8814A_power_on_flow[RTL8814A_TRANS_CARDEMU_TO_ACT_STEPS + RTL8814A_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8814A_radio_off_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8814A_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8814A_card_disable_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8814A_TRANS_CARDEMU_TO_PDN_STEPS + RTL8814A_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8814A_card_enable_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8814A_TRANS_CARDEMU_TO_PDN_STEPS + RTL8814A_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8814A_suspend_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8814A_TRANS_CARDEMU_TO_SUS_STEPS + RTL8814A_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8814A_resume_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8814A_TRANS_CARDEMU_TO_SUS_STEPS + RTL8814A_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8814A_hwpdn_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8814A_TRANS_CARDEMU_TO_PDN_STEPS + RTL8814A_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8814A_enter_lps_flow[RTL8814A_TRANS_ACT_TO_LPS_STEPS + RTL8814A_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8814A_leave_lps_flow[RTL8814A_TRANS_LPS_TO_ACT_STEPS + RTL8814A_TRANS_END_STEPS];
|
||||
|
||||
#endif /* __HAL8814PWRSEQ_H__ */
|
||||
@@ -0,0 +1,86 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) Semiconductor - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
|
||||
|
||||
#include "Hal8821APwrSeq.h"
|
||||
#include <rtl8812a_hal.h>
|
||||
|
||||
|
||||
/*
|
||||
drivers should parse below arrays and do the corresponding actions
|
||||
*/
|
||||
/* 3 Power on Array */
|
||||
WLAN_PWR_CFG rtl8821A_power_on_flow[RTL8821A_TRANS_CARDEMU_TO_ACT_STEPS + RTL8821A_TRANS_END_STEPS] = {
|
||||
RTL8821A_TRANS_CARDEMU_TO_ACT
|
||||
RTL8821A_TRANS_END
|
||||
};
|
||||
|
||||
/* 3Radio off GPIO Array */
|
||||
WLAN_PWR_CFG rtl8821A_radio_off_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8821A_TRANS_END_STEPS] = {
|
||||
RTL8821A_TRANS_ACT_TO_CARDEMU
|
||||
RTL8821A_TRANS_END
|
||||
};
|
||||
|
||||
/* 3Card Disable Array */
|
||||
WLAN_PWR_CFG rtl8821A_card_disable_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS + RTL8821A_TRANS_END_STEPS] = {
|
||||
RTL8821A_TRANS_ACT_TO_CARDEMU
|
||||
RTL8821A_TRANS_CARDEMU_TO_CARDDIS
|
||||
RTL8821A_TRANS_END
|
||||
};
|
||||
|
||||
/* 3 Card Enable Array */
|
||||
WLAN_PWR_CFG rtl8821A_card_enable_flow[RTL8821A_TRANS_CARDDIS_TO_CARDEMU_STEPS + RTL8821A_TRANS_CARDEMU_TO_ACT_STEPS + RTL8821A_TRANS_END_STEPS] = {
|
||||
RTL8821A_TRANS_CARDDIS_TO_CARDEMU
|
||||
RTL8821A_TRANS_CARDEMU_TO_ACT
|
||||
RTL8821A_TRANS_END
|
||||
};
|
||||
|
||||
/* 3Suspend Array */
|
||||
WLAN_PWR_CFG rtl8821A_suspend_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8821A_TRANS_CARDEMU_TO_SUS_STEPS + RTL8821A_TRANS_END_STEPS] = {
|
||||
RTL8821A_TRANS_ACT_TO_CARDEMU
|
||||
RTL8821A_TRANS_CARDEMU_TO_SUS
|
||||
RTL8821A_TRANS_END
|
||||
};
|
||||
|
||||
/* 3 Resume Array */
|
||||
WLAN_PWR_CFG rtl8821A_resume_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8821A_TRANS_CARDEMU_TO_SUS_STEPS + RTL8821A_TRANS_END_STEPS] = {
|
||||
RTL8821A_TRANS_SUS_TO_CARDEMU
|
||||
RTL8821A_TRANS_CARDEMU_TO_ACT
|
||||
RTL8821A_TRANS_END
|
||||
};
|
||||
|
||||
|
||||
|
||||
/* 3HWPDN Array */
|
||||
WLAN_PWR_CFG rtl8821A_hwpdn_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS + RTL8821A_TRANS_END_STEPS] = {
|
||||
RTL8821A_TRANS_ACT_TO_CARDEMU
|
||||
RTL8821A_TRANS_CARDEMU_TO_PDN
|
||||
RTL8821A_TRANS_END
|
||||
};
|
||||
|
||||
/* 3 Enter LPS */
|
||||
WLAN_PWR_CFG rtl8821A_enter_lps_flow[RTL8821A_TRANS_ACT_TO_LPS_STEPS + RTL8821A_TRANS_END_STEPS] = {
|
||||
/* FW behavior */
|
||||
RTL8821A_TRANS_ACT_TO_LPS
|
||||
RTL8821A_TRANS_END
|
||||
};
|
||||
|
||||
/* 3 Leave LPS */
|
||||
WLAN_PWR_CFG rtl8821A_leave_lps_flow[RTL8821A_TRANS_LPS_TO_ACT_STEPS + RTL8821A_TRANS_END_STEPS] = {
|
||||
/* FW behavior */
|
||||
RTL8821A_TRANS_LPS_TO_ACT
|
||||
RTL8821A_TRANS_END
|
||||
};
|
||||
@@ -0,0 +1,200 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2016 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef REALTEK_POWER_SEQUENCE_8821
|
||||
#define REALTEK_POWER_SEQUENCE_8821
|
||||
|
||||
#include "HalPwrSeqCmd.h"
|
||||
|
||||
/*
|
||||
Check document WM-20130516-JackieLau-RTL8821A_Power_Architecture-R10.vsd
|
||||
There are 6 HW Power States:
|
||||
0: POFF--Power Off
|
||||
1: PDN--Power Down
|
||||
2: CARDEMU--Card Emulation
|
||||
3: ACT--Active Mode
|
||||
4: LPS--Low Power State
|
||||
5: SUS--Suspend
|
||||
|
||||
The transision from different states are defined below
|
||||
TRANS_CARDEMU_TO_ACT
|
||||
TRANS_ACT_TO_CARDEMU
|
||||
TRANS_CARDEMU_TO_SUS
|
||||
TRANS_SUS_TO_CARDEMU
|
||||
TRANS_CARDEMU_TO_PDN
|
||||
TRANS_ACT_TO_LPS
|
||||
TRANS_LPS_TO_ACT
|
||||
|
||||
TRANS_END
|
||||
*/
|
||||
#define RTL8821A_TRANS_CARDEMU_TO_ACT_STEPS 25
|
||||
#define RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS 15
|
||||
#define RTL8821A_TRANS_CARDEMU_TO_SUS_STEPS 15
|
||||
#define RTL8821A_TRANS_SUS_TO_CARDEMU_STEPS 15
|
||||
#define RTL8821A_TRANS_CARDDIS_TO_CARDEMU_STEPS 15
|
||||
#define RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS 15
|
||||
#define RTL8821A_TRANS_PDN_TO_CARDEMU_STEPS 15
|
||||
#define RTL8821A_TRANS_ACT_TO_LPS_STEPS 15
|
||||
#define RTL8821A_TRANS_LPS_TO_ACT_STEPS 15
|
||||
#define RTL8821A_TRANS_END_STEPS 1
|
||||
|
||||
|
||||
#define RTL8821A_TRANS_CARDEMU_TO_ACT \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/ \
|
||||
{0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x67[0] = 0 to disable BT_GPS_SEL pins*/ \
|
||||
{0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS},/*Delay 1ms*/ \
|
||||
{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0}, /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4 | BIT3 | BIT2), 0},/* disable SW LPS 0x04[10]=0 and WLSUS_EN 0x04[12:11]=0*/ \
|
||||
{0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 , BIT0},/* Disable USB suspend */ \
|
||||
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \
|
||||
{0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 , 0},/* Enable USB suspend */ \
|
||||
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset 0x04[16]=1*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* disable HWPDN 0x04[15]=0*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4 | BIT3), 0},/* disable WL suspend*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},/**/ \
|
||||
{0x004F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*0x4C[24] = 0x4F[0] = 1, switch DPDT_SEL_P output from WL BB */\
|
||||
{0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT5 | BIT4), (BIT5 | BIT4)},/*0x66[13] = 0x67[5] = 1, switch for PAPE_G/PAPE_A from WL BB ; 0x66[12] = 0x67[4] = 1, switch LNAON from WL BB */\
|
||||
{0x0025, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, 0},/*anapar_mac<118> , 0x25[6]=0 by wlan single function*/\
|
||||
{0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable falling edge triggering interrupt*/\
|
||||
{0x0063, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable GPIO9 interrupt mode*/\
|
||||
{0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Enable GPIO9 input mode*/\
|
||||
{0x0058, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*Enable HSISR GPIO[C:0] interrupt*/\
|
||||
{0x005A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable HSISR GPIO9 interrupt*/\
|
||||
{0x007A, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x3A},/*0x7A = 0x3A start BT*/\
|
||||
{0x002E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF , 0x82 },/* 0x2C[23:12]=0x820 ; XTAL trim */ \
|
||||
{0x0010, PWR_CUT_A_MSK , PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6 , BIT6 },/* 0x10[6]=1 ; MP新增對於0x2C的控制權，須把0x10[6]設為1才能讓WLAN控制 */ \
|
||||
|
||||
|
||||
#define RTL8821A_TRANS_ACT_TO_CARDEMU \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/ \
|
||||
{0x004F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*0x4C[24] = 0x4F[0] = 0, switch DPDT_SEL_P output from register 0x65[2] */\
|
||||
{0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Enable rising edge triggering interrupt*/ \
|
||||
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset 0x04[16]=1*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \
|
||||
{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5}, /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/ \
|
||||
{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*0x20[0] = 1b'0 disable LDOA12 MACRO block*/ \
|
||||
|
||||
|
||||
#define RTL8821A_TRANS_CARDEMU_TO_SUS \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4 | BIT3, (BIT4 | BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \
|
||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
|
||||
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3 | BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
|
||||
|
||||
#define RTL8821A_TRANS_SUS_TO_CARDEMU \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
|
||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
|
||||
|
||||
#define RTL8821A_TRANS_CARDEMU_TO_CARDDIS \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07 = 0x20 , SOP option to disable BG/MB*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2}, /*0x04[10] = 1, enable SW LPS*/ \
|
||||
{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 1}, /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/ \
|
||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
|
||||
|
||||
#define RTL8821A_TRANS_CARDDIS_TO_CARDEMU \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
|
||||
{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\
|
||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \
|
||||
{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/
|
||||
|
||||
|
||||
#define RTL8821A_TRANS_CARDEMU_TO_PDN \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
|
||||
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK | PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/ \
|
||||
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
|
||||
|
||||
#define RTL8821A_TRANS_PDN_TO_CARDEMU \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
|
||||
|
||||
#define RTL8821A_TRANS_ACT_TO_LPS \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/ \
|
||||
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/ \
|
||||
{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
|
||||
{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
|
||||
{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
|
||||
{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/ \
|
||||
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/ \
|
||||
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \
|
||||
{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/ \
|
||||
{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/ \
|
||||
|
||||
|
||||
#define RTL8821A_TRANS_LPS_TO_ACT \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\
|
||||
{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
|
||||
{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\
|
||||
{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*. 0x08[4] = 0 switch TSF to 40M*/\
|
||||
{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0 TSF in 40M*/\
|
||||
{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6 | BIT7, 0}, /*. 0x29[7:6] = 2b'00 enable BB clock*/\
|
||||
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1*/\
|
||||
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/\
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1 | BIT0, BIT1 | BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\
|
||||
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/
|
||||
|
||||
#define RTL8821A_TRANS_END \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, PWR_CMD_END, 0, 0},
|
||||
|
||||
|
||||
extern WLAN_PWR_CFG rtl8821A_power_on_flow[RTL8821A_TRANS_CARDEMU_TO_ACT_STEPS + RTL8821A_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8821A_radio_off_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8821A_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8821A_card_disable_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS + RTL8821A_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8821A_card_enable_flow[RTL8821A_TRANS_CARDDIS_TO_CARDEMU_STEPS + RTL8821A_TRANS_CARDEMU_TO_ACT_STEPS + RTL8821A_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8821A_suspend_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8821A_TRANS_CARDEMU_TO_SUS_STEPS + RTL8821A_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8821A_resume_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8821A_TRANS_CARDEMU_TO_SUS_STEPS + RTL8821A_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8821A_hwpdn_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS + RTL8821A_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8821A_enter_lps_flow[RTL8821A_TRANS_ACT_TO_LPS_STEPS + RTL8821A_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8821A_leave_lps_flow[RTL8821A_TRANS_LPS_TO_ACT_STEPS + RTL8821A_TRANS_END_STEPS];
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,130 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __HALPWRSEQCMD_H__
|
||||
#define __HALPWRSEQCMD_H__
|
||||
|
||||
#include <drv_types.h>
|
||||
|
||||
/*---------------------------------------------*/
|
||||
/* 3 The value of cmd: 4 bits
|
||||
*---------------------------------------------*/
|
||||
#define PWR_CMD_READ 0x00
|
||||
/* offset: the read register offset
|
||||
* msk: the mask of the read value
|
||||
* value: N/A, left by 0
|
||||
* note: dirver shall implement this function by read & msk */
|
||||
|
||||
#define PWR_CMD_WRITE 0x01
|
||||
/* offset: the read register offset
|
||||
* msk: the mask of the write bits
|
||||
* value: write value
|
||||
* note: driver shall implement this cmd by read & msk after write */
|
||||
|
||||
#define PWR_CMD_POLLING 0x02
|
||||
/* offset: the read register offset
|
||||
* msk: the mask of the polled value
|
||||
* value: the value to be polled, masked by the msd field.
|
||||
* note: driver shall implement this cmd by
|
||||
* do {
|
||||
* if( (Read(offset) & msk) == (value & msk) )
|
||||
* break;
|
||||
* } while(not timeout); */
|
||||
|
||||
#define PWR_CMD_DELAY 0x03
|
||||
/* offset: the value to delay
|
||||
* msk: N/A
|
||||
* value: the unit of delay, 0: us, 1: ms */
|
||||
|
||||
#define PWR_CMD_END 0x04
|
||||
/* offset: N/A
|
||||
* msk: N/A
|
||||
* value: N/A */
|
||||
|
||||
/*---------------------------------------------*/
|
||||
/* 3 The value of base: 4 bits
|
||||
*---------------------------------------------
|
||||
* define the base address of each block */
|
||||
#define PWR_BASEADDR_MAC 0x00
|
||||
#define PWR_BASEADDR_USB 0x01
|
||||
#define PWR_BASEADDR_PCIE 0x02
|
||||
#define PWR_BASEADDR_SDIO 0x03
|
||||
|
||||
/*---------------------------------------------*/
|
||||
/* 3 The value of interface_msk: 4 bits
|
||||
*---------------------------------------------*/
|
||||
#define PWR_INTF_SDIO_MSK BIT(0)
|
||||
#define PWR_INTF_USB_MSK BIT(1)
|
||||
#define PWR_INTF_PCI_MSK BIT(2)
|
||||
#define PWR_INTF_ALL_MSK (BIT(0) | BIT(1) | BIT(2) | BIT(3))
|
||||
|
||||
/*---------------------------------------------*/
|
||||
/* 3 The value of fab_msk: 4 bits
|
||||
*---------------------------------------------*/
|
||||
#define PWR_FAB_TSMC_MSK BIT(0)
|
||||
#define PWR_FAB_UMC_MSK BIT(1)
|
||||
#define PWR_FAB_ALL_MSK (BIT(0) | BIT(1) | BIT(2) | BIT(3))
|
||||
|
||||
/*---------------------------------------------*/
|
||||
/* 3 The value of cut_msk: 8 bits
|
||||
*---------------------------------------------*/
|
||||
#define PWR_CUT_TESTCHIP_MSK BIT(0)
|
||||
#define PWR_CUT_A_MSK BIT(1)
|
||||
#define PWR_CUT_B_MSK BIT(2)
|
||||
#define PWR_CUT_C_MSK BIT(3)
|
||||
#define PWR_CUT_D_MSK BIT(4)
|
||||
#define PWR_CUT_E_MSK BIT(5)
|
||||
#define PWR_CUT_F_MSK BIT(6)
|
||||
#define PWR_CUT_G_MSK BIT(7)
|
||||
#define PWR_CUT_ALL_MSK 0xFF
|
||||
|
||||
|
||||
typedef enum _PWRSEQ_CMD_DELAY_UNIT_ {
|
||||
PWRSEQ_DELAY_US,
|
||||
PWRSEQ_DELAY_MS,
|
||||
} PWRSEQ_DELAY_UNIT;
|
||||
|
||||
typedef struct _WL_PWR_CFG_ {
|
||||
u16 offset;
|
||||
u8 cut_msk;
|
||||
u8 fab_msk:4;
|
||||
u8 interface_msk:4;
|
||||
u8 base:4;
|
||||
u8 cmd:4;
|
||||
u8 msk;
|
||||
u8 value;
|
||||
} WLAN_PWR_CFG, *PWLAN_PWR_CFG;
|
||||
|
||||
|
||||
#define GET_PWR_CFG_OFFSET(__PWR_CMD) ((__PWR_CMD).offset)
|
||||
#define GET_PWR_CFG_CUT_MASK(__PWR_CMD) ((__PWR_CMD).cut_msk)
|
||||
#define GET_PWR_CFG_FAB_MASK(__PWR_CMD) ((__PWR_CMD).fab_msk)
|
||||
#define GET_PWR_CFG_INTF_MASK(__PWR_CMD) ((__PWR_CMD).interface_msk)
|
||||
#define GET_PWR_CFG_BASE(__PWR_CMD) ((__PWR_CMD).base)
|
||||
#define GET_PWR_CFG_CMD(__PWR_CMD) ((__PWR_CMD).cmd)
|
||||
#define GET_PWR_CFG_MASK(__PWR_CMD) ((__PWR_CMD).msk)
|
||||
#define GET_PWR_CFG_VALUE(__PWR_CMD) ((__PWR_CMD).value)
|
||||
|
||||
|
||||
/* ********************************************************************************
|
||||
* Prototype of protected function.
|
||||
* ******************************************************************************** */
|
||||
u8 HalPwrSeqCmdParsing(
|
||||
PADAPTER padapter,
|
||||
u8 CutVersion,
|
||||
u8 FabVersion,
|
||||
u8 InterfaceType,
|
||||
WLAN_PWR_CFG PwrCfgCmd[]);
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,211 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __HAL_VERSION_DEF_H__
|
||||
#define __HAL_VERSION_DEF_H__
|
||||
|
||||
#undef TRUE
|
||||
#undef FALSE
|
||||
|
||||
#include "basic_types.h"
|
||||
#include "drv_types.h"
|
||||
|
||||
#define TRUE _TRUE
|
||||
#define FALSE _FALSE
|
||||
|
||||
/* HAL_IC_TYPE_E */
|
||||
typedef enum tag_HAL_IC_Type_Definition {
|
||||
CHIP_8192S = 0,
|
||||
CHIP_8188C = 1,
|
||||
CHIP_8192C = 2,
|
||||
CHIP_8192D = 3,
|
||||
CHIP_8723A = 4,
|
||||
CHIP_8188E = 5,
|
||||
CHIP_8812 = 6,
|
||||
CHIP_8821 = 7,
|
||||
CHIP_8723B = 8,
|
||||
CHIP_8192E = 9,
|
||||
CHIP_8814A = 10,
|
||||
CHIP_8703B = 11,
|
||||
CHIP_8188F = 12,
|
||||
CHIP_8822B = 13,
|
||||
CHIP_8723D = 14,
|
||||
CHIP_8821C = 15,
|
||||
/* Jaguar3 family added by devourer (not in upstream HalVerDef). 8822C and
|
||||
* 8822E share the rtl8822c phydm generation; 8812EU enumerates under the
|
||||
* 8822E HAL. */
|
||||
CHIP_8822C = 16,
|
||||
CHIP_8822E = 17
|
||||
} HAL_IC_TYPE_E;
|
||||
|
||||
/* HAL_CHIP_TYPE_E */
|
||||
typedef enum tag_HAL_CHIP_Type_Definition {
|
||||
TEST_CHIP = 0,
|
||||
NORMAL_CHIP = 1,
|
||||
FPGA = 2,
|
||||
} HAL_CHIP_TYPE_E;
|
||||
|
||||
/* HAL_CUT_VERSION_E */
|
||||
typedef enum tag_HAL_Cut_Version_Definition {
|
||||
A_CUT_VERSION = 0,
|
||||
B_CUT_VERSION = 1,
|
||||
C_CUT_VERSION = 2,
|
||||
D_CUT_VERSION = 3,
|
||||
E_CUT_VERSION = 4,
|
||||
F_CUT_VERSION = 5,
|
||||
G_CUT_VERSION = 6,
|
||||
H_CUT_VERSION = 7,
|
||||
I_CUT_VERSION = 8,
|
||||
J_CUT_VERSION = 9,
|
||||
K_CUT_VERSION = 10,
|
||||
} HAL_CUT_VERSION_E;
|
||||
|
||||
/* HAL_Manufacturer */
|
||||
typedef enum tag_HAL_Manufacturer_Version_Definition {
|
||||
CHIP_VENDOR_TSMC = 0,
|
||||
CHIP_VENDOR_UMC = 1,
|
||||
CHIP_VENDOR_SMIC = 2,
|
||||
} HAL_VENDOR_E;
|
||||
|
||||
typedef enum tag_HAL_RF_Type_Definition {
|
||||
RF_TYPE_1T1R = 0,
|
||||
RF_TYPE_1T2R = 1,
|
||||
RF_TYPE_2T2R = 2,
|
||||
RF_TYPE_2T3R = 3,
|
||||
RF_TYPE_2T4R = 4,
|
||||
RF_TYPE_3T3R = 5,
|
||||
RF_TYPE_3T4R = 6,
|
||||
RF_TYPE_4T4R = 7,
|
||||
RF_TYPE_MAX = 0x0F,
|
||||
} HAL_RF_TYPE_E;
|
||||
|
||||
typedef struct tag_HAL_VERSION {
|
||||
HAL_IC_TYPE_E ICType;
|
||||
HAL_CHIP_TYPE_E ChipType;
|
||||
HAL_CUT_VERSION_E CUTVersion;
|
||||
HAL_VENDOR_E VendorType;
|
||||
HAL_RF_TYPE_E RFType;
|
||||
u8 ROMVer;
|
||||
} HAL_VERSION, *PHAL_VERSION;
|
||||
|
||||
/* VERSION_8192C VersionID;
|
||||
* HAL_VERSION VersionID; */
|
||||
|
||||
/* Get element */
|
||||
#define GET_CVID_IC_TYPE(version) ((HAL_IC_TYPE_E)(((HAL_VERSION)version).ICType))
|
||||
#define GET_CVID_CHIP_TYPE(version) ((HAL_CHIP_TYPE_E)(((HAL_VERSION)version).ChipType))
|
||||
#define GET_CVID_RF_TYPE(version) ((HAL_RF_TYPE_E)(((HAL_VERSION)version).RFType))
|
||||
#define GET_CVID_MANUFACTUER(version) ((HAL_VENDOR_E)(((HAL_VERSION)version).VendorType))
|
||||
#define GET_CVID_CUT_VERSION(version) ((HAL_CUT_VERSION_E)(((HAL_VERSION)version).CUTVersion))
|
||||
#define GET_CVID_ROM_VERSION(version) ((((HAL_VERSION)version).ROMVer) & ROM_VERSION_MASK)
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
* Common Macro. --
|
||||
* ----------------------------------------------------------------------------
|
||||
* HAL_VERSION VersionID */
|
||||
|
||||
/* HAL_IC_TYPE_E */
|
||||
#if 0
|
||||
#define IS_81XXC(version) (((GET_CVID_IC_TYPE(version) == CHIP_8192C) || (GET_CVID_IC_TYPE(version) == CHIP_8188C)) ? TRUE : FALSE)
|
||||
#define IS_8723_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8723A) ? TRUE : FALSE)
|
||||
#define IS_92D(version) ((GET_CVID_IC_TYPE(version) == CHIP_8192D) ? TRUE : FALSE)
|
||||
#endif
|
||||
|
||||
#define IS_8188E(version) ((GET_CVID_IC_TYPE(version) == CHIP_8188E) ? TRUE : FALSE)
|
||||
#define IS_8188F(version) ((GET_CVID_IC_TYPE(version) == CHIP_8188F) ? TRUE : FALSE)
|
||||
#define IS_8192E(version) ((GET_CVID_IC_TYPE(version) == CHIP_8192E) ? TRUE : FALSE)
|
||||
#define IS_8812_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8812) ? TRUE : FALSE)
|
||||
#define IS_8821_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8821) ? TRUE : FALSE)
|
||||
#define IS_8814A_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8814A) ? TRUE : FALSE)
|
||||
#define IS_8723B_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8723B) ? TRUE : FALSE)
|
||||
#define IS_8703B_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8703B) ? TRUE : FALSE)
|
||||
#define IS_8822B_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8822B) ? TRUE : FALSE)
|
||||
#define IS_8821C_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8821C) ? TRUE : FALSE)
|
||||
#define IS_8822C_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8822C) ? TRUE : FALSE)
|
||||
#define IS_8822E_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8822E) ? TRUE : FALSE)
|
||||
/* Jaguar3 = the 8822C/8822E baseband+MAC generation (shared rtl8822c phydm).
|
||||
* Used by the WiFiDriver factory to dispatch to RtlJaguar3Device. */
|
||||
#define IS_JAGUAR3(version) ((IS_8822C_SERIES(version) || IS_8822E_SERIES(version)) ? TRUE : FALSE)
|
||||
#define IS_8723D_SERIES(version)\
|
||||
((GET_CVID_IC_TYPE(version) == CHIP_8723D) ? TRUE : FALSE)
|
||||
/* HAL_CHIP_TYPE_E */
|
||||
#define IS_TEST_CHIP(version) ((GET_CVID_CHIP_TYPE(version) == TEST_CHIP) ? TRUE : FALSE)
|
||||
#define IS_NORMAL_CHIP(version) ((GET_CVID_CHIP_TYPE(version) == NORMAL_CHIP) ? TRUE : FALSE)
|
||||
|
||||
/* HAL_CUT_VERSION_E */
|
||||
#define IS_A_CUT(version) ((GET_CVID_CUT_VERSION(version) == A_CUT_VERSION) ? TRUE : FALSE)
|
||||
#define IS_B_CUT(version) ((GET_CVID_CUT_VERSION(version) == B_CUT_VERSION) ? TRUE : FALSE)
|
||||
#define IS_C_CUT(version) ((GET_CVID_CUT_VERSION(version) == C_CUT_VERSION) ? TRUE : FALSE)
|
||||
#define IS_D_CUT(version) ((GET_CVID_CUT_VERSION(version) == D_CUT_VERSION) ? TRUE : FALSE)
|
||||
#define IS_E_CUT(version) ((GET_CVID_CUT_VERSION(version) == E_CUT_VERSION) ? TRUE : FALSE)
|
||||
#define IS_F_CUT(version) ((GET_CVID_CUT_VERSION(version) == F_CUT_VERSION) ? TRUE : FALSE)
|
||||
#define IS_I_CUT(version) ((GET_CVID_CUT_VERSION(version) == I_CUT_VERSION) ? TRUE : FALSE)
|
||||
#define IS_J_CUT(version) ((GET_CVID_CUT_VERSION(version) == J_CUT_VERSION) ? TRUE : FALSE)
|
||||
#define IS_K_CUT(version) ((GET_CVID_CUT_VERSION(version) == K_CUT_VERSION) ? TRUE : FALSE)
|
||||
|
||||
/* HAL_VENDOR_E */
|
||||
#define IS_CHIP_VENDOR_TSMC(version) ((GET_CVID_MANUFACTUER(version) == CHIP_VENDOR_TSMC) ? TRUE : FALSE)
|
||||
#define IS_CHIP_VENDOR_UMC(version) ((GET_CVID_MANUFACTUER(version) == CHIP_VENDOR_UMC) ? TRUE : FALSE)
|
||||
#define IS_CHIP_VENDOR_SMIC(version) ((GET_CVID_MANUFACTUER(version) == CHIP_VENDOR_SMIC) ? TRUE : FALSE)
|
||||
|
||||
/* HAL_RF_TYPE_E */
|
||||
#define IS_1T1R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_1T1R) ? TRUE : FALSE)
|
||||
#define IS_1T2R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_1T2R) ? TRUE : FALSE)
|
||||
#define IS_2T2R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_2T2R) ? TRUE : FALSE)
|
||||
#define IS_3T3R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_3T3R) ? TRUE : FALSE)
|
||||
#define IS_3T4R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_3T4R) ? TRUE : FALSE)
|
||||
#define IS_4T4R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_4T4R) ? TRUE : FALSE)
|
||||
|
||||
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
* Chip version Macro. --
|
||||
* ---------------------------------------------------------------------------- */
|
||||
#if 0
|
||||
#define IS_81XXC_TEST_CHIP(version) ((IS_81XXC(version) && (!IS_NORMAL_CHIP(version))) ? TRUE : FALSE)
|
||||
|
||||
#define IS_92C_SERIAL(version) ((IS_81XXC(version) && IS_2T2R(version)) ? TRUE : FALSE)
|
||||
#define IS_81xxC_VENDOR_UMC_A_CUT(version) (IS_81XXC(version) ? (IS_CHIP_VENDOR_UMC(version) ? (IS_A_CUT(version) ? TRUE : FALSE) : FALSE) : FALSE)
|
||||
#define IS_81xxC_VENDOR_UMC_B_CUT(version) (IS_81XXC(version) ? (IS_CHIP_VENDOR_UMC(version) ? (IS_B_CUT(version) ? TRUE : FALSE) : FALSE) : FALSE)
|
||||
#define IS_81xxC_VENDOR_UMC_C_CUT(version) (IS_81XXC(version) ? (IS_CHIP_VENDOR_UMC(version) ? (IS_C_CUT(version) ? TRUE : FALSE) : FALSE) : FALSE)
|
||||
|
||||
#define IS_NORMAL_CHIP92D(version) ((IS_92D(version)) ? ((GET_CVID_CHIP_TYPE(version) == NORMAL_CHIP) ? TRUE : FALSE) : FALSE)
|
||||
|
||||
#define IS_92D_SINGLEPHY(version) ((IS_92D(version)) ? (IS_2T2R(version) ? TRUE : FALSE) : FALSE)
|
||||
#define IS_92D_C_CUT(version) ((IS_92D(version)) ? (IS_C_CUT(version) ? TRUE : FALSE) : FALSE)
|
||||
#define IS_92D_D_CUT(version) ((IS_92D(version)) ? (IS_D_CUT(version) ? TRUE : FALSE) : FALSE)
|
||||
#define IS_92D_E_CUT(version) ((IS_92D(version)) ? (IS_E_CUT(version) ? TRUE : FALSE) : FALSE)
|
||||
|
||||
#define IS_8723A_A_CUT(version) ((IS_8723_SERIES(version)) ? (IS_A_CUT(version) ? TRUE : FALSE) : FALSE)
|
||||
#define IS_8723A_B_CUT(version) ((IS_8723_SERIES(version)) ? (IS_B_CUT(version) ? TRUE : FALSE) : FALSE)
|
||||
#endif
|
||||
#define IS_VENDOR_8188E_I_CUT_SERIES(_Adapter) ((IS_8188E(GET_HAL_DATA(_Adapter)->version_id)) ? ((GET_CVID_CUT_VERSION(GET_HAL_DATA(_Adapter)->version_id) >= I_CUT_VERSION) ? TRUE : FALSE) : FALSE)
|
||||
#define IS_VENDOR_8812A_TEST_CHIP(_Adapter) ((IS_8812_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? FALSE : TRUE) : FALSE)
|
||||
#define IS_VENDOR_8812A_MP_CHIP(_Adapter) ((IS_8812_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? TRUE : FALSE) : FALSE)
|
||||
#define IS_VENDOR_8812A_C_CUT(_Adapter) ((IS_8812_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((GET_CVID_CUT_VERSION(GET_HAL_DATA(_Adapter)->version_id) == C_CUT_VERSION) ? TRUE : FALSE) : FALSE)
|
||||
|
||||
#define IS_VENDOR_8821A_TEST_CHIP(_Adapter) ((IS_8821_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? FALSE : TRUE) : FALSE)
|
||||
#define IS_VENDOR_8821A_MP_CHIP(_Adapter) ((IS_8821_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? TRUE : FALSE) : FALSE)
|
||||
|
||||
#define IS_VENDOR_8192E_B_CUT(_Adapter) ((GET_CVID_CUT_VERSION(GET_HAL_DATA(_Adapter)->version_id) == B_CUT_VERSION) ? TRUE : FALSE)
|
||||
|
||||
#define IS_VENDOR_8723B_TEST_CHIP(_Adapter) ((IS_8723B_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? FALSE : TRUE) : FALSE)
|
||||
#define IS_VENDOR_8723B_MP_CHIP(_Adapter) ((IS_8723B_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? TRUE : FALSE) : FALSE)
|
||||
|
||||
#define IS_VENDOR_8703B_TEST_CHIP(_Adapter) ((IS_8703B_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? FALSE : TRUE) : FALSE)
|
||||
#define IS_VENDOR_8703B_MP_CHIP(_Adapter) ((IS_8703B_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? TRUE : FALSE) : FALSE)
|
||||
#define IS_VENDOR_8814A_TEST_CHIP(_Adapter) ((IS_8814A_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? FALSE : TRUE) : FALSE)
|
||||
#define IS_VENDOR_8814A_MP_CHIP(_Adapter) ((IS_8814A_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? TRUE : FALSE) : FALSE)
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,35 @@
|
||||
#ifndef BASIC_TYPES_H
|
||||
#define BASIC_TYPES_H
|
||||
|
||||
#include "drv_types.h"
|
||||
|
||||
#define SUCCESS 0
|
||||
#define FAIL (-1)
|
||||
|
||||
#ifndef TRUE
|
||||
#define _TRUE 1
|
||||
#else
|
||||
#define _TRUE TRUE
|
||||
#endif
|
||||
|
||||
#ifndef FALSE
|
||||
#define _FALSE 0
|
||||
#else
|
||||
#define _FALSE FALSE
|
||||
#endif
|
||||
|
||||
#define cpu_to_le32(x) ((__u32)(x))
|
||||
#define le32_to_cpu(x) ((__u32)(x))
|
||||
#define cpu_to_le16(x) ((__u16)(x))
|
||||
#define le16_to_cpu(x) ((__u16)(x))
|
||||
|
||||
|
||||
#define LE_BITS_TO_4BYTE(__pStart, __BitOffset, __BitLen) \
|
||||
((LE_P4BYTE_TO_HOST_4BYTE(__pStart) >> (__BitOffset)) & \
|
||||
BIT_LEN_MASK_32(__BitLen))
|
||||
#define LE_P4BYTE_TO_HOST_4BYTE(__pStart) (le32_to_cpu(*((u32 *)(__pStart))))
|
||||
#define BIT_LEN_MASK_32(__BitLen) ((u32)(0xFFFFFFFF >> (32 - (__BitLen))))
|
||||
|
||||
#define ReadLE2Byte(_ptr) le16_to_cpu(*((u16 *)(_ptr)))
|
||||
|
||||
#endif /* BASIC_TYPES_H */
|
||||
@@ -0,0 +1,67 @@
|
||||
#ifndef DRV_TYPES_H
|
||||
#define DRV_TYPES_H
|
||||
|
||||
#define BIT(nr) (1UL << (nr))
|
||||
#define BIT0 BIT(0)
|
||||
#define BIT1 BIT(1)
|
||||
#define BIT2 BIT(2)
|
||||
#define BIT3 BIT(3)
|
||||
#define BIT4 BIT(4)
|
||||
#define BIT5 BIT(5)
|
||||
#define BIT6 BIT(6)
|
||||
#define BIT7 BIT(7)
|
||||
#define BIT8 BIT(8)
|
||||
#define BIT9 BIT(9)
|
||||
#define BIT10 BIT(10)
|
||||
#define BIT11 BIT(11)
|
||||
#define BIT12 BIT(12)
|
||||
#define BIT13 BIT(13)
|
||||
#define BIT14 BIT(14)
|
||||
#define BIT15 BIT(15)
|
||||
#define BIT16 BIT(16)
|
||||
#define BIT17 BIT(17)
|
||||
#define BIT18 BIT(18)
|
||||
#define BIT19 BIT(19)
|
||||
#define BIT20 BIT(20)
|
||||
#define BIT21 BIT(21)
|
||||
#define BIT22 BIT(22)
|
||||
#define BIT23 BIT(23)
|
||||
#define BIT24 BIT(24)
|
||||
#define BIT25 BIT(25)
|
||||
#define BIT26 BIT(26)
|
||||
#define BIT27 BIT(27)
|
||||
#define BIT28 BIT(28)
|
||||
#define BIT29 BIT(29)
|
||||
#define BIT30 BIT(30)
|
||||
#define BIT31 BIT(31)
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
|
||||
typedef uint8_t u8;
|
||||
typedef uint16_t u16;
|
||||
typedef uint32_t u32;
|
||||
/* basic_types.h's cpu_to_le / le_to_cpu macros expand to these; define them
|
||||
* here (the typedef home) so any TU that includes basic_types.h has them,
|
||||
* independent of the TX-descriptor headers. */
|
||||
typedef uint16_t __u16;
|
||||
typedef uint32_t __u32;
|
||||
typedef void *PADAPTER;
|
||||
#ifndef WIN32
|
||||
typedef bool BOOLEAN;
|
||||
typedef void VOID;
|
||||
#endif
|
||||
|
||||
|
||||
static uint32_t PHY_CalculateBitShift(uint32_t BitMask) {
|
||||
int i;
|
||||
|
||||
for (i = 0; i <= 31; i++) {
|
||||
if (((BitMask >> i) & 0x1) == 1)
|
||||
break;
|
||||
}
|
||||
|
||||
return i;
|
||||
}
|
||||
|
||||
#endif /* DRV_TYPES_H */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,15 @@
|
||||
/* Auto-extracted RTL8733B NIC firmware. See hal8733b_fw.c. */
|
||||
#ifndef HAL8733B_FW_H
|
||||
#define HAL8733B_FW_H
|
||||
#include "drv_types.h"
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
extern const u8 array_mp_8733b_fw_nic[];
|
||||
extern const u32 array_mp_8733b_fw_nic_len;
|
||||
extern const u8 ccv_array_mp_8733b_fw_nic[];
|
||||
extern const u32 ccv_array_mp_8733b_fw_nic_len;
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* HAL8733B_FW_H */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,26 @@
|
||||
/* Auto-extracted RTL8733B parameter tables. See hal8733b_tables.c. */
|
||||
#ifndef HAL8733B_TABLES_H
|
||||
#define HAL8733B_TABLES_H
|
||||
#include <stddef.h>
|
||||
#include <stdint.h>
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
extern const uint32_t array_mp_8733b_mac_reg[];
|
||||
extern const size_t array_mp_8733b_mac_reg_len;
|
||||
extern const uint32_t array_mp_8733b_agc_tab[];
|
||||
extern const size_t array_mp_8733b_agc_tab_len;
|
||||
extern const uint32_t array_mp_8733b_phy_reg[];
|
||||
extern const size_t array_mp_8733b_phy_reg_len;
|
||||
extern const uint32_t array_mp_8733b_phy_reg_pg[];
|
||||
extern const size_t array_mp_8733b_phy_reg_pg_len;
|
||||
extern const uint32_t array_mp_8733b_radioa[];
|
||||
extern const size_t array_mp_8733b_radioa_len;
|
||||
extern const uint32_t array_mp_8733b_radiob[];
|
||||
extern const size_t array_mp_8733b_radiob_len;
|
||||
extern const uint32_t array_mp_8733b_cal_init[];
|
||||
extern const size_t array_mp_8733b_cal_init_len;
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* HAL8733B_TABLES_H */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,47 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2016 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifdef CONFIG_RTL8812A
|
||||
|
||||
#ifndef _FW_HEADER_8812A_H
|
||||
#define _FW_HEADER_8812A_H
|
||||
|
||||
#ifdef LOAD_FW_HEADER_FROM_DRIVER
|
||||
#if (defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP)))
|
||||
extern u8 array_mp_8812a_fw_ap[24130];
|
||||
extern u32 array_length_mp_8812a_fw_ap;
|
||||
#endif
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) || (DM_ODM_SUPPORT_TYPE & (ODM_CE))
|
||||
extern u8 array_mp_8812a_fw_nic[27054];
|
||||
extern u32 array_length_mp_8812a_fw_nic;
|
||||
extern u8 array_mp_8812a_fw_nic_bt[29918];
|
||||
extern u32 array_length_mp_8812a_fw_nic_bt;
|
||||
extern u8 array_mp_8812a_fw_nic_mcc[29452];
|
||||
extern u32 array_length_mp_8812a_fw_nic_mcc;
|
||||
extern u8 array_mp_8812a_fw_wowlan[32450];
|
||||
extern u32 array_length_mp_8812a_fw_wowlan;
|
||||
#endif
|
||||
#endif /* end of LOAD_FW_HEADER_FROM_DRIVER */
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,43 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2016 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifdef CONFIG_RTL8814A
|
||||
|
||||
#ifndef _FW_HEADER_8814A_H
|
||||
#define _FW_HEADER_8814A_H
|
||||
|
||||
#ifdef LOAD_FW_HEADER_FROM_DRIVER
|
||||
#if (defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP)))
|
||||
extern u8 array_mp_8814a_fw_ap[42248];
|
||||
extern u32 array_length_mp_8814a_fw_ap;
|
||||
#endif
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) || (DM_ODM_SUPPORT_TYPE & (ODM_CE))
|
||||
extern u8 array_mp_8814a_fw_nic[68320];
|
||||
extern u32 array_length_mp_8814a_fw_nic;
|
||||
extern u8 array_mp_8814a_fw_wowlan[45944];
|
||||
extern u32 array_length_mp_8814a_fw_wowlan;
|
||||
#endif
|
||||
#endif /* end of LOAD_FW_HEADER_FROM_DRIVER */
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,40 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_RTL8821A
|
||||
|
||||
#ifndef _FW_HEADER_8821A_H
|
||||
#define _FW_HEADER_8821A_H
|
||||
|
||||
#ifdef LOAD_FW_HEADER_FROM_DRIVER
|
||||
#if (defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP)))
|
||||
extern u8 array_mp_8821a_fw_ap[17152];
|
||||
extern u32 array_length_mp_8821a_fw_ap;
|
||||
#endif
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) || (DM_ODM_SUPPORT_TYPE & (ODM_CE))
|
||||
extern u8 array_mp_8821a_fw_nic[31834];
|
||||
extern u32 array_length_mp_8821a_fw_nic;
|
||||
extern u8 array_mp_8821a_fw_nic_bt[32392];
|
||||
extern u32 array_length_mp_8821a_fw_nic_bt;
|
||||
extern u8 array_mp_8821a_fw_wowlan[28298];
|
||||
extern u32 array_length_mp_8821a_fw_wowlan;
|
||||
#endif
|
||||
#endif /* end of LOAD_FW_HEADER_FROM_DRIVER */
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,13 @@
|
||||
/* Auto-extracted RTL8821C NIC firmware blob. See hal8821c_fw.c. */
|
||||
#ifndef HAL8821C_FW_H
|
||||
#define HAL8821C_FW_H
|
||||
#include "drv_types.h"
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
extern const u8 array_mp_8821c_fw_nic[];
|
||||
extern const u32 array_mp_8821c_fw_nic_len;
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* HAL8821C_FW_H */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,13 @@
|
||||
/* Auto-extracted RTL8822B NIC firmware blob. See hal8822b_fw.c. */
|
||||
#ifndef HAL8822B_FW_H
|
||||
#define HAL8822B_FW_H
|
||||
#include "drv_types.h"
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
extern const u8 array_mp_8822b_fw_nic[];
|
||||
extern const u32 array_mp_8822b_fw_nic_len;
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* HAL8822B_FW_H */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,13 @@
|
||||
/* Auto-extracted RTL8822C NIC firmware blob. See hal8822c_fw.c. */
|
||||
#ifndef HAL8822C_FW_H
|
||||
#define HAL8822C_FW_H
|
||||
#include "drv_types.h"
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
extern const u8 array_mp_8822c_fw_nic[];
|
||||
extern const u32 array_mp_8822c_fw_nic_len;
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* HAL8822C_FW_H */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,13 @@
|
||||
/* Auto-extracted RTL8822E NIC firmware blob. See hal8822e_fw.c. */
|
||||
#ifndef HAL8822E_FW_H
|
||||
#define HAL8822E_FW_H
|
||||
#include "drv_types.h"
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
extern const u8 array_mp_8822e_fw_nic[];
|
||||
extern const u32 array_mp_8822e_fw_nic_len;
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* HAL8822E_FW_H */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,16 @@
|
||||
/* Auto-extracted RTL8852B NICCE firmware blobs (u2 = cut CBV, u3 = cut CCV+).
|
||||
* See hal8852b_fw.c. */
|
||||
#ifndef HAL8852B_FW_H
|
||||
#define HAL8852B_FW_H
|
||||
#include "drv_types.h"
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
extern const u8 array_8852b_u2_nicce[];
|
||||
extern const u32 array_8852b_u2_nicce_len;
|
||||
extern const u8 array_8852b_u3_nicce[];
|
||||
extern const u32 array_8852b_u3_nicce_len;
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* HAL8852B_FW_H */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,16 @@
|
||||
/* Auto-extracted RTL8852C NIC firmware blobs (u1 = cut CAV, u2 = cut CBV+).
|
||||
* See hal8852c_fw.c. */
|
||||
#ifndef HAL8852C_FW_H
|
||||
#define HAL8852C_FW_H
|
||||
#include "drv_types.h"
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
extern const u8 array_8852c_u1_nic[];
|
||||
extern const u32 array_8852c_u1_nic_len;
|
||||
extern const u8 array_8852c_u2_nic[];
|
||||
extern const u32 array_8852c_u2_nic_len;
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* HAL8852C_FW_H */
|
||||
@@ -0,0 +1,659 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __HAL_COMMON_H__
|
||||
#define __HAL_COMMON_H__
|
||||
|
||||
#include "HalVerDef.h"
|
||||
#include "hal_pg.h"
|
||||
#include "hal_phy.h"
|
||||
#include "hal_phy_reg.h"
|
||||
#include "hal_com_reg.h"
|
||||
#include "hal_com_phycfg.h"
|
||||
#include "../hal/hal_com_c2h.h"
|
||||
|
||||
/*------------------------------ Tx Desc definition Macro ------------------------*/
|
||||
/* #pragma mark -- Tx Desc related definition. -- */
|
||||
/* ----------------------------------------------------------------------------
|
||||
* -----------------------------------------------------------
|
||||
* Rate
|
||||
* -----------------------------------------------------------
|
||||
* CCK Rates, TxHT = 0 */
|
||||
#define DESC_RATE1M 0x00
|
||||
#define DESC_RATE2M 0x01
|
||||
#define DESC_RATE5_5M 0x02
|
||||
#define DESC_RATE11M 0x03
|
||||
|
||||
/* OFDM Rates, TxHT = 0 */
|
||||
#define DESC_RATE6M 0x04
|
||||
#define DESC_RATE9M 0x05
|
||||
#define DESC_RATE12M 0x06
|
||||
#define DESC_RATE18M 0x07
|
||||
#define DESC_RATE24M 0x08
|
||||
#define DESC_RATE36M 0x09
|
||||
#define DESC_RATE48M 0x0a
|
||||
#define DESC_RATE54M 0x0b
|
||||
|
||||
/* MCS Rates, TxHT = 1 */
|
||||
#define DESC_RATEMCS0 0x0c
|
||||
#define DESC_RATEMCS1 0x0d
|
||||
#define DESC_RATEMCS2 0x0e
|
||||
#define DESC_RATEMCS3 0x0f
|
||||
#define DESC_RATEMCS4 0x10
|
||||
#define DESC_RATEMCS5 0x11
|
||||
#define DESC_RATEMCS6 0x12
|
||||
#define DESC_RATEMCS7 0x13
|
||||
#define DESC_RATEMCS8 0x14
|
||||
#define DESC_RATEMCS9 0x15
|
||||
#define DESC_RATEMCS10 0x16
|
||||
#define DESC_RATEMCS11 0x17
|
||||
#define DESC_RATEMCS12 0x18
|
||||
#define DESC_RATEMCS13 0x19
|
||||
#define DESC_RATEMCS14 0x1a
|
||||
#define DESC_RATEMCS15 0x1b
|
||||
#define DESC_RATEMCS16 0x1C
|
||||
#define DESC_RATEMCS17 0x1D
|
||||
#define DESC_RATEMCS18 0x1E
|
||||
#define DESC_RATEMCS19 0x1F
|
||||
#define DESC_RATEMCS20 0x20
|
||||
#define DESC_RATEMCS21 0x21
|
||||
#define DESC_RATEMCS22 0x22
|
||||
#define DESC_RATEMCS23 0x23
|
||||
#define DESC_RATEMCS24 0x24
|
||||
#define DESC_RATEMCS25 0x25
|
||||
#define DESC_RATEMCS26 0x26
|
||||
#define DESC_RATEMCS27 0x27
|
||||
#define DESC_RATEMCS28 0x28
|
||||
#define DESC_RATEMCS29 0x29
|
||||
#define DESC_RATEMCS30 0x2A
|
||||
#define DESC_RATEMCS31 0x2B
|
||||
#define DESC_RATEVHTSS1MCS0 0x2C
|
||||
#define DESC_RATEVHTSS1MCS1 0x2D
|
||||
#define DESC_RATEVHTSS1MCS2 0x2E
|
||||
#define DESC_RATEVHTSS1MCS3 0x2F
|
||||
#define DESC_RATEVHTSS1MCS4 0x30
|
||||
#define DESC_RATEVHTSS1MCS5 0x31
|
||||
#define DESC_RATEVHTSS1MCS6 0x32
|
||||
#define DESC_RATEVHTSS1MCS7 0x33
|
||||
#define DESC_RATEVHTSS1MCS8 0x34
|
||||
#define DESC_RATEVHTSS1MCS9 0x35
|
||||
#define DESC_RATEVHTSS2MCS0 0x36
|
||||
#define DESC_RATEVHTSS2MCS1 0x37
|
||||
#define DESC_RATEVHTSS2MCS2 0x38
|
||||
#define DESC_RATEVHTSS2MCS3 0x39
|
||||
#define DESC_RATEVHTSS2MCS4 0x3A
|
||||
#define DESC_RATEVHTSS2MCS5 0x3B
|
||||
#define DESC_RATEVHTSS2MCS6 0x3C
|
||||
#define DESC_RATEVHTSS2MCS7 0x3D
|
||||
#define DESC_RATEVHTSS2MCS8 0x3E
|
||||
#define DESC_RATEVHTSS2MCS9 0x3F
|
||||
#define DESC_RATEVHTSS3MCS0 0x40
|
||||
#define DESC_RATEVHTSS3MCS1 0x41
|
||||
#define DESC_RATEVHTSS3MCS2 0x42
|
||||
#define DESC_RATEVHTSS3MCS3 0x43
|
||||
#define DESC_RATEVHTSS3MCS4 0x44
|
||||
#define DESC_RATEVHTSS3MCS5 0x45
|
||||
#define DESC_RATEVHTSS3MCS6 0x46
|
||||
#define DESC_RATEVHTSS3MCS7 0x47
|
||||
#define DESC_RATEVHTSS3MCS8 0x48
|
||||
#define DESC_RATEVHTSS3MCS9 0x49
|
||||
#define DESC_RATEVHTSS4MCS0 0x4A
|
||||
#define DESC_RATEVHTSS4MCS1 0x4B
|
||||
#define DESC_RATEVHTSS4MCS2 0x4C
|
||||
#define DESC_RATEVHTSS4MCS3 0x4D
|
||||
#define DESC_RATEVHTSS4MCS4 0x4E
|
||||
#define DESC_RATEVHTSS4MCS5 0x4F
|
||||
#define DESC_RATEVHTSS4MCS6 0x50
|
||||
#define DESC_RATEVHTSS4MCS7 0x51
|
||||
#define DESC_RATEVHTSS4MCS8 0x52
|
||||
#define DESC_RATEVHTSS4MCS9 0x53
|
||||
|
||||
#define HDATA_RATE(rate)\
|
||||
(rate == DESC_RATE1M) ? "CCK_1M" :\
|
||||
(rate == DESC_RATE2M) ? "CCK_2M" :\
|
||||
(rate == DESC_RATE5_5M) ? "CCK5_5M" :\
|
||||
(rate == DESC_RATE11M) ? "CCK_11M" :\
|
||||
(rate == DESC_RATE6M) ? "OFDM_6M" :\
|
||||
(rate == DESC_RATE9M) ? "OFDM_9M" :\
|
||||
(rate == DESC_RATE12M) ? "OFDM_12M" :\
|
||||
(rate == DESC_RATE18M) ? "OFDM_18M" :\
|
||||
(rate == DESC_RATE24M) ? "OFDM_24M" :\
|
||||
(rate == DESC_RATE36M) ? "OFDM_36M" :\
|
||||
(rate == DESC_RATE48M) ? "OFDM_48M" :\
|
||||
(rate == DESC_RATE54M) ? "OFDM_54M" :\
|
||||
(rate == DESC_RATEMCS0) ? "MCS0" :\
|
||||
(rate == DESC_RATEMCS1) ? "MCS1" :\
|
||||
(rate == DESC_RATEMCS2) ? "MCS2" :\
|
||||
(rate == DESC_RATEMCS3) ? "MCS3" :\
|
||||
(rate == DESC_RATEMCS4) ? "MCS4" :\
|
||||
(rate == DESC_RATEMCS5) ? "MCS5" :\
|
||||
(rate == DESC_RATEMCS6) ? "MCS6" :\
|
||||
(rate == DESC_RATEMCS7) ? "MCS7" :\
|
||||
(rate == DESC_RATEMCS8) ? "MCS8" :\
|
||||
(rate == DESC_RATEMCS9) ? "MCS9" :\
|
||||
(rate == DESC_RATEMCS10) ? "MCS10" :\
|
||||
(rate == DESC_RATEMCS11) ? "MCS11" :\
|
||||
(rate == DESC_RATEMCS12) ? "MCS12" :\
|
||||
(rate == DESC_RATEMCS13) ? "MCS13" :\
|
||||
(rate == DESC_RATEMCS14) ? "MCS14" :\
|
||||
(rate == DESC_RATEMCS15) ? "MCS15" :\
|
||||
(rate == DESC_RATEMCS16) ? "MCS16" :\
|
||||
(rate == DESC_RATEMCS17) ? "MCS17" :\
|
||||
(rate == DESC_RATEMCS18) ? "MCS18" :\
|
||||
(rate == DESC_RATEMCS19) ? "MCS19" :\
|
||||
(rate == DESC_RATEMCS20) ? "MCS20" :\
|
||||
(rate == DESC_RATEMCS21) ? "MCS21" :\
|
||||
(rate == DESC_RATEMCS22) ? "MCS22" :\
|
||||
(rate == DESC_RATEMCS23) ? "MCS23" :\
|
||||
(rate == DESC_RATEVHTSS1MCS0) ? "VHTSS1MCS0" :\
|
||||
(rate == DESC_RATEVHTSS1MCS1) ? "VHTSS1MCS1" :\
|
||||
(rate == DESC_RATEVHTSS1MCS2) ? "VHTSS1MCS2" :\
|
||||
(rate == DESC_RATEVHTSS1MCS3) ? "VHTSS1MCS3" :\
|
||||
(rate == DESC_RATEVHTSS1MCS4) ? "VHTSS1MCS4" :\
|
||||
(rate == DESC_RATEVHTSS1MCS5) ? "VHTSS1MCS5" :\
|
||||
(rate == DESC_RATEVHTSS1MCS6) ? "VHTSS1MCS6" :\
|
||||
(rate == DESC_RATEVHTSS1MCS7) ? "VHTSS1MCS7" :\
|
||||
(rate == DESC_RATEVHTSS1MCS8) ? "VHTSS1MCS8" :\
|
||||
(rate == DESC_RATEVHTSS1MCS9) ? "VHTSS1MCS9" :\
|
||||
(rate == DESC_RATEVHTSS2MCS0) ? "VHTSS2MCS0" :\
|
||||
(rate == DESC_RATEVHTSS2MCS1) ? "VHTSS2MCS1" :\
|
||||
(rate == DESC_RATEVHTSS2MCS2) ? "VHTSS2MCS2" :\
|
||||
(rate == DESC_RATEVHTSS2MCS3) ? "VHTSS2MCS3" :\
|
||||
(rate == DESC_RATEVHTSS2MCS4) ? "VHTSS2MCS4" :\
|
||||
(rate == DESC_RATEVHTSS2MCS5) ? "VHTSS2MCS5" :\
|
||||
(rate == DESC_RATEVHTSS2MCS6) ? "VHTSS2MCS6" :\
|
||||
(rate == DESC_RATEVHTSS2MCS7) ? "VHTSS2MCS7" :\
|
||||
(rate == DESC_RATEVHTSS2MCS8) ? "VHTSS2MCS8" :\
|
||||
(rate == DESC_RATEVHTSS2MCS9) ? "VHTSS2MCS9" :\
|
||||
(rate == DESC_RATEVHTSS3MCS0) ? "VHTSS3MCS0" :\
|
||||
(rate == DESC_RATEVHTSS3MCS1) ? "VHTSS3MCS1" :\
|
||||
(rate == DESC_RATEVHTSS3MCS2) ? "VHTSS3MCS2" :\
|
||||
(rate == DESC_RATEVHTSS3MCS3) ? "VHTSS3MCS3" :\
|
||||
(rate == DESC_RATEVHTSS3MCS4) ? "VHTSS3MCS4" :\
|
||||
(rate == DESC_RATEVHTSS3MCS5) ? "VHTSS3MCS5" :\
|
||||
(rate == DESC_RATEVHTSS3MCS6) ? "VHTSS3MCS6" :\
|
||||
(rate == DESC_RATEVHTSS3MCS7) ? "VHTSS3MCS7" :\
|
||||
(rate == DESC_RATEVHTSS3MCS8) ? "VHTSS3MCS8" :\
|
||||
(rate == DESC_RATEVHTSS3MCS9) ? "VHTSS3MCS9" : "UNKNOWN"
|
||||
|
||||
enum {
|
||||
UP_LINK,
|
||||
DOWN_LINK,
|
||||
};
|
||||
typedef enum _RT_MEDIA_STATUS {
|
||||
RT_MEDIA_DISCONNECT = 0,
|
||||
RT_MEDIA_CONNECT = 1
|
||||
} RT_MEDIA_STATUS;
|
||||
|
||||
#define MAX_DLFW_PAGE_SIZE 4096 /* @ page : 4k bytes */
|
||||
typedef enum _FIRMWARE_SOURCE {
|
||||
FW_SOURCE_IMG_FILE = 0,
|
||||
FW_SOURCE_HEADER_FILE = 1, /* from header file */
|
||||
} FIRMWARE_SOURCE, *PFIRMWARE_SOURCE;
|
||||
|
||||
typedef enum _CH_SW_USE_CASE {
|
||||
CH_SW_USE_CASE_TDLS = 0,
|
||||
CH_SW_USE_CASE_MCC = 1
|
||||
} CH_SW_USE_CASE;
|
||||
|
||||
typedef enum _WAKEUP_REASON{
|
||||
RX_PAIRWISEKEY = 0x01,
|
||||
RX_GTK = 0x02,
|
||||
RX_FOURWAY_HANDSHAKE = 0x03,
|
||||
RX_DISASSOC = 0x04,
|
||||
RX_DEAUTH = 0x08,
|
||||
RX_ARP_REQUEST = 0x09,
|
||||
FW_DECISION_DISCONNECT = 0x10,
|
||||
RX_MAGIC_PKT = 0x21,
|
||||
RX_UNICAST_PKT = 0x22,
|
||||
RX_PATTERN_PKT = 0x23,
|
||||
RTD3_SSID_MATCH = 0x24,
|
||||
RX_REALWOW_V2_WAKEUP_PKT = 0x30,
|
||||
RX_REALWOW_V2_ACK_LOST = 0x31,
|
||||
ENABLE_FAIL_DMA_IDLE = 0x40,
|
||||
ENABLE_FAIL_DMA_PAUSE = 0x41,
|
||||
RTIME_FAIL_DMA_IDLE = 0x42,
|
||||
RTIME_FAIL_DMA_PAUSE = 0x43,
|
||||
RX_PNO = 0x55,
|
||||
AP_OFFLOAD_WAKEUP = 0x66,
|
||||
CLK_32K_UNLOCK = 0xFD,
|
||||
CLK_32K_LOCK = 0xFE
|
||||
}WAKEUP_REASON;
|
||||
|
||||
/*
|
||||
* Queue Select Value in TxDesc
|
||||
* */
|
||||
#define QSLT_BK 0x2/* 0x01 */
|
||||
#define QSLT_BE 0x0
|
||||
#define QSLT_VI 0x5/* 0x4 */
|
||||
#define QSLT_VO 0x7/* 0x6 */
|
||||
#define QSLT_BEACON 0x10
|
||||
#define QSLT_HIGH 0x11
|
||||
#define QSLT_MGNT 0x12
|
||||
#define QSLT_CMD 0x13
|
||||
|
||||
/* BK, BE, VI, VO, HCCA, MANAGEMENT, COMMAND, HIGH, BEACON.
|
||||
* #define MAX_TX_QUEUE 9 */
|
||||
|
||||
#define TX_SELE_HQ BIT(0) /* High Queue */
|
||||
#define TX_SELE_LQ BIT(1) /* Low Queue */
|
||||
#define TX_SELE_NQ BIT(2) /* Normal Queue */
|
||||
#define TX_SELE_EQ BIT(3) /* Extern Queue */
|
||||
|
||||
#define PageNum_128(_Len) (u32)(((_Len)>>7) + ((_Len) & 0x7F ? 1 : 0))
|
||||
#define PageNum_256(_Len) (u32)(((_Len)>>8) + ((_Len) & 0xFF ? 1 : 0))
|
||||
#define PageNum_512(_Len) (u32)(((_Len)>>9) + ((_Len) & 0x1FF ? 1 : 0))
|
||||
#define PageNum(_Len, _Size) (u32)(((_Len)/(_Size)) + ((_Len)&((_Size) - 1) ? 1 : 0))
|
||||
|
||||
struct dbg_rx_counter {
|
||||
u32 rx_pkt_ok;
|
||||
u32 rx_pkt_crc_error;
|
||||
u32 rx_pkt_drop;
|
||||
u32 rx_ofdm_fa;
|
||||
u32 rx_cck_fa;
|
||||
u32 rx_ht_fa;
|
||||
};
|
||||
|
||||
#ifdef CONFIG_MBSSID_CAM
|
||||
#define DBG_MBID_CAM_DUMP
|
||||
|
||||
void rtw_mbid_cam_init(struct dvobj_priv *dvobj);
|
||||
void rtw_mbid_cam_deinit(struct dvobj_priv *dvobj);
|
||||
void rtw_mbid_cam_reset(_adapter *adapter);
|
||||
u8 rtw_get_max_mbid_cam_id(_adapter *adapter);
|
||||
u8 rtw_get_mbid_cam_entry_num(_adapter *adapter);
|
||||
int rtw_mbid_cam_cache_dump(void *sel, const char *fun_name , _adapter *adapter);
|
||||
int rtw_mbid_cam_dump(void *sel, const char *fun_name, _adapter *adapter);
|
||||
void rtw_mbid_cam_restore(_adapter *adapter);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MI_WITH_MBSSID_CAM
|
||||
void rtw_hal_set_macaddr_mbid(_adapter *adapter, u8 *mac_addr);
|
||||
void rtw_hal_change_macaddr_mbid(_adapter *adapter, u8 *mac_addr);
|
||||
#ifdef CONFIG_SWTIMER_BASED_TXBCN
|
||||
u16 rtw_hal_bcn_interval_adjust(_adapter *adapter, u16 bcn_interval);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
void rtw_dump_mac_rx_counters(_adapter *padapter, struct dbg_rx_counter *rx_counter);
|
||||
void rtw_dump_phy_rx_counters(_adapter *padapter, struct dbg_rx_counter *rx_counter);
|
||||
void rtw_reset_mac_rx_counters(_adapter *padapter);
|
||||
void rtw_reset_phy_rx_counters(_adapter *padapter);
|
||||
void rtw_reset_phy_trx_ok_counters(_adapter *padapter);
|
||||
|
||||
#ifdef DBG_RX_COUNTER_DUMP
|
||||
#define DUMP_DRV_RX_COUNTER BIT0
|
||||
#define DUMP_MAC_RX_COUNTER BIT1
|
||||
#define DUMP_PHY_RX_COUNTER BIT2
|
||||
#define DUMP_DRV_TRX_COUNTER_DATA BIT3
|
||||
|
||||
void rtw_dump_phy_rxcnts_preprocess(_adapter *padapter, u8 rx_cnt_mode);
|
||||
void rtw_dump_rx_counters(_adapter *padapter);
|
||||
#endif
|
||||
|
||||
void dump_chip_info(HAL_VERSION ChipVersion);
|
||||
void rtw_hal_config_rftype(PADAPTER padapter);
|
||||
|
||||
#define BAND_CAP_2G BIT0
|
||||
#define BAND_CAP_5G BIT1
|
||||
#define BAND_CAP_BIT_NUM 2
|
||||
|
||||
#define BW_CAP_5M BIT0
|
||||
#define BW_CAP_10M BIT1
|
||||
#define BW_CAP_20M BIT2
|
||||
#define BW_CAP_40M BIT3
|
||||
#define BW_CAP_80M BIT4
|
||||
#define BW_CAP_160M BIT5
|
||||
#define BW_CAP_80_80M BIT6
|
||||
#define BW_CAP_BIT_NUM 7
|
||||
|
||||
#define PROTO_CAP_11B BIT0
|
||||
#define PROTO_CAP_11G BIT1
|
||||
#define PROTO_CAP_11N BIT2
|
||||
#define PROTO_CAP_11AC BIT3
|
||||
#define PROTO_CAP_BIT_NUM 4
|
||||
|
||||
#define WL_FUNC_P2P BIT0
|
||||
#define WL_FUNC_MIRACAST BIT1
|
||||
#define WL_FUNC_TDLS BIT2
|
||||
#define WL_FUNC_FTM BIT3
|
||||
#define WL_FUNC_BIT_NUM 4
|
||||
|
||||
#define TBTT_PROHIBIT_SETUP_TIME 0x04 /* 128us, unit is 32us */
|
||||
#define TBTT_PROHIBIT_HOLD_TIME 0x80 /* 4ms, unit is 32us*/
|
||||
#define TBTT_PROHIBIT_HOLD_TIME_STOP_BCN 0x64 /* 3.2ms unit is 32us*/
|
||||
|
||||
int hal_spec_init(_adapter *adapter);
|
||||
void dump_hal_spec(void *sel, _adapter *adapter);
|
||||
|
||||
bool hal_chk_band_cap(_adapter *adapter, u8 cap);
|
||||
bool hal_chk_bw_cap(_adapter *adapter, u8 cap);
|
||||
bool hal_chk_proto_cap(_adapter *adapter, u8 cap);
|
||||
bool hal_is_band_support(_adapter *adapter, u8 band);
|
||||
bool hal_is_bw_support(_adapter *adapter, u8 bw);
|
||||
bool hal_is_wireless_mode_support(_adapter *adapter, u8 mode);
|
||||
u8 hal_largest_bw(_adapter *adapter, u8 in_bw);
|
||||
|
||||
bool hal_chk_wl_func(_adapter *adapter, u8 func);
|
||||
|
||||
void hal_com_config_channel_plan(
|
||||
IN PADAPTER padapter,
|
||||
IN char *hw_alpha2,
|
||||
IN u8 hw_chplan,
|
||||
IN char *sw_alpha2,
|
||||
IN u8 sw_chplan,
|
||||
IN u8 def_chplan,
|
||||
IN BOOLEAN AutoLoadFail
|
||||
);
|
||||
|
||||
int hal_config_macaddr(_adapter *adapter, bool autoload_fail);
|
||||
|
||||
BOOLEAN
|
||||
HAL_IsLegalChannel(
|
||||
IN PADAPTER Adapter,
|
||||
IN u32 Channel
|
||||
);
|
||||
|
||||
u8 MRateToHwRate(u8 rate);
|
||||
|
||||
u8 hw_rate_to_m_rate(u8 rate);
|
||||
|
||||
void HalSetBrateCfg(
|
||||
IN PADAPTER Adapter,
|
||||
IN u8 *mBratesOS,
|
||||
OUT u16 *pBrateCfg);
|
||||
|
||||
BOOLEAN
|
||||
Hal_MappingOutPipe(
|
||||
IN PADAPTER pAdapter,
|
||||
IN u8 NumOutPipe
|
||||
);
|
||||
|
||||
void rtw_dump_fw_info(void *sel, _adapter *adapter);
|
||||
void rtw_restore_hw_port_cfg(_adapter *adapter);
|
||||
void rtw_restore_mac_addr(_adapter *adapter);/*set mac addr when hal_init for all iface*/
|
||||
void rtw_hal_dump_macaddr(void *sel, _adapter *adapter);
|
||||
|
||||
void rtw_init_hal_com_default_value(PADAPTER Adapter);
|
||||
|
||||
#ifdef CONFIG_FW_C2H_REG
|
||||
void c2h_evt_clear(_adapter *adapter);
|
||||
s32 c2h_evt_read_88xx(_adapter *adapter, u8 *buf);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FW_C2H_PKT
|
||||
void rtw_hal_c2h_pkt_pre_hdl(_adapter *adapter, u8 *buf, u16 len);
|
||||
void rtw_hal_c2h_pkt_hdl(_adapter *adapter, u8 *buf, u16 len);
|
||||
#endif
|
||||
|
||||
u8 rtw_get_mgntframe_raid(_adapter *adapter, unsigned char network_type);
|
||||
|
||||
void rtw_hal_update_sta_wset(_adapter *adapter, struct sta_info *psta);
|
||||
s8 rtw_get_sta_rx_nss(_adapter *adapter, struct sta_info *psta);
|
||||
s8 rtw_get_sta_tx_nss(_adapter *adapter, struct sta_info *psta);
|
||||
void rtw_hal_update_sta_ra_info(PADAPTER padapter, struct sta_info *psta);
|
||||
|
||||
/* access HW only */
|
||||
u32 rtw_sec_read_cam(_adapter *adapter, u8 addr);
|
||||
void rtw_sec_write_cam(_adapter *adapter, u8 addr, u32 wdata);
|
||||
void rtw_sec_read_cam_ent(_adapter *adapter, u8 id, u8 *ctrl, u8 *mac, u8 *key);
|
||||
void rtw_sec_write_cam_ent(_adapter *adapter, u8 id, u16 ctrl, u8 *mac, u8 *key);
|
||||
void rtw_sec_clr_cam_ent(_adapter *adapter, u8 id);
|
||||
bool rtw_sec_read_cam_is_gk(_adapter *adapter, u8 id);
|
||||
|
||||
u8 rtw_hal_rcr_check(_adapter *adapter, u32 check_bit);
|
||||
|
||||
u8 rtw_hal_rcr_add(_adapter *adapter, u32 add);
|
||||
u8 rtw_hal_rcr_clear(_adapter *adapter, u32 clear);
|
||||
void rtw_hal_rcr_set_chk_bssid(_adapter *adapter, u8 self_action);
|
||||
|
||||
void hw_var_port_switch(_adapter *adapter);
|
||||
|
||||
u8 SetHwReg(PADAPTER padapter, u8 variable, u8 *val);
|
||||
void GetHwReg(PADAPTER padapter, u8 variable, u8 *val);
|
||||
void rtw_hal_check_rxfifo_full(_adapter *adapter);
|
||||
void rtw_hal_reqtxrpt(_adapter *padapter, u8 macid);
|
||||
|
||||
u8 SetHalDefVar(_adapter *adapter, HAL_DEF_VARIABLE variable, void *value);
|
||||
u8 GetHalDefVar(_adapter *adapter, HAL_DEF_VARIABLE variable, void *value);
|
||||
|
||||
BOOLEAN
|
||||
eqNByte(
|
||||
u8 *str1,
|
||||
u8 *str2,
|
||||
u32 num
|
||||
);
|
||||
|
||||
u32
|
||||
MapCharToHexDigit(
|
||||
IN char chTmp
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
GetHexValueFromString(
|
||||
IN char *szStr,
|
||||
IN OUT u32 *pu4bVal,
|
||||
IN OUT u32 *pu4bMove
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
GetFractionValueFromString(
|
||||
IN char *szStr,
|
||||
IN OUT u8 *pInteger,
|
||||
IN OUT u8 *pFraction,
|
||||
IN OUT u32 *pu4bMove
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
IsCommentString(
|
||||
IN char *szStr
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
ParseQualifiedString(
|
||||
IN char *In,
|
||||
IN OUT u32 *Start,
|
||||
OUT char *Out,
|
||||
IN char LeftQualifier,
|
||||
IN char RightQualifier
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
GetU1ByteIntegerFromStringInDecimal(
|
||||
IN char *Str,
|
||||
IN OUT u8 *pInt
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
isAllSpaceOrTab(
|
||||
u8 *data,
|
||||
u8 size
|
||||
);
|
||||
|
||||
void linked_info_dump(_adapter *padapter, u8 benable);
|
||||
#ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA
|
||||
void rtw_get_raw_rssi_info(void *sel, _adapter *padapter);
|
||||
void rtw_dump_raw_rssi_info(_adapter *padapter, void *sel);
|
||||
#endif
|
||||
|
||||
#ifdef DBG_RX_DFRAME_RAW_DATA
|
||||
void rtw_dump_rx_dframe_info(_adapter *padapter, void *sel);
|
||||
#endif
|
||||
void rtw_store_phy_info(_adapter *padapter, union recv_frame *prframe);
|
||||
#define HWSET_MAX_SIZE 1024
|
||||
#ifdef CONFIG_EFUSE_CONFIG_FILE
|
||||
#define EFUSE_FILE_COLUMN_NUM 16
|
||||
u32 Hal_readPGDataFromConfigFile(PADAPTER padapter);
|
||||
u32 Hal_ReadMACAddrFromFile(PADAPTER padapter, u8 *mac_addr);
|
||||
#endif /* CONFIG_EFUSE_CONFIG_FILE */
|
||||
|
||||
int check_phy_efuse_tx_power_info_valid(PADAPTER padapter);
|
||||
int hal_efuse_macaddr_offset(_adapter *adapter);
|
||||
int Hal_GetPhyEfuseMACAddr(PADAPTER padapter, u8 *mac_addr);
|
||||
void rtw_dump_cur_efuse(PADAPTER padapter);
|
||||
|
||||
#ifdef CONFIG_RF_POWER_TRIM
|
||||
void rtw_bb_rf_gain_offset(_adapter *padapter);
|
||||
#endif /*CONFIG_RF_POWER_TRIM*/
|
||||
|
||||
void dm_DynamicUsbTxAgg(_adapter *padapter, u8 from_timer);
|
||||
u8 rtw_hal_busagg_qsel_check(_adapter *padapter, u8 pre_qsel, u8 next_qsel);
|
||||
|
||||
u8 rtw_get_current_tx_rate(_adapter *padapter, struct sta_info *psta);
|
||||
u8 rtw_get_current_tx_sgi(_adapter *padapter, struct sta_info *psta);
|
||||
void rtw_hal_construct_NullFunctionData(PADAPTER, u8 *pframe, u32 *pLength, u8 *StaAddr, u8 bQoS, u8 AC, u8 bEosp, u8 bForcePowerSave);
|
||||
|
||||
void rtw_hal_set_fw_rsvd_page(_adapter *adapter, bool finished);
|
||||
u8 rtw_hal_get_rsvd_page_num(struct _ADAPTER *adapter);
|
||||
|
||||
#ifdef CONFIG_TSF_RESET_OFFLOAD
|
||||
int rtw_hal_reset_tsf(_adapter *adapter, u8 reset_port);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_TDLS
|
||||
#ifdef CONFIG_TDLS_CH_SW
|
||||
s32 rtw_hal_ch_sw_oper_offload(_adapter *padapter, u8 channel, u8 channel_offset, u16 bwmode);
|
||||
#endif
|
||||
#endif
|
||||
#if defined(CONFIG_BT_COEXIST) && defined(CONFIG_FW_MULTI_PORT_SUPPORT)
|
||||
s32 rtw_hal_set_wifi_port_id_cmd(_adapter *adapter);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_GPIO_API
|
||||
u8 rtw_hal_get_gpio(_adapter *adapter, u8 gpio_num);
|
||||
int rtw_hal_set_gpio_output_value(_adapter *adapter, u8 gpio_num, bool isHigh);
|
||||
int rtw_hal_config_gpio(_adapter *adapter, u8 gpio_num, bool isOutput);
|
||||
int rtw_hal_register_gpio_interrupt(_adapter *adapter, int gpio_num, void(*callback)(u8 level));
|
||||
int rtw_hal_disable_gpio_interrupt(_adapter *adapter, int gpio_num);
|
||||
#endif
|
||||
|
||||
s8 rtw_hal_ch_sw_iqk_info_search(_adapter *padapter, u8 central_chnl, u8 bw_mode);
|
||||
void rtw_hal_ch_sw_iqk_info_backup(_adapter *adapter);
|
||||
void rtw_hal_ch_sw_iqk_info_restore(_adapter *padapter, u8 ch_sw_use_case);
|
||||
|
||||
#ifdef CONFIG_GPIO_WAKEUP
|
||||
void rtw_hal_switch_gpio_wl_ctrl(_adapter *padapter, u8 index, u8 enable);
|
||||
void rtw_hal_set_output_gpio(_adapter *padapter, u8 index, u8 outputval);
|
||||
void rtw_hal_set_input_gpio(_adapter *padapter, u8 index);
|
||||
#endif
|
||||
|
||||
void update_IOT_info(_adapter *padapter);
|
||||
|
||||
void hal_set_crystal_cap(_adapter *adapter, u8 crystal_cap);
|
||||
void rtw_hal_correct_tsf(_adapter *padapter, u8 hw_port, u64 tsf);
|
||||
|
||||
void ResumeTxBeacon(_adapter *padapter);
|
||||
void StopTxBeacon(_adapter *padapter);
|
||||
#ifdef CONFIG_MI_WITH_MBSSID_CAM /*HW port0 - MBSS*/
|
||||
void hw_var_set_opmode_mbid(_adapter *Adapter, u8 mode);
|
||||
u8 rtw_mbid_camid_alloc(_adapter *adapter, u8 *mac_addr);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ANTENNA_DIVERSITY
|
||||
u8 rtw_hal_antdiv_before_linked(_adapter *padapter);
|
||||
void rtw_hal_antdiv_rssi_compared(_adapter *padapter, WLAN_BSSID_EX *dst, WLAN_BSSID_EX *src);
|
||||
#endif
|
||||
|
||||
#ifdef DBG_SEC_CAM_MOVE
|
||||
void rtw_hal_move_sta_gk_to_dk(_adapter *adapter);
|
||||
void rtw_hal_read_sta_dk_key(_adapter *adapter, u8 key_id);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_LPS_PG
|
||||
#define LPSPG_RSVD_PAGE_SET_MACID(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x00, 0, 8, _value)/*used macid*/
|
||||
#define LPSPG_RSVD_PAGE_SET_MBSSCAMID(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x00, 8, 8, _value)/*used BSSID CAM entry*/
|
||||
#define LPSPG_RSVD_PAGE_SET_PMC_NUM(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x00, 16, 8, _value)/*Max used Pattern Match CAM entry*/
|
||||
#define LPSPG_RSVD_PAGE_SET_MU_RAID_GID(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x00, 24, 8, _value)/*Max MU rate table Group ID*/
|
||||
#define LPSPG_RSVD_PAGE_SET_SEC_CAM_NUM(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x04, 0, 8, _value)/*used Security CAM entry number*/
|
||||
#define LPSPG_RSVD_PAGE_SET_DRV_RSVDPAGE_NUM(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x04, 8, 8, _value)/*Txbuf used page number for fw offload*/
|
||||
#define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID1(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x08, 0, 8, _value)/*used Security CAM entry -1*/
|
||||
#define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID2(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x08, 8, 8, _value)/*used Security CAM entry -2*/
|
||||
#define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID3(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x08, 16, 8, _value)/*used Security CAM entry -3*/
|
||||
#define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID4(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x08, 24, 8, _value)/*used Security CAM entry -4*/
|
||||
#define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID5(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x0C, 0, 8, _value)/*used Security CAM entry -5*/
|
||||
#define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID6(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x0C, 8, 8, _value)/*used Security CAM entry -6*/
|
||||
#define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID7(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x0C, 16, 8, _value)/*used Security CAM entry -7*/
|
||||
#define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID8(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x0C, 24, 8, _value)/*used Security CAM entry -8*/
|
||||
enum lps_pg_hdl_id {
|
||||
LPS_PG_INFO_CFG = 0,
|
||||
LPS_PG_REDLEMEM,
|
||||
LPS_PG_RESEND_H2C,
|
||||
};
|
||||
|
||||
u8 rtw_hal_set_lps_pg_info(_adapter *adapter);
|
||||
#endif
|
||||
|
||||
int rtw_hal_get_rsvd_page(_adapter *adapter, u32 page_offset, u32 page_num, u8 *buffer, u32 buffer_size);
|
||||
|
||||
#ifdef CONFIG_WOWLAN
|
||||
struct rtl_wow_pattern {
|
||||
u16 crc;
|
||||
u8 type;
|
||||
u32 mask[4];
|
||||
};
|
||||
void rtw_wow_pattern_cam_dump(_adapter *adapter);
|
||||
|
||||
#ifdef CONFIG_WOW_PATTERN_HW_CAM
|
||||
void rtw_wow_pattern_read_cam_ent(_adapter *adapter, u8 id, struct rtl_wow_pattern *context);
|
||||
void rtw_dump_wow_pattern(void *sel, struct rtl_wow_pattern *pwow_pattern, u8 idx);
|
||||
#endif
|
||||
|
||||
struct rtw_ndp_info {
|
||||
u8 enable:1;
|
||||
u8 check_remote_ip:1; /* Need to Check Sender IP or not */
|
||||
u8 rsvd:6;
|
||||
u8 num_of_target_ip; /* Number of Check IP which NA query IP */
|
||||
u8 target_link_addr[6]; /* DUT's MAC address */
|
||||
u8 remote_ipv6_addr[16]; /* Just respond IP */
|
||||
u8 target_ipv6_addr[16]; /* target IP */
|
||||
};
|
||||
#define REMOTE_INFO_CTRL_SET_VALD_EN(target, _value) \
|
||||
SET_BITS_TO_LE_4BYTE(target + 0, 0, 8, _value)
|
||||
#define REMOTE_INFO_CTRL_SET_PTK_EN(target, _value) \
|
||||
SET_BITS_TO_LE_4BYTE(target + 1, 0, 1, _value)
|
||||
#define REMOTE_INFO_CTRL_SET_GTK_EN(target, _value) \
|
||||
SET_BITS_TO_LE_4BYTE(target + 1, 1, 1, _value)
|
||||
#define REMOTE_INFO_CTRL_SET_GTK_IDX(target, _value) \
|
||||
SET_BITS_TO_LE_4BYTE(target + 2, 0, 8, _value)
|
||||
#endif /*CONFIG_WOWLAN*/
|
||||
|
||||
void rtw_dump_phy_cap(void *sel, _adapter *adapter);
|
||||
void rtw_dump_rsvd_page(void *sel, _adapter *adapter, u8 page_offset, u8 page_num);
|
||||
#ifdef CONFIG_SUPPORT_FIFO_DUMP
|
||||
void rtw_dump_fifo(void *sel, _adapter *adapter, u8 fifo_sel, u32 fifo_addr, u32 fifo_size);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FW_MULTI_PORT_SUPPORT
|
||||
s32 rtw_hal_set_default_port_id_cmd(_adapter *adapter, u8 mac_id);
|
||||
s32 rtw_set_default_port_id(_adapter *adapter);
|
||||
s32 rtw_set_ps_rsvd_page(_adapter *adapter);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_P2P_PS
|
||||
#ifdef RTW_HALMAC
|
||||
void rtw_set_p2p_ps_offload_cmd(_adapter *adapter, u8 p2p_ps_state);
|
||||
#endif
|
||||
#endif
|
||||
s16 translate_dbm_to_percentage(s16 signal);
|
||||
|
||||
#ifdef CONFIG_SWTIMER_BASED_TXBCN
|
||||
#ifdef CONFIG_BCN_RECOVERY
|
||||
u8 rtw_ap_bcn_recovery(_adapter *padapter);
|
||||
#endif
|
||||
#ifdef CONFIG_BCN_XMIT_PROTECT
|
||||
u8 rtw_ap_bcn_queue_empty_check(_adapter *padapter, u32 txbcn_timer_ms);
|
||||
#endif
|
||||
#endif /*CONFIG_SWTIMER_BASED_TXBCN*/
|
||||
|
||||
#endif /* __HAL_COMMON_H__ */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,204 @@
|
||||
/* C glue: owns a bb_info and drives the vendored halbb-G6 BB functions for
|
||||
* both Kestrel chips. Compiled as C behind the shim (hal/halbb/
|
||||
* hal_headers_le.h). See the header. */
|
||||
#include "halbb_precomp.h" /* full bb_info + halbb types + BB functions */
|
||||
#include "kestrel_halbb_glue.h"
|
||||
|
||||
struct kestrel_halbb_ctx {
|
||||
struct bb_info bb;
|
||||
struct rtw_hal_com_t hal;
|
||||
struct rtw_phl_com_t phl;
|
||||
struct bb_cmn_info cmn;
|
||||
int env_mntr_ready; /* lazy halbb_env_mntr init done */
|
||||
};
|
||||
|
||||
struct kestrel_halbb_ctx *kestrel_halbb_create(struct kestrel_halbb_bridge *br,
|
||||
enum kestrel_chip chip,
|
||||
unsigned char cut,
|
||||
unsigned char rfe_type) {
|
||||
struct kestrel_halbb_ctx *c =
|
||||
(struct kestrel_halbb_ctx *)malloc(sizeof(struct kestrel_halbb_ctx));
|
||||
if (!c)
|
||||
return 0;
|
||||
_os_mem_set(0, c, 0, sizeof(*c));
|
||||
|
||||
c->hal.drv_priv = br; /* -> kestrel_halbb_bridge (register plane) */
|
||||
c->hal.cv = cut;
|
||||
c->phl.dev_cap.rfe_type = rfe_type;
|
||||
|
||||
c->bb.hal_com = &c->hal;
|
||||
c->bb.phl_com = &c->phl;
|
||||
c->bb.bb_cmn_hooker = &c->cmn;
|
||||
c->bb.bb_phy_idx = HW_PHY_0;
|
||||
if (chip == KESTREL_CHIP_8852B) {
|
||||
c->bb.ic_type = BB_RTL8852B;
|
||||
c->bb.ic_sub_type = BB_IC_SUB_TYPE_8852B_8852B;
|
||||
c->hal.chip_id = CHIP_WIFI6_8852B;
|
||||
} else {
|
||||
c->bb.ic_type = BB_RTL8852C;
|
||||
c->bb.ic_sub_type = BB_IC_SUB_TYPE_8852C_8852C;
|
||||
c->hal.chip_id = CHIP_WIFI6_8852C;
|
||||
}
|
||||
c->bb.rx_path = RF_PATH_AB;
|
||||
/* Both supported dies are 2SS / 2 RF paths. The vendor derives these in
|
||||
* halbb_cmn_info_self_init from ic_type; the minimal bring-up must set them
|
||||
* itself — halbb_physts_parsing_init shifts a
|
||||
* halbb_gen_mask_from_0(num_rf_path) into the physts IE04..07 bits, so a
|
||||
* zero here silently disables the per-path IE pages (per-antenna SNR/EVM). */
|
||||
c->bb.num_rf_path = 2;
|
||||
c->bb.num_tx_path = 2;
|
||||
c->bb.num_ss = 2;
|
||||
c->bb.cr_type = BB_CLIENT; /* USB client CR bank; without it the env-monitor
|
||||
* CR-init switch falls through and the NHM
|
||||
* ready-bit address stays 0 (report never rdy) */
|
||||
c->bb.bb0_cr_offset = 0; /* bridge adds the BB window (wIndex=1) */
|
||||
/* halbb_init_cr_default guards on this flag; it asserts exactly the wiring
|
||||
* done above (hal_com/phl_com/bb_cmn_hooker present). */
|
||||
c->bb.bb_cmn_info_init_ready = true;
|
||||
br->bb_info = &c->bb; /* halrf's cross-plane rtw_hal_bb_* calls (shim) */
|
||||
return c;
|
||||
}
|
||||
|
||||
/* Apply the built-in BB register table + load the gain table + the efuse RX
|
||||
* gain offsets — the vendor's own loader flow (halbb_init_reg ->
|
||||
* halbb_init_cr_default + halbb_init_gain_table + halbb_get_efuse_ofst_init),
|
||||
* walking the vendored hwimg arrays with the vendor's check-positive engine.
|
||||
* Returns nonzero on success. */
|
||||
int kestrel_halbb_init_reg(struct kestrel_halbb_ctx *ctx) {
|
||||
if (!ctx)
|
||||
return 0;
|
||||
return halbb_init_reg(&ctx->bb) ? 1 : 0;
|
||||
}
|
||||
|
||||
void kestrel_halbb_rx_bringup(struct kestrel_halbb_ctx *ctx) {
|
||||
if (!ctx)
|
||||
return;
|
||||
struct bb_info *bb = &ctx->bb;
|
||||
/* The gain cache (bb_gain_i) is populated by kestrel_halbb_init_reg's
|
||||
* halbb_init_gain_table; this entry owns the front-end routing + chains. */
|
||||
/* LNAON / TRSW / PAPE RF-front-end routing (the both-bands deafness fix on
|
||||
* the 8852C). Vendor core dispatcher — per-chip via ic_type. */
|
||||
halbb_gpio_setting_init(bb);
|
||||
/* Enable both RX chains (rx_path_en). Vendor core dispatcher; its 8852C
|
||||
* case passes hal_com->dbcc_en (0 here) — same as the direct call did. */
|
||||
halbb_ctrl_rx_path(bb, RF_PATH_AB, HW_PHY_0);
|
||||
|
||||
/* 8852C physts MEASUREMENT bring-up. Devourer's minimal halbb bring-up runs
|
||||
* only halbb_init_reg (BB table) + this, skipping the vendor's
|
||||
* halbb_dm_init_per_phy measurement inits. On the 8852B the physts engine
|
||||
* fills reports anyway (its table covers it); on the 8852C the reports arrive
|
||||
* EMPTY (is_valid=0) without these — halbb_ic_hw_setting_init_8852c sets the
|
||||
* BB evm/measurement report-enable (0xa10[0]), and the physts CR map + IE
|
||||
* bitmap must be programmed for the engine to snapshot RSSI/SNR/EVM. */
|
||||
#ifdef BB_8852C_SUPPORT
|
||||
if (bb->ic_type == BB_RTL8852C) {
|
||||
halbb_ic_hw_setting_init_8852c(bb); /* 0xa10[0] evm/measurement rpt-en */
|
||||
halbb_cr_cfg_physts_init(bb);
|
||||
halbb_physts_parsing_init(bb);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
void kestrel_halbb_set_gain(struct kestrel_halbb_ctx *ctx, unsigned char central_ch,
|
||||
unsigned char band_type) {
|
||||
if (!ctx)
|
||||
return;
|
||||
struct bb_info *bb = &ctx->bb;
|
||||
if (bb->ic_type == BB_RTL8852B) {
|
||||
#ifdef BB_8852B_SUPPORT
|
||||
/* The 8852B loader applies both paths in one call (no efem arg). */
|
||||
halbb_set_gain_error_8852b(bb, central_ch, (enum band_type)band_type);
|
||||
#endif
|
||||
} else {
|
||||
#ifdef BB_8852C_SUPPORT
|
||||
/* is_efem=false (compact USB dongle, no external LNA). Vendor skips 2.4G
|
||||
* gain-error internally. */
|
||||
halbb_set_gain_error_8852c(bb, central_ch, (enum band_type)band_type,
|
||||
false, RF_PATH_A);
|
||||
halbb_set_gain_error_8852c(bb, central_ch, (enum band_type)band_type,
|
||||
false, RF_PATH_B);
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
void kestrel_halbb_ctrl_bw_ch(struct kestrel_halbb_ctx *ctx, unsigned char pri_ch,
|
||||
unsigned char central_ch, unsigned char bw,
|
||||
unsigned char band_type) {
|
||||
if (!ctx)
|
||||
return;
|
||||
/* Vendor core dispatcher (halbb_api.c): its per-chip case forwards to
|
||||
* halbb_ctrl_bw_ch_<chip> with these exact arguments (seg1 is 80+80-only,
|
||||
* unused on both chips). */
|
||||
halbb_ctrl_bw_ch(&ctx->bb, pri_ch, central_ch, /*central_ch_seg1=*/0,
|
||||
(enum band_type)band_type, (enum channel_width)bw,
|
||||
HW_PHY_0);
|
||||
}
|
||||
|
||||
void kestrel_halbb_ctrl_tx_path(struct kestrel_halbb_ctx *ctx) {
|
||||
/* 8852C-only: the 8852B routes TX antennas per-STA via the CMAC antenna
|
||||
* model (TXWD/cctl), there is no path-com block to program. */
|
||||
#ifdef BB_8852C_SUPPORT
|
||||
if (ctx && ctx->bb.ic_type == BB_RTL8852C)
|
||||
halbb_ctrl_tx_path_tmac_8852c(&ctx->bb, RF_PATH_A, false);
|
||||
#else
|
||||
(void)ctx;
|
||||
#endif
|
||||
}
|
||||
|
||||
/* One-shot active/frame-free NHM absolute noise floor. See the header. */
|
||||
int kestrel_halbb_env_mntr_nhm(struct kestrel_halbb_ctx *ctx,
|
||||
unsigned short mntr_time_ms,
|
||||
signed char *nhm_pwr_dbm) {
|
||||
struct bb_info *bb;
|
||||
struct ccx_para_info para;
|
||||
struct env_trig_rpt trig;
|
||||
struct env_mntr_rpt rpt;
|
||||
void *drv;
|
||||
u16 mtime;
|
||||
int i;
|
||||
|
||||
if (!ctx || !nhm_pwr_dbm)
|
||||
return 0;
|
||||
bb = &ctx->bb;
|
||||
drv = bb->hal_com->drv_priv;
|
||||
mtime = mntr_time_ms ? mntr_time_ms : 100;
|
||||
|
||||
/* Lazy env-monitor init: the RX bring-up flow (kestrel_halbb_init_reg) only
|
||||
* runs halbb_init_reg, so the NHM CR addresses (incl. nhm_rdy) and the ccx/nhm
|
||||
* state are still zero. Run the two vendor inits once before the first
|
||||
* trigger. */
|
||||
if (!ctx->env_mntr_ready) {
|
||||
halbb_cr_cfg_env_mntr_init(bb);
|
||||
halbb_env_mntr_init(bb);
|
||||
ctx->env_mntr_ready = 1;
|
||||
}
|
||||
|
||||
/* One-shot NHM in the vendor's IEEE-11k idle-noise mode. A zeroed para gives
|
||||
* nhm_incld_cca=NHM_EXCLUDE_CCA + nav/rssi gating DISABLED (all enum 0). */
|
||||
_os_mem_set(0, ¶, 0, sizeof(para));
|
||||
para.rac_lv = RAC_LV_4; /* debug priority: always wins the racing arbiter */
|
||||
para.mntr_time = mtime; /* ms; drives ccx_period (must be nonzero) */
|
||||
para.nhm_app = NHM_DBG_11K; /* 802.11k noise-floor thresholds */
|
||||
|
||||
if (!(halbb_env_mntr_trigger(bb, ¶, &trig, HW_PHY_0) & NHM_SUCCESS))
|
||||
return 0;
|
||||
|
||||
/* The measurement runs mntr_time in HW; wait the window, then poll the ready
|
||||
* bit (halbb_env_mntr_result returns NHM_SUCCESS once nhm_rdy is set). */
|
||||
_os_delay_ms(drv, mtime);
|
||||
for (i = 0; i < 8; ++i) {
|
||||
_os_mem_set(0, &rpt, 0, sizeof(rpt));
|
||||
if ((halbb_env_mntr_result(bb, &rpt, HW_PHY_0) & NHM_SUCCESS) &&
|
||||
rpt.nhm_pwr != ENV_MNTR_FAIL_BYTE) {
|
||||
*nhm_pwr_dbm = (signed char)((int)rpt.nhm_pwr - 110); /* 110+x dBm */
|
||||
return 1;
|
||||
}
|
||||
_os_delay_ms(drv, 3);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
void kestrel_halbb_destroy(struct kestrel_halbb_ctx *ctx) {
|
||||
if (ctx)
|
||||
free(ctx);
|
||||
}
|
||||
@@ -0,0 +1,83 @@
|
||||
/* C/C++ boundary for the vendored halbb-G6 baseband plane (both Kestrel
|
||||
* chips).
|
||||
*
|
||||
* The vendored halbb C (compiled behind hal/halbb/hal_headers_le.h) owns the
|
||||
* full `struct bb_info` and the BB functions (gpio routing, RX-path enable,
|
||||
* per-band gain-error, per-channel BB config). This header exposes an OPAQUE
|
||||
* handle + a tiny API so devourer's C++ (RtlKestrelDevice/HalKestrel) can
|
||||
* drive them WITHOUT including any halbb header — the C++ side only sees
|
||||
* plain types + the register bridge. Chip dispatch is the vendor core's own
|
||||
* runtime ic_type switch; the glue only selects the ic_type at create and
|
||||
* forks the few entry points that have no generic dispatcher.
|
||||
*
|
||||
* Register/OS access is routed back to devourer through kestrel_halbb_bridge
|
||||
* (shim/halbb_bridge.h): the caller fills its callbacks (BB window read/write,
|
||||
* MAC pwr-reg read/write, delay, XTAL-SI) pointing at its RtlAdapter, then
|
||||
* hands it in.
|
||||
*/
|
||||
#ifndef KESTREL_HALBB_GLUE_H
|
||||
#define KESTREL_HALBB_GLUE_H
|
||||
|
||||
#include "shim/halbb_bridge.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
struct kestrel_halbb_ctx; /* opaque; owns a bb_info + hal_com/phl_com */
|
||||
|
||||
/* Allocate + populate a bb_info for `chip`, non-DBCC, HW_PHY_0, RX_PATH_AB.
|
||||
* `br` must outlive the ctx (its callbacks are stored; br->bb_info is set to
|
||||
* the live bb so the halrf plane's cross-plane calls resolve). `cut` = chip
|
||||
* cut version, `rfe_type` = efuse RFE type (drives the gpio/gain RFE branch). */
|
||||
struct kestrel_halbb_ctx *kestrel_halbb_create(struct kestrel_halbb_bridge *br,
|
||||
enum kestrel_chip chip,
|
||||
unsigned char cut,
|
||||
unsigned char rfe_type);
|
||||
void kestrel_halbb_destroy(struct kestrel_halbb_ctx *ctx);
|
||||
|
||||
/* Apply the built-in BB register table + gain table + efuse RX gain offsets
|
||||
* via the vendor's own loader flow (halbb_init_reg). Returns nonzero on
|
||||
* success. Run after the MAC's enable_bb_rf, before rx_bringup. */
|
||||
int kestrel_halbb_init_reg(struct kestrel_halbb_ctx *ctx);
|
||||
|
||||
/* One-shot RX bring-up: the LNAON/TRSW/PAPE RF-front-end gpio routing
|
||||
* (halbb_gpio_setting_init), then enable the RX chains (halbb_ctrl_rx_path).
|
||||
* The gain cache is loaded by kestrel_halbb_init_reg. */
|
||||
void kestrel_halbb_rx_bringup(struct kestrel_halbb_ctx *ctx);
|
||||
|
||||
/* Per-channel: apply the cached per-band LNA/TIA gain-error
|
||||
* (halbb_set_gain_error_<chip>). band_type: 0 = 2.4G (vendor skips
|
||||
* gain-error), 1 = 5G, 2 = 6G. */
|
||||
void kestrel_halbb_set_gain(struct kestrel_halbb_ctx *ctx, unsigned char central_ch,
|
||||
unsigned char band_type);
|
||||
|
||||
/* Full vendor per-channel BB config (halbb_ctrl_bw_ch -> per-chip backend):
|
||||
* gain-error, hidden/normal efuse RX gain, band mode-sel, SCO comp, BW/RXBB/
|
||||
* ADC, CCK en. bw is enum channel_width (20=0,40=1,80=2,160=3,5=6,10=7);
|
||||
* band_type 0=2.4G,1=5G,2=6G. */
|
||||
void kestrel_halbb_ctrl_bw_ch(struct kestrel_halbb_ctx *ctx, unsigned char pri_ch,
|
||||
unsigned char central_ch, unsigned char bw,
|
||||
unsigned char band_type);
|
||||
|
||||
/* T-MAC TX path-com routing (halbb_ctrl_tx_path_tmac_8852c): the 0xD800..
|
||||
* 0xD820 path-com block (per-cut, via the MAC pwr-reg plane) + the 0x9a4 path
|
||||
* enable + both-path TSSI reset. Connects the BB IFFT output to the TX chain.
|
||||
* 8852C-only — the 8852B selects its TX antenna per-STA via the CMAC antenna
|
||||
* model, so this is a no-op there. Single-PHY, RF_PATH_A. */
|
||||
void kestrel_halbb_ctrl_tx_path(struct kestrel_halbb_ctx *ctx);
|
||||
|
||||
/* One-shot active/frame-free NHM absolute noise floor. Runs a manual IEEE-11k
|
||||
* NHM measurement over `mntr_time_ms` (0 -> 100) and returns the
|
||||
* idle in-band power as signed dBm (nhm_pwr - 110). Frame-free, BB-driven, no
|
||||
* clock-stop -> no RX wedge. Lazily runs halbb_cr_cfg_env_mntr_init +
|
||||
* halbb_env_mntr_init on first call (the RX bring-up path does not). Returns 1
|
||||
* on a valid reading (fills *nhm_pwr_dbm), 0 on timeout/failure. */
|
||||
int kestrel_halbb_env_mntr_nhm(struct kestrel_halbb_ctx *ctx,
|
||||
unsigned short mntr_time_ms,
|
||||
signed char *nhm_pwr_dbm);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* KESTREL_HALBB_GLUE_H */
|
||||
@@ -0,0 +1,231 @@
|
||||
/* Disabled-path stubs for the vendored halbb-G6 8852C RX bring-up.
|
||||
*
|
||||
* With FW offload OFF (HALBB_FW_OFLD_SUPPORT=0, dev_cap.io_ofld=0) the register
|
||||
* writers reference three fwofld entry points that would otherwise drag the
|
||||
* whole cmd-offload/MAC surface in. check_fw_ofld returns false (so the direct
|
||||
* register path is always taken); fw_delay/fw_set_reg are never reached at
|
||||
* runtime. Providing them here avoids vendoring halbb_fwofld.c. Compiled as C
|
||||
* behind the shim, same as the vendored .c. */
|
||||
#include "halbb_precomp.h"
|
||||
|
||||
bool halbb_check_fw_ofld(struct bb_info *bb) { (void)bb; return false; }
|
||||
|
||||
bool halbb_fw_delay(struct bb_info *bb, u32 val) { (void)bb; (void)val; return false; }
|
||||
|
||||
bool halbb_fw_set_reg(struct bb_info *bb, u32 addr, u32 mask, u32 val, u8 lc) {
|
||||
(void)bb; (void)addr; (void)mask; (void)val; (void)lc; return false;
|
||||
}
|
||||
|
||||
bool halbb_fw_set_reg_cmn(struct bb_info *bb, u32 addr, u32 mask, u32 val,
|
||||
enum phl_phy_idx phy_idx, u8 lst_cmd) {
|
||||
(void)bb; (void)addr; (void)mask; (void)val; (void)phy_idx; (void)lst_cmd;
|
||||
return false;
|
||||
}
|
||||
|
||||
/* halbb_pmac_setting.c brackets set_tmac_tx/restore_info with this fwofld
|
||||
* batching toggle — with io_ofld off it only flips bb_cmn_hooker state the
|
||||
* direct register path never reads. */
|
||||
void halbb_fwofld_bitmap_en(struct bb_info *bb, bool en, enum fw_ofld_type app) {
|
||||
(void)bb; (void)en; (void)app;
|
||||
}
|
||||
|
||||
/* The halbb_ctrl_bw_ch dispatcher's 8852B case branches on
|
||||
* halbb_check_fw_ofld (false above), so this fwofld variant is never called —
|
||||
* the symbol just has to link (halbb_8852b_fwofld_api.c is not vendored). */
|
||||
bool halbb_fwofld_ctrl_bw_ch_8852b(struct bb_info *bb, u8 pri_ch, u8 central_ch,
|
||||
enum channel_width bw, enum band_type band,
|
||||
enum phl_phy_idx phy_idx) {
|
||||
(void)bb; (void)pri_ch; (void)central_ch; (void)bw; (void)band; (void)phy_idx;
|
||||
return false;
|
||||
}
|
||||
|
||||
/* DV/PXP (design-verification platform) debug print toggle (halbb_dv_dbg.c,
|
||||
* not vendored) — a log-gate only. */
|
||||
void halbb_dv_pxp_print_en(struct bb_info *bb, bool en) {
|
||||
(void)bb; (void)en;
|
||||
}
|
||||
|
||||
/* TPU / TSSI-ctrl MAC CR init (halbb_pwr_ctrl.c, not vendored) — the vendor's
|
||||
* TX-power-unit plane. Devourer's hand-ported fixed-dBm TXAGC owns the MAC
|
||||
* power CRs (set_txpwr_dbm, applied at every set_channel), so the vendor
|
||||
* init stays a no-op here; the pwr_ctrl TU would come in with a
|
||||
* TSSI-referenced power model. */
|
||||
void halbb_tpu_mac_cr_init(struct bb_info *bb, enum phl_phy_idx phy_idx) {
|
||||
(void)bb; (void)phy_idx;
|
||||
}
|
||||
void halbb_tssi_ctrl_mac_cr_init(struct bb_info *bb, enum phl_phy_idx phy_idx) {
|
||||
(void)bb; (void)phy_idx;
|
||||
}
|
||||
|
||||
/* fwofld variants behind halbb_check_fw_ofld (false above) — link-only. */
|
||||
bool halbb_fwcfg_bb_phy_8852b(struct bb_info *bb, u32 addr, u32 data,
|
||||
enum phl_phy_idx phy_idx) {
|
||||
(void)bb; (void)addr; (void)data; (void)phy_idx;
|
||||
return false;
|
||||
}
|
||||
void halbb_fwofld_set_gain_cr_init_8852c(struct bb_info *bb) { (void)bb; }
|
||||
|
||||
/* Spur suppression (halbb_spur_suppress.c, not vendored): channel-specific NBI
|
||||
* /CSI notch, not RX-hearing-critical — no-op (no spur notch). */
|
||||
void halbb_csi_tone_idx(struct bb_info *bb, u8 central_ch, enum channel_width bw,
|
||||
enum band_type band, enum phl_phy_idx phy_idx) {
|
||||
(void)bb; (void)central_ch; (void)bw; (void)band; (void)phy_idx;
|
||||
}
|
||||
void halbb_nbi_tone_idx(struct bb_info *bb, u8 central_ch, u8 pri_ch,
|
||||
enum channel_width bw, enum band_type band,
|
||||
enum rf_path path) {
|
||||
(void)bb; (void)central_ch; (void)pri_ch; (void)bw; (void)band; (void)path;
|
||||
}
|
||||
|
||||
/* ---- Link-only stubs for the un-vendored halbb subsystems ----------------
|
||||
*
|
||||
* The verbatim vendor TUs reference entry points that live in halbb .c files
|
||||
* we deliberately do NOT vendor. No runtime path reaches them (the callers
|
||||
* are un-driven vendor entry points kept verbatim), and GNU --gc-sections
|
||||
* dead-strips the references on Linux — but MSVC and MinGW ld resolve
|
||||
* archive members before dead-stripping, so the symbols must exist at link.
|
||||
* Signatures match the vendored header prototypes exactly (this TU includes
|
||||
* them via halbb_precomp.h). */
|
||||
|
||||
/* BB debug port (halbb_dbg.c, not vendored): register-window arbitration for
|
||||
* the vendor debug console + the fw dbg-print C2H decoder. */
|
||||
u32 halbb_get_bb_dbg_port_idx(struct bb_info *bb) { (void)bb; return 0; }
|
||||
void halbb_set_bb_dbg_port(struct bb_info *bb, u32 dbg_port) {
|
||||
(void)bb; (void)dbg_port;
|
||||
}
|
||||
void halbb_set_bb_dbg_port_ip(struct bb_info *bb, enum bb_dbg_port_ip_t ip) {
|
||||
(void)bb; (void)ip;
|
||||
}
|
||||
void halbb_release_bb_dbg_port(struct bb_info *bb) { (void)bb; }
|
||||
bool halbb_bb_dbg_port_racing(struct bb_info *bb, u8 curr_dbg_priority) {
|
||||
(void)bb; (void)curr_dbg_priority;
|
||||
return false; /* port not granted */
|
||||
}
|
||||
u32 halbb_get_bb_dbg_port_val(struct bb_info *bb) { (void)bb; return 0; }
|
||||
void halbb_cr_hook_fake_init(struct bb_info *bb, u32 *str_table, u32 len) {
|
||||
(void)bb; (void)str_table; (void)len;
|
||||
}
|
||||
void halbb_cr_hook_init_dump(struct bb_info *bb, u32 *str_table, u32 len) {
|
||||
(void)bb; (void)str_table; (void)len;
|
||||
}
|
||||
u32 halbb_c2h_fw_dbg(struct bb_info *bb, u16 len, u8 *c2h) {
|
||||
(void)bb; (void)len; (void)c2h;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* MP / mass-production counters (halbb_mp_ex.c, not vendored). */
|
||||
u32 halbb_mp_get_rx_crc_ok(struct bb_info *bb, enum phl_phy_idx phy_idx) {
|
||||
(void)bb; (void)phy_idx;
|
||||
return 0;
|
||||
}
|
||||
u32 halbb_mp_get_rx_crc_err(struct bb_info *bb, enum phl_phy_idx phy_idx) {
|
||||
(void)bb; (void)phy_idx;
|
||||
return 0;
|
||||
}
|
||||
void halbb_dbg_port_sel(struct bb_info *bb, u16 dbg_port_sel, u8 dbg_port_ip_sel,
|
||||
bool dbg_port_ref_clk_en, bool dbg_port_en) {
|
||||
(void)bb; (void)dbg_port_sel; (void)dbg_port_ip_sel;
|
||||
(void)dbg_port_ref_clk_en; (void)dbg_port_en;
|
||||
}
|
||||
|
||||
/* RA rate-adaptive reports (halbb_ra.c, not vendored): rate parsing helpers
|
||||
* + the fw RA-report / TX-history / TX-status C2H decoders. */
|
||||
bool halbb_is_cck_rate(struct bb_info *bb, u16 rate) {
|
||||
(void)bb; (void)rate;
|
||||
return false;
|
||||
}
|
||||
enum bb_mode_type halbb_get_rate_mode(struct bb_info *bb, u16 rate_idx) {
|
||||
(void)bb; (void)rate_idx;
|
||||
return BB_LEGACY_MODE;
|
||||
}
|
||||
void halbb_rate_idx_parsor(struct bb_info *bb, u16 rate_idx,
|
||||
enum rtw_gi_ltf gi_ltf, struct bb_rate_info *ra_i) {
|
||||
(void)bb; (void)rate_idx; (void)gi_ltf; (void)ra_i;
|
||||
}
|
||||
void halbb_print_rate_2_buff(struct bb_info *bb, u16 rate_idx,
|
||||
enum rtw_gi_ltf gi_ltf, char *buf, u16 buf_size) {
|
||||
(void)bb; (void)rate_idx; (void)gi_ltf;
|
||||
if (buf && buf_size)
|
||||
buf[0] = '\0';
|
||||
}
|
||||
u32 halbb_get_fw_ra_rpt(struct bb_info *bb, u16 len, u8 *c2h) {
|
||||
(void)bb; (void)len; (void)c2h;
|
||||
return 0;
|
||||
}
|
||||
void halbb_get_fw_c2h_tx_hist(struct bb_info *bb, u16 len, u8 *c2h) {
|
||||
(void)bb; (void)len; (void)c2h;
|
||||
}
|
||||
u32 halbb_get_fw_ra_dbgrpt_wifi7(struct bb_info *bb, u16 len, u8 *c2h) {
|
||||
(void)bb; (void)len; (void)c2h;
|
||||
return 0;
|
||||
}
|
||||
u32 halbb_get_txsts_rpt(struct bb_info *bb, u16 len, u8 *c2h) {
|
||||
(void)bb; (void)len; (void)c2h;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* FW statistics C2H (halbb_statistics.c fw half, not vendored). */
|
||||
u32 halbb_get_fw_c2h_statistics(struct bb_info *bb_0, u16 len, u8 *c2h) {
|
||||
(void)bb_0; (void)len; (void)c2h;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Common per-frame report plane (halbb_cmn_rpt.c, not vendored). */
|
||||
void halbb_cmn_rpt(struct bb_info *bb, struct physts_rxd *desc,
|
||||
u32 physts_bitmap) {
|
||||
(void)bb; (void)desc; (void)physts_bitmap;
|
||||
}
|
||||
u8 halbb_get_rssi_min(struct bb_info *bb) { (void)bb; return 0; }
|
||||
|
||||
/* Antenna / TX-path diversity (halbb_ant_div.c / halbb_path_div.c /
|
||||
* halbb_rua_tbl.c, not vendored). */
|
||||
void halbb_antdiv_phy_sts(struct bb_info *bb, u32 physts_bitmap,
|
||||
struct physts_rxd *desc) {
|
||||
(void)bb; (void)physts_bitmap; (void)desc;
|
||||
}
|
||||
void halbb_pathdiv_phy_sts(struct bb_info *bb, struct physts_rxd *desc) {
|
||||
(void)bb; (void)desc;
|
||||
}
|
||||
void halbb_set_tx_path(struct bb_info *bb, u16 macid,
|
||||
enum bb_path tx_path_sel_1ss) {
|
||||
(void)bb; (void)macid; (void)tx_path_sel_1ss;
|
||||
}
|
||||
u32 halbb_trxpath_notif(struct bb_info *bb, enum rf_path tx_path,
|
||||
enum rf_path rx_path) {
|
||||
(void)bb; (void)tx_path; (void)rx_path;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Dynamic 1R-CCA / DTR watchdog mechanisms (halbb_dyn_1r_cca.c /
|
||||
* halbb_dyn_dtr.c, not vendored). */
|
||||
void halbb_dyn_1r_cca(struct bb_info *bb) { (void)bb; }
|
||||
void halbb_dyn_1r_cca_rst(struct bb_info *bb) { (void)bb; }
|
||||
void halbb_dyn_dtr_watchdog(struct bb_info *bb) { (void)bb; }
|
||||
|
||||
/* Watchdog pause arbitration (halbb_init.c pause half, not vendored). */
|
||||
u8 halbb_pause_func(struct bb_info *bb, enum habb_fun_t pause_func,
|
||||
enum halbb_pause_type pause_type,
|
||||
enum halbb_pause_lv_type lv,
|
||||
u8 val_lehgth,
|
||||
u32 *val_buf, enum phl_phy_idx phy_idx) {
|
||||
(void)bb; (void)pause_func; (void)pause_type; (void)lv; (void)val_lehgth;
|
||||
(void)val_buf; (void)phy_idx;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* TSSI band-edge config (halbb_pwr_ctrl.c, not vendored — same subsystem as
|
||||
* the tpu/tssi cr-init no-ops above). */
|
||||
void halbb_tssi_ctrl_set_bandedge_cfg(struct bb_info *bb,
|
||||
enum phl_phy_idx phy_idx,
|
||||
enum tssi_bandedge_cfg bandedge_cfg) {
|
||||
(void)bb; (void)phy_idx; (void)bandedge_cfg;
|
||||
}
|
||||
|
||||
/* BE (11BE / WiFi7) primary-sub-band helper referenced by halbb_env_mntr.c's
|
||||
* EDCCA-opt path only in its 11BE branch - dead code on the AX Kestrel ICs
|
||||
* (halbb_api_be.c is not vendored). A link-only stub, never called at runtime. */
|
||||
u8 halbb_get_prim_sb(struct bb_info *bb, u8 central_ch, u8 pri_ch,
|
||||
enum channel_width bw) {
|
||||
(void)bb; (void)central_ch; (void)pri_ch; (void)bw;
|
||||
return 0;
|
||||
}
|
||||
@@ -0,0 +1,492 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2019 - 2023 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef _HAL_GENERAL_DEF_H_
|
||||
#define _HAL_GENERAL_DEF_H_
|
||||
|
||||
#define FL_COMP_VER BIT0
|
||||
#define FL_COMP_INIT BIT1
|
||||
#define FL_COMP_TASK BIT2
|
||||
#define FL_COMP_CNS BIT3
|
||||
#define FL_COMP_H2C BIT4
|
||||
#define FL_COMP_C2H BIT5
|
||||
#define FL_COMP_TX BIT6
|
||||
#define FL_COMP_RX BIT7
|
||||
#define FL_COMP_IPSEC BIT8
|
||||
#define FL_COMP_TIMER BIT9
|
||||
#define FL_COMP_DBGPKT BIT10
|
||||
#define FL_COMP_PS BIT11
|
||||
#define FL_COMP_BB BIT16
|
||||
#define FL_COMP_TWT BIT17
|
||||
#define FL_COMP_MCC BIT20
|
||||
#define FL_COMP_NAN BIT26
|
||||
#define FL_COMP_SCAN BIT28
|
||||
|
||||
#define RTW_MAC_TBTT_AGG_DEF 1
|
||||
|
||||
/* RXBUF should larger than RXBD, or it will cause RX RDU
|
||||
the minimum number of RXBUF - RXBD is 32 */
|
||||
#define RTW_RX_BUF_BD_MIN_DIFF 32
|
||||
|
||||
enum rtw_chip_id {
|
||||
CHIP_WIFI6_8852A,
|
||||
CHIP_WIFI6_8834A,
|
||||
CHIP_WIFI6_8852B,
|
||||
CHIP_WIFI6_8852C,
|
||||
CHIP_WIFI6_8852D,
|
||||
CHIP_WIFI6_8192XB,
|
||||
CHIP_WIFI6_8832BR,
|
||||
CHIP_WIFI6_8852BP,
|
||||
CHIP_WIFI7_8922A,
|
||||
CHIP_WIFI6_8851B,
|
||||
CHIP_WIFI6_8852BT,
|
||||
CHIP_WIFI6_8852BPT,
|
||||
CHIP_WIFI6_8842A,
|
||||
CHIP_WIFI6_MAX
|
||||
};
|
||||
|
||||
enum rtw_efuse_info {
|
||||
/* MAC Part */
|
||||
EFUSE_INFO_MAC_ADDR,
|
||||
EFUSE_INFO_MAC_PID,
|
||||
EFUSE_INFO_MAC_DID,
|
||||
EFUSE_INFO_MAC_VID,
|
||||
EFUSE_INFO_MAC_SVID,
|
||||
EFUSE_INFO_MAC_SMID,
|
||||
EFUSE_INFO_MAC_MAX,
|
||||
/* BB Part */
|
||||
EFUSE_INFO_BB_ANTDIV,
|
||||
EFUSE_INFO_BB_MAX,
|
||||
/* RF Part */
|
||||
EFUSE_INFO_RF_PKG_TYPE,
|
||||
EFUSE_INFO_RF_PA,
|
||||
EFUSE_INFO_RF_VALID_PATH,
|
||||
EFUSE_INFO_RF_RFE,
|
||||
EFUSE_INFO_RF_TXPWR,
|
||||
EFUSE_INFO_RF_BOARD_OPTION,
|
||||
EFUSE_INFO_RF_CHAN_PLAN,
|
||||
EFUSE_INFO_RF_CHAN_PLAN_6GHZ,
|
||||
EFUSE_INFO_RF_CHAN_PLAN_FORCE_HW,
|
||||
EFUSE_INFO_RF_COUNTRY,
|
||||
EFUSE_INFO_RF_THERMAL,
|
||||
EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_1,
|
||||
EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_2,
|
||||
EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_3,
|
||||
EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_4,
|
||||
EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_5,
|
||||
EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_6,
|
||||
EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_1,
|
||||
EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_2,
|
||||
EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_3,
|
||||
EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_4,
|
||||
EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_5,
|
||||
EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_1,
|
||||
EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_2,
|
||||
EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_3,
|
||||
EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_4,
|
||||
EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_5,
|
||||
EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_6,
|
||||
EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_7,
|
||||
EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_8,
|
||||
EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_9,
|
||||
EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_10,
|
||||
EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_11,
|
||||
EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_12,
|
||||
EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_13,
|
||||
EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_14,
|
||||
EFUSE_INFO_RF_5G_BW20M1S_BW40M1S_A_DIFF,
|
||||
EFUSE_INFO_RF_5G_OFDM1T_BW40M1S_A_DIFF,
|
||||
EFUSE_INFO_RF_5G_BW40M2S_BW40M1S_A_DIFF,
|
||||
EFUSE_INFO_RF_5G_BW20M2S_BW20M1S_A_DIFF,
|
||||
EFUSE_INFO_RF_5G_BW40M3S_BW40M2S_A_DIFF,
|
||||
EFUSE_INFO_RF_5G_BW20M3S_BW20M2S_A_DIFF,
|
||||
EFUSE_INFO_RF_5G_BW40M4S_BW40M3S_A_DIFF,
|
||||
EFUSE_INFO_RF_5G_BW20M4S_BW20M3S_A_DIFF,
|
||||
EFUSE_INFO_RF_5G_OFDM2T_OFDM1T_A_DIFF,
|
||||
EFUSE_INFO_RF_5G_OFDM3T_OFDM2T_A_DIFF,
|
||||
EFUSE_INFO_RF_5G_OFDM4T_OFDM3T_A_DIFF,
|
||||
EFUSE_INFO_RF_5G_BW80M1S_BW40M1S_A_DIFF,
|
||||
EFUSE_INFO_RF_5G_BW160M1S_BW80M1S_A_DIFF,
|
||||
EFUSE_INFO_RF_5G_BW80M2S_BW80M1S_A_DIFF,
|
||||
EFUSE_INFO_RF_5G_BW160M2S_BW160M1S_A_DIFF,
|
||||
EFUSE_INFO_RF_5G_BW80M3S_BW80M2S_A_DIFF,
|
||||
EFUSE_INFO_RF_5G_BW160M3S_BW160M2S_A_DIFF,
|
||||
EFUSE_INFO_RF_5G_BW80M4S_BW80M3S_A_DIFF,
|
||||
EFUSE_INFO_RF_5G_BW160M4S_BW160M3S_A_DIFF,
|
||||
EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_1,
|
||||
EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_2,
|
||||
EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_3,
|
||||
EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_4,
|
||||
EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_5,
|
||||
EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_6,
|
||||
EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_1,
|
||||
EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_2,
|
||||
EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_3,
|
||||
EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_4,
|
||||
EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_5,
|
||||
EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_1,
|
||||
EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_2,
|
||||
EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_3,
|
||||
EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_4,
|
||||
EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_5,
|
||||
EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_6,
|
||||
EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_7,
|
||||
EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_8,
|
||||
EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_9,
|
||||
EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_10,
|
||||
EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_11,
|
||||
EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_12,
|
||||
EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_13,
|
||||
EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_14,
|
||||
EFUSE_INFO_RF_5G_BW20M1S_BW40M1S_B_DIFF,
|
||||
EFUSE_INFO_RF_5G_OFDM1T_BW40M1S_B_DIFF,
|
||||
EFUSE_INFO_RF_5G_BW40M2S_BW40M1S_B_DIFF,
|
||||
EFUSE_INFO_RF_5G_BW20M2S_BW20M1S_B_DIFF,
|
||||
EFUSE_INFO_RF_5G_BW40M3S_BW40M2S_B_DIFF,
|
||||
EFUSE_INFO_RF_5G_BW20M3S_BW20M2S_B_DIFF,
|
||||
EFUSE_INFO_RF_5G_BW40M4S_BW40M3S_B_DIFF,
|
||||
EFUSE_INFO_RF_5G_BW20M4S_BW20M3S_B_DIFF,
|
||||
EFUSE_INFO_RF_5G_OFDM2T_OFDM1T_B_DIFF,
|
||||
EFUSE_INFO_RF_5G_OFDM3T_OFDM2T_B_DIFF,
|
||||
EFUSE_INFO_RF_5G_OFDM4T_OFDM3T_B_DIFF,
|
||||
EFUSE_INFO_RF_5G_BW80M1S_BW40M1S_B_DIFF,
|
||||
EFUSE_INFO_RF_5G_BW160M1S_BW80M1S_B_DIFF,
|
||||
EFUSE_INFO_RF_5G_BW80M2S_BW80M1S_B_DIFF,
|
||||
EFUSE_INFO_RF_5G_BW160M2S_BW160M1S_B_DIFF,
|
||||
EFUSE_INFO_RF_5G_BW80M3S_BW80M2S_B_DIFF,
|
||||
EFUSE_INFO_RF_5G_BW160M3S_BW160M2S_B_DIFF,
|
||||
EFUSE_INFO_RF_5G_BW80M4S_BW80M3S_B_DIFF,
|
||||
EFUSE_INFO_RF_5G_BW160M4S_BW160M3S_B_DIFF,
|
||||
EFUSE_INFO_RF_2G_CCK_C_TSSI_DE_1,
|
||||
EFUSE_INFO_RF_2G_CCK_C_TSSI_DE_2,
|
||||
EFUSE_INFO_RF_2G_CCK_C_TSSI_DE_3,
|
||||
EFUSE_INFO_RF_2G_CCK_C_TSSI_DE_4,
|
||||
EFUSE_INFO_RF_2G_CCK_C_TSSI_DE_5,
|
||||
EFUSE_INFO_RF_2G_CCK_C_TSSI_DE_6,
|
||||
EFUSE_INFO_RF_2G_BW40M_C_TSSI_DE_1,
|
||||
EFUSE_INFO_RF_2G_BW40M_C_TSSI_DE_2,
|
||||
EFUSE_INFO_RF_2G_BW40M_C_TSSI_DE_3,
|
||||
EFUSE_INFO_RF_2G_BW40M_C_TSSI_DE_4,
|
||||
EFUSE_INFO_RF_2G_BW40M_C_TSSI_DE_5,
|
||||
EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_1,
|
||||
EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_2,
|
||||
EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_3,
|
||||
EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_4,
|
||||
EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_5,
|
||||
EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_6,
|
||||
EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_7,
|
||||
EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_8,
|
||||
EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_9,
|
||||
EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_10,
|
||||
EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_11,
|
||||
EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_12,
|
||||
EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_13,
|
||||
EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_14,
|
||||
EFUSE_INFO_RF_5G_BW20M1S_BW40M1S_C_DIFF,
|
||||
EFUSE_INFO_RF_5G_OFDM1T_BW40M1S_C_DIFF,
|
||||
EFUSE_INFO_RF_5G_BW40M2S_BW40M1S_C_DIFF,
|
||||
EFUSE_INFO_RF_5G_BW20M2S_BW20M1S_C_DIFF,
|
||||
EFUSE_INFO_RF_5G_BW40M3S_BW40M2S_C_DIFF,
|
||||
EFUSE_INFO_RF_5G_BW20M3S_BW20M2S_C_DIFF,
|
||||
EFUSE_INFO_RF_5G_BW40M4S_BW40M3S_C_DIFF,
|
||||
EFUSE_INFO_RF_5G_BW20M4S_BW20M3S_C_DIFF,
|
||||
EFUSE_INFO_RF_5G_OFDM2T_OFDM1T_C_DIFF,
|
||||
EFUSE_INFO_RF_5G_OFDM3T_OFDM2T_C_DIFF,
|
||||
EFUSE_INFO_RF_5G_OFDM4T_OFDM3T_C_DIFF,
|
||||
EFUSE_INFO_RF_5G_BW80M1S_BW40M1S_C_DIFF,
|
||||
EFUSE_INFO_RF_5G_BW160M1S_BW80M1S_C_DIFF,
|
||||
EFUSE_INFO_RF_5G_BW80M2S_BW80M1S_C_DIFF,
|
||||
EFUSE_INFO_RF_5G_BW160M2S_BW160M1S_C_DIFF,
|
||||
EFUSE_INFO_RF_5G_BW80M3S_BW80M2S_C_DIFF,
|
||||
EFUSE_INFO_RF_5G_BW160M3S_BW160M2S_C_DIFF,
|
||||
EFUSE_INFO_RF_5G_BW80M4S_BW80M3S_C_DIFF,
|
||||
EFUSE_INFO_RF_5G_BW160M4S_BW160M3S_C_DIFF,
|
||||
EFUSE_INFO_RF_2G_CCK_D_TSSI_DE_1,
|
||||
EFUSE_INFO_RF_2G_CCK_D_TSSI_DE_2,
|
||||
EFUSE_INFO_RF_2G_CCK_D_TSSI_DE_3,
|
||||
EFUSE_INFO_RF_2G_CCK_D_TSSI_DE_4,
|
||||
EFUSE_INFO_RF_2G_CCK_D_TSSI_DE_5,
|
||||
EFUSE_INFO_RF_2G_CCK_D_TSSI_DE_6,
|
||||
EFUSE_INFO_RF_2G_BW40M_D_TSSI_DE_1,
|
||||
EFUSE_INFO_RF_2G_BW40M_D_TSSI_DE_2,
|
||||
EFUSE_INFO_RF_2G_BW40M_D_TSSI_DE_3,
|
||||
EFUSE_INFO_RF_2G_BW40M_D_TSSI_DE_4,
|
||||
EFUSE_INFO_RF_2G_BW40M_D_TSSI_DE_5,
|
||||
EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_1,
|
||||
EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_2,
|
||||
EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_3,
|
||||
EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_4,
|
||||
EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_5,
|
||||
EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_6,
|
||||
EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_7,
|
||||
EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_8,
|
||||
EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_9,
|
||||
EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_10,
|
||||
EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_11,
|
||||
EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_12,
|
||||
EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_13,
|
||||
EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_14,
|
||||
EFUSE_INFO_RF_5G_BW20M1S_BW40M1S_D_DIFF,
|
||||
EFUSE_INFO_RF_5G_OFDM1T_BW40M1S_D_DIFF,
|
||||
EFUSE_INFO_RF_5G_BW40M2S_BW40M1S_D_DIFF,
|
||||
EFUSE_INFO_RF_5G_BW20M2S_BW20M1S_D_DIFF,
|
||||
EFUSE_INFO_RF_5G_BW40M3S_BW40M2S_D_DIFF,
|
||||
EFUSE_INFO_RF_5G_BW20M3S_BW20M2S_D_DIFF,
|
||||
EFUSE_INFO_RF_5G_BW40M4S_BW40M3S_D_DIFF,
|
||||
EFUSE_INFO_RF_5G_BW20M4S_BW20M3S_D_DIFF,
|
||||
EFUSE_INFO_RF_5G_OFDM2T_OFDM1T_D_DIFF,
|
||||
EFUSE_INFO_RF_5G_OFDM3T_OFDM2T_D_DIFF,
|
||||
EFUSE_INFO_RF_5G_OFDM4T_OFDM3T_D_DIFF,
|
||||
EFUSE_INFO_RF_5G_BW80M1S_BW40M1S_D_DIFF,
|
||||
EFUSE_INFO_RF_5G_BW160M1S_BW80M1S_D_DIFF,
|
||||
EFUSE_INFO_RF_5G_BW80M2S_BW80M1S_D_DIFF,
|
||||
EFUSE_INFO_RF_5G_BW160M2S_BW160M1S_D_DIFF,
|
||||
EFUSE_INFO_RF_5G_BW80M3S_BW80M2S_D_DIFF,
|
||||
EFUSE_INFO_RF_5G_BW160M3S_BW160M2S_D_DIFF,
|
||||
EFUSE_INFO_RF_5G_BW80M4S_BW80M3S_D_DIFF,
|
||||
EFUSE_INFO_RF_5G_BW160M4S_BW160M3S_D_DIFF,
|
||||
EFUSE_INFO_RF_THERMAL_A,
|
||||
EFUSE_INFO_RF_THERMAL_B,
|
||||
EFUSE_INFO_RF_THERMAL_C,
|
||||
EFUSE_INFO_RF_THERMAL_D,
|
||||
EFUSE_INFO_RF_XTAL,
|
||||
EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_1,
|
||||
EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_2,
|
||||
EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_3,
|
||||
EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_4,
|
||||
EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_5,
|
||||
EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_6,
|
||||
EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_7,
|
||||
EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_8,
|
||||
EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_9,
|
||||
EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_10,
|
||||
EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_11,
|
||||
EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_12,
|
||||
EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_13,
|
||||
EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_14,
|
||||
EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_15,
|
||||
EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_16,
|
||||
EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_17,
|
||||
EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_18,
|
||||
EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_19,
|
||||
EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_20,
|
||||
EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_21,
|
||||
EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_22,
|
||||
EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_23,
|
||||
EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_24,
|
||||
EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_25,
|
||||
EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_26,
|
||||
EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_27,
|
||||
EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_28,
|
||||
EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_29,
|
||||
EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_30,
|
||||
EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_31,
|
||||
EFUSE_INFO_RF_6G_BW40M_A_TSSI_DE_32,
|
||||
EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_1,
|
||||
EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_2,
|
||||
EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_3,
|
||||
EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_4,
|
||||
EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_5,
|
||||
EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_6,
|
||||
EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_7,
|
||||
EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_8,
|
||||
EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_9,
|
||||
EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_10,
|
||||
EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_11,
|
||||
EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_12,
|
||||
EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_13,
|
||||
EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_14,
|
||||
EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_15,
|
||||
EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_16,
|
||||
EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_17,
|
||||
EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_18,
|
||||
EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_19,
|
||||
EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_20,
|
||||
EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_21,
|
||||
EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_22,
|
||||
EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_23,
|
||||
EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_24,
|
||||
EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_25,
|
||||
EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_26,
|
||||
EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_27,
|
||||
EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_28,
|
||||
EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_29,
|
||||
EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_30,
|
||||
EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_31,
|
||||
EFUSE_INFO_RF_6G_BW40M_B_TSSI_DE_32,
|
||||
EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_1,
|
||||
EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_2,
|
||||
EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_3,
|
||||
EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_4,
|
||||
EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_5,
|
||||
EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_6,
|
||||
EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_7,
|
||||
EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_8,
|
||||
EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_9,
|
||||
EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_10,
|
||||
EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_11,
|
||||
EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_12,
|
||||
EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_13,
|
||||
EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_14,
|
||||
EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_15,
|
||||
EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_16,
|
||||
EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_17,
|
||||
EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_18,
|
||||
EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_19,
|
||||
EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_20,
|
||||
EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_21,
|
||||
EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_22,
|
||||
EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_23,
|
||||
EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_24,
|
||||
EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_25,
|
||||
EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_26,
|
||||
EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_27,
|
||||
EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_28,
|
||||
EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_29,
|
||||
EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_30,
|
||||
EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_31,
|
||||
EFUSE_INFO_RF_6G_BW40M_C_TSSI_DE_32,
|
||||
EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_1,
|
||||
EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_2,
|
||||
EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_3,
|
||||
EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_4,
|
||||
EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_5,
|
||||
EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_6,
|
||||
EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_7,
|
||||
EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_8,
|
||||
EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_9,
|
||||
EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_10,
|
||||
EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_11,
|
||||
EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_12,
|
||||
EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_13,
|
||||
EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_14,
|
||||
EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_15,
|
||||
EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_16,
|
||||
EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_17,
|
||||
EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_18,
|
||||
EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_19,
|
||||
EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_20,
|
||||
EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_21,
|
||||
EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_22,
|
||||
EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_23,
|
||||
EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_24,
|
||||
EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_25,
|
||||
EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_26,
|
||||
EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_27,
|
||||
EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_28,
|
||||
EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_29,
|
||||
EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_30,
|
||||
EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_31,
|
||||
EFUSE_INFO_RF_6G_BW40M_D_TSSI_DE_32,
|
||||
/*RX Gain K*/
|
||||
EFUSE_INFO_RF_RX_GAIN_K_A_2G_CCK,
|
||||
EFUSE_INFO_RF_RX_GAIN_K_A_2G_OFMD,
|
||||
EFUSE_INFO_RF_RX_GAIN_K_A_5GL,
|
||||
EFUSE_INFO_RF_RX_GAIN_K_A_5GM,
|
||||
EFUSE_INFO_RF_RX_GAIN_K_A_5GH,
|
||||
EFUSE_INFO_RF_RX_GAIN_K_A_6GL1,
|
||||
EFUSE_INFO_RF_RX_GAIN_K_A_6GL2,
|
||||
EFUSE_INFO_RF_RX_GAIN_K_A_6GL3,
|
||||
EFUSE_INFO_RF_RX_GAIN_K_A_6GM1,
|
||||
EFUSE_INFO_RF_RX_GAIN_K_A_6GM2,
|
||||
EFUSE_INFO_RF_RX_GAIN_K_A_6GM3,
|
||||
EFUSE_INFO_RF_RX_GAIN_K_A_6GH1,
|
||||
EFUSE_INFO_RF_RX_GAIN_K_A_6GH2,
|
||||
/*RF BW Power Diff*/
|
||||
EFUSE_INFO_RF_5G_BW160M_BW40M_DIFF,
|
||||
EFUSE_INFO_RF_6G_BW160M_BW40M_DIFF,
|
||||
EFUSE_INFO_RF_6G_BW320M_BW160M_DIFF,
|
||||
EFUSE_INFO_RF_MAX,
|
||||
/* BTCOEX Part */
|
||||
EFUSE_INFO_BTCOEX_COEX,
|
||||
EFUSE_INFO_BTCOEX_ANT_NUM,
|
||||
EFUSE_INFO_BTCOEX_ANT_PATH,
|
||||
EFUSE_INFO_BTCOEX_MAX,
|
||||
};
|
||||
|
||||
enum rtw_cv {
|
||||
CAV,
|
||||
CBV,
|
||||
CCV,
|
||||
CDV,
|
||||
CEV,
|
||||
CFV,
|
||||
CGV,
|
||||
CTV,
|
||||
CV_MAX,
|
||||
};
|
||||
|
||||
enum rtw_fv {
|
||||
FTV,
|
||||
FUV,
|
||||
FSV,
|
||||
FGV,
|
||||
FV_MAX
|
||||
};
|
||||
|
||||
enum rtw_dv_sel {
|
||||
DAV,
|
||||
DDV,
|
||||
};
|
||||
|
||||
enum hal_pwr_by_rate_setting {
|
||||
PW_BY_RATE_ON = 0,
|
||||
PW_BY_RATE_ALL_SAME = 1
|
||||
};
|
||||
|
||||
enum hal_pwr_limit_type {
|
||||
PWLMT_BY_EFUSE = 0,
|
||||
PWLMT_DISABLE = 1,
|
||||
PWBYRATE_AND_PWLMT = 2
|
||||
};
|
||||
|
||||
enum wl_func {
|
||||
EFUSE_WL_FUNC_NONE = 0,
|
||||
EFUSE_WL_FUNC_DRAGON = 0xe,
|
||||
EFUSE_WL_FUNC_GENERAL = 0xf
|
||||
};
|
||||
enum hw_stype{
|
||||
EFUSE_HW_STYPE_NONE = 0x0,
|
||||
EFUSE_HW_STYPE_GENERAL = 0xf
|
||||
};
|
||||
|
||||
enum n_bb_path {
|
||||
BB_0PATH = 0,
|
||||
BB_1PATH = 1,
|
||||
BB_2PATH = 2,
|
||||
BB_3PATH = 3,
|
||||
};
|
||||
|
||||
enum n_rf_entity {
|
||||
RF_1ENTITY = 1,
|
||||
RF_2ENTITY = 2
|
||||
};
|
||||
|
||||
#define BB0_N_PATH_SFT 0
|
||||
#define BB1_N_PATH_SFT 4
|
||||
#define RF_N_ENTITY_SFT 12
|
||||
enum mlo_dbcc_mode_type { /* for HALBB/HALRF reference */
|
||||
MLO_DBCC_NOT_SUPPORT = 0,
|
||||
MLO_0_PLUS_2_1RF = (RF_1ENTITY << RF_N_ENTITY_SFT | BB_2PATH << BB1_N_PATH_SFT | BB_0PATH),
|
||||
MLO_0_PLUS_2_2RF = (RF_2ENTITY << RF_N_ENTITY_SFT | BB_2PATH << BB1_N_PATH_SFT | BB_0PATH),
|
||||
MLO_1_PLUS_1_1RF = (RF_1ENTITY << RF_N_ENTITY_SFT | BB_1PATH << BB1_N_PATH_SFT | BB_1PATH),
|
||||
MLO_1_PLUS_1_2RF = (RF_2ENTITY << RF_N_ENTITY_SFT | BB_1PATH << BB1_N_PATH_SFT | BB_1PATH),
|
||||
MLO_2_PLUS_0_1RF = (RF_1ENTITY << RF_N_ENTITY_SFT | BB_0PATH << BB1_N_PATH_SFT | BB_2PATH),
|
||||
MLO_2_PLUS_0_2RF = (RF_2ENTITY << RF_N_ENTITY_SFT | BB_0PATH << BB1_N_PATH_SFT | BB_2PATH),
|
||||
MLO_2_PLUS_2_2RF = (RF_2ENTITY << RF_N_ENTITY_SFT | BB_2PATH << BB1_N_PATH_SFT | BB_2PATH),
|
||||
DBCC_LEGACY = 0xffffffff /* ex:8852C DBCC (2PHY in 1BB) x 1 */
|
||||
};
|
||||
|
||||
#endif /* _HAL_GENERAL_DEF_H_*/
|
||||
|
||||
@@ -0,0 +1,68 @@
|
||||
/* halbb-G6 shim bridge — the register/OS plane the vendored halbb/halrf C
|
||||
* bottoms out in, routed to devourer's RtlAdapter. C ABI, shared by the shim'd
|
||||
* vendor C and devourer's C++ (RtlKestrelDevice owns the bridge instance and
|
||||
* installs the callbacks). See hal/halbb/g6/shim/ and tools/vendor_halbb_*.sh.
|
||||
*
|
||||
* The vendor code calls hal_write32(bb->hal_com, addr, val) etc.; hal_com's
|
||||
* drv_priv points at a kestrel_halbb_bridge whose fn pointers reach the device.
|
||||
*/
|
||||
#ifndef KESTREL_HALBB_BRIDGE_H
|
||||
#define KESTREL_HALBB_BRIDGE_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Which Kestrel chip the glue drives — selects ic_type/chip_id for the
|
||||
* vendored cores' own runtime dispatch. */
|
||||
enum kestrel_chip {
|
||||
KESTREL_CHIP_8852B = 0,
|
||||
KESTREL_CHIP_8852C = 1,
|
||||
};
|
||||
|
||||
/* Opaque device cookie (a devourer RtlKestrelDevice* on the C++ side). */
|
||||
struct kestrel_halbb_bridge {
|
||||
void *dev; /* passed back to every callback */
|
||||
unsigned int (*read32)(void *dev, unsigned int addr);
|
||||
void (*write32)(void *dev, unsigned int addr, unsigned int val);
|
||||
/* MAC power-register plane (rtw_hal_mac_*_pwr_reg): field/shift write. */
|
||||
unsigned int (*read_pwr)(void *dev, unsigned int addr);
|
||||
void (*write_pwr)(void *dev, unsigned int addr, unsigned int val);
|
||||
/* RF-register plane (rtw_hal_*_rf_reg): 3-wire LSSI, masked field read/write
|
||||
* per RF path. May be NULL when only the BB plane is used (halbb). */
|
||||
unsigned int (*read_rf)(void *dev, unsigned int path, unsigned int addr,
|
||||
unsigned int mask);
|
||||
void (*write_rf)(void *dev, unsigned int path, unsigned int addr,
|
||||
unsigned int mask, unsigned int val);
|
||||
void (*delay_us)(void *dev, unsigned int us);
|
||||
/* Logical-efuse field read: devourer parses `id` (enum rtw_efuse_info) out of
|
||||
* its efuse shadow via the vendored 8852c map, writes `size` bytes to value.
|
||||
* Returns nonzero on success. NULL on halbb-only / no-efuse builds. */
|
||||
int (*efuse_get_info)(void *dev, unsigned int id, void *value,
|
||||
unsigned int size);
|
||||
/* diagnostic sink (BB_DBG/BB_WARNING) — may be NULL for no-op. */
|
||||
void (*logline)(void *dev, const char *msg);
|
||||
/* XTAL-SI plane (rtw_hal_mac_get/set_xsi): the 8852B's a-die SI reset
|
||||
* (halrf_arfc_si_reset_8852b, on the halrf_dm_init RFK prologue) needs it.
|
||||
* NULL-able: the shim falls back to a no-op (fine for the 8852C paths). */
|
||||
unsigned char (*read_xsi)(void *dev, unsigned char offset);
|
||||
void (*write_xsi)(void *dev, unsigned char offset, unsigned char val);
|
||||
/* fwcmd H2C plane (rtw_hal_mac_send_h2c): `data` = content dwords,
|
||||
* `len_bytes` = content length. The C++ side forwards ONLY the OUTSRC
|
||||
* radio-page classes (8 = radio A, 9 = radio B, func = page#) into its
|
||||
* mac_ax H2C encoder — every other halrf H2C stays inert, matching the
|
||||
* validated bring-up. Returns 0 on success (and for ignored classes).
|
||||
* NULL-able: the shim then reports success without sending. */
|
||||
int (*send_h2c)(void *dev, unsigned char h2c_class, unsigned char h2c_func,
|
||||
const unsigned int *data, unsigned short len_bytes);
|
||||
/* The live struct bb_info* (set by kestrel_halbb_create). The shim's
|
||||
* halrf->halbb cross-plane calls (rtw_hal_bb_backup_info / restore /
|
||||
* tx_mode_switch — hal_api_bb.c in the vendor) resolve the bb instance
|
||||
* through here, since the halrf ctx owns a different rtw_hal_com_t. */
|
||||
void *bb_info;
|
||||
};
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* KESTREL_HALBB_BRIDGE_H */
|
||||
@@ -0,0 +1,683 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2019 - 2023 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef _RTW_GENERAL_DEF_H_
|
||||
#define _RTW_GENERAL_DEF_H_
|
||||
|
||||
#define SEC_CAP_CHK_BMC BIT0
|
||||
|
||||
#define BIT0 0x00000001
|
||||
#define BIT1 0x00000002
|
||||
#define BIT2 0x00000004
|
||||
#define BIT3 0x00000008
|
||||
#define BIT4 0x00000010
|
||||
#define BIT5 0x00000020
|
||||
#define BIT6 0x00000040
|
||||
#define BIT7 0x00000080
|
||||
#define BIT8 0x00000100
|
||||
#define BIT9 0x00000200
|
||||
#define BIT10 0x00000400
|
||||
#define BIT11 0x00000800
|
||||
#define BIT12 0x00001000
|
||||
#define BIT13 0x00002000
|
||||
#define BIT14 0x00004000
|
||||
#define BIT15 0x00008000
|
||||
#define BIT16 0x00010000
|
||||
#define BIT17 0x00020000
|
||||
#define BIT18 0x00040000
|
||||
#define BIT19 0x00080000
|
||||
#define BIT20 0x00100000
|
||||
#define BIT21 0x00200000
|
||||
#define BIT22 0x00400000
|
||||
#define BIT23 0x00800000
|
||||
#define BIT24 0x01000000
|
||||
#define BIT25 0x02000000
|
||||
#define BIT26 0x04000000
|
||||
#define BIT27 0x08000000
|
||||
#define BIT28 0x10000000
|
||||
#define BIT29 0x20000000
|
||||
#define BIT30 0x40000000
|
||||
#define BIT31 0x80000000
|
||||
|
||||
#define RTW_U32_MAX 0xFFFFFFFF
|
||||
|
||||
enum rtl_ic_id {
|
||||
RTL8852A,
|
||||
RTL8834A,
|
||||
RTL8852B,
|
||||
RTL8852C,
|
||||
RTL8842A,
|
||||
RTL8852D,
|
||||
RTL8192XB,
|
||||
RTL8832BR,
|
||||
RTL8852BP,
|
||||
RTL8851B,
|
||||
RTL8852BT,
|
||||
RTL8852BPT,
|
||||
MAX_IC_ID
|
||||
};
|
||||
|
||||
/* BIT definition for combination */
|
||||
enum rtw_hci_type {
|
||||
RTW_HCI_PCIE = BIT0,
|
||||
RTW_HCI_USB = BIT1,
|
||||
RTW_HCI_SDIO = BIT2,
|
||||
RTW_HCI_GSPI = BIT3,
|
||||
RTW_HCI_MAX,
|
||||
};
|
||||
|
||||
enum rtw_pcie_gen {
|
||||
RTW_PCIE_GEN_UNKNOWN,
|
||||
RTW_PCIE_GEN_1 = 1,
|
||||
RTW_PCIE_GEN_2 = 2,
|
||||
RTW_PCIE_GEN_MAX
|
||||
};
|
||||
|
||||
#define SM_PS_STATIC 0
|
||||
#define SM_PS_DYNAMIC 1
|
||||
#define SM_PS_INVALID 2
|
||||
#define SM_PS_DISABLE 3
|
||||
|
||||
#define MAC_ADDRESS_LENGTH 6
|
||||
#define IPV4_ADDRESS_LENGTH 4
|
||||
#define IPV6_ADDRESS_LENGTH 16
|
||||
|
||||
/* Core shall translate system condition into device state for PHL controller */
|
||||
enum rtw_dev_state {
|
||||
RTW_DEV_WORKING = BIT0,
|
||||
RTW_DEV_SUSPENDING = BIT1,
|
||||
RTW_DEV_RESUMING = BIT2,
|
||||
RTW_DEV_SURPRISE_REMOVAL = BIT3,
|
||||
RTW_DEV_IN_DFS_CAC_PERIOD = BIT4,
|
||||
RTW_DEV_SHUTTING_DOWN = BIT5, /* set by core */
|
||||
RTW_DEV_SUSPENDED = BIT6,
|
||||
RTW_DEV_MAX
|
||||
};
|
||||
|
||||
#define RTW_RATE_MODE_MASK (BIT(7) | BIT(8))
|
||||
#define RTW_RATE_MODE_SHIFT 7
|
||||
#define RTW_RATE_INDEX_MASK 0x007f
|
||||
|
||||
#define RTW_GET_RATE_MODE(_rtw_data_rate) (u16)((_rtw_data_rate & RTW_RATE_MODE_MASK) >> RTW_RATE_MODE_SHIFT)
|
||||
#define RTW_GET_RATE_INDEX(_rtw_data_rate) (u16)(_rtw_data_rate & RTW_RATE_INDEX_MASK)
|
||||
|
||||
enum rtw_rate_mode {
|
||||
RTW_LEGACY_MODE = 0,
|
||||
RTW_HT_MODE = 1,
|
||||
RTW_VHT_MODE = 2,
|
||||
RTW_HE_MODE = 3
|
||||
};
|
||||
|
||||
enum rtw_data_rate {
|
||||
RTW_DATA_RATE_CCK1 = 0x0,
|
||||
RTW_DATA_RATE_CCK2 = 0x1,
|
||||
RTW_DATA_RATE_CCK5_5 = 0x2,
|
||||
RTW_DATA_RATE_CCK11 = 0x3,
|
||||
RTW_DATA_RATE_OFDM6 = 0x4,
|
||||
RTW_DATA_RATE_OFDM9 = 0x5,
|
||||
RTW_DATA_RATE_OFDM12 = 0x6,
|
||||
RTW_DATA_RATE_OFDM18 = 0x7,
|
||||
RTW_DATA_RATE_OFDM24 = 0x8,
|
||||
RTW_DATA_RATE_OFDM36 = 0x9,
|
||||
RTW_DATA_RATE_OFDM48 = 0xA,
|
||||
RTW_DATA_RATE_OFDM54 = 0xB,
|
||||
RTW_DATA_RATE_MCS0 = 0x80,
|
||||
RTW_DATA_RATE_MCS1 = 0x81,
|
||||
RTW_DATA_RATE_MCS2 = 0x82,
|
||||
RTW_DATA_RATE_MCS3 = 0x83,
|
||||
RTW_DATA_RATE_MCS4 = 0x84,
|
||||
RTW_DATA_RATE_MCS5 = 0x85,
|
||||
RTW_DATA_RATE_MCS6 = 0x86,
|
||||
RTW_DATA_RATE_MCS7 = 0x87,
|
||||
RTW_DATA_RATE_MCS8 = 0x88,
|
||||
RTW_DATA_RATE_MCS9 = 0x89,
|
||||
RTW_DATA_RATE_MCS10 = 0x8A,
|
||||
RTW_DATA_RATE_MCS11 = 0x8B,
|
||||
RTW_DATA_RATE_MCS12 = 0x8C,
|
||||
RTW_DATA_RATE_MCS13 = 0x8D,
|
||||
RTW_DATA_RATE_MCS14 = 0x8E,
|
||||
RTW_DATA_RATE_MCS15 = 0x8F,
|
||||
RTW_DATA_RATE_MCS16 = 0x90,
|
||||
RTW_DATA_RATE_MCS17 = 0x91,
|
||||
RTW_DATA_RATE_MCS18 = 0x92,
|
||||
RTW_DATA_RATE_MCS19 = 0x93,
|
||||
RTW_DATA_RATE_MCS20 = 0x94,
|
||||
RTW_DATA_RATE_MCS21 = 0x95,
|
||||
RTW_DATA_RATE_MCS22 = 0x96,
|
||||
RTW_DATA_RATE_MCS23 = 0x97,
|
||||
RTW_DATA_RATE_MCS24 = 0x98,
|
||||
RTW_DATA_RATE_MCS25 = 0x99,
|
||||
RTW_DATA_RATE_MCS26 = 0x9A,
|
||||
RTW_DATA_RATE_MCS27 = 0x9B,
|
||||
RTW_DATA_RATE_MCS28 = 0x9C,
|
||||
RTW_DATA_RATE_MCS29 = 0x9D,
|
||||
RTW_DATA_RATE_MCS30 = 0x9E,
|
||||
RTW_DATA_RATE_MCS31 = 0x9F,
|
||||
RTW_DATA_RATE_VHT_NSS1_MCS0 = 0x100,
|
||||
RTW_DATA_RATE_VHT_NSS1_MCS1 = 0x101,
|
||||
RTW_DATA_RATE_VHT_NSS1_MCS2 = 0x102,
|
||||
RTW_DATA_RATE_VHT_NSS1_MCS3 = 0x103,
|
||||
RTW_DATA_RATE_VHT_NSS1_MCS4 = 0x104,
|
||||
RTW_DATA_RATE_VHT_NSS1_MCS5 = 0x105,
|
||||
RTW_DATA_RATE_VHT_NSS1_MCS6 = 0x106,
|
||||
RTW_DATA_RATE_VHT_NSS1_MCS7 = 0x107,
|
||||
RTW_DATA_RATE_VHT_NSS1_MCS8 = 0x108,
|
||||
RTW_DATA_RATE_VHT_NSS1_MCS9 = 0x109,
|
||||
RTW_DATA_RATE_VHT_NSS2_MCS0 = 0x110,
|
||||
RTW_DATA_RATE_VHT_NSS2_MCS1 = 0x111,
|
||||
RTW_DATA_RATE_VHT_NSS2_MCS2 = 0x112,
|
||||
RTW_DATA_RATE_VHT_NSS2_MCS3 = 0x113,
|
||||
RTW_DATA_RATE_VHT_NSS2_MCS4 = 0x114,
|
||||
RTW_DATA_RATE_VHT_NSS2_MCS5 = 0x115,
|
||||
RTW_DATA_RATE_VHT_NSS2_MCS6 = 0x116,
|
||||
RTW_DATA_RATE_VHT_NSS2_MCS7 = 0x117,
|
||||
RTW_DATA_RATE_VHT_NSS2_MCS8 = 0x118,
|
||||
RTW_DATA_RATE_VHT_NSS2_MCS9 = 0x119,
|
||||
RTW_DATA_RATE_VHT_NSS3_MCS0 = 0x120,
|
||||
RTW_DATA_RATE_VHT_NSS3_MCS1 = 0x121,
|
||||
RTW_DATA_RATE_VHT_NSS3_MCS2 = 0x122,
|
||||
RTW_DATA_RATE_VHT_NSS3_MCS3 = 0x123,
|
||||
RTW_DATA_RATE_VHT_NSS3_MCS4 = 0x124,
|
||||
RTW_DATA_RATE_VHT_NSS3_MCS5 = 0x125,
|
||||
RTW_DATA_RATE_VHT_NSS3_MCS6 = 0x126,
|
||||
RTW_DATA_RATE_VHT_NSS3_MCS7 = 0x127,
|
||||
RTW_DATA_RATE_VHT_NSS3_MCS8 = 0x128,
|
||||
RTW_DATA_RATE_VHT_NSS3_MCS9 = 0x129,
|
||||
RTW_DATA_RATE_VHT_NSS4_MCS0 = 0x130,
|
||||
RTW_DATA_RATE_VHT_NSS4_MCS1 = 0x131,
|
||||
RTW_DATA_RATE_VHT_NSS4_MCS2 = 0x132,
|
||||
RTW_DATA_RATE_VHT_NSS4_MCS3 = 0x133,
|
||||
RTW_DATA_RATE_VHT_NSS4_MCS4 = 0x134,
|
||||
RTW_DATA_RATE_VHT_NSS4_MCS5 = 0x135,
|
||||
RTW_DATA_RATE_VHT_NSS4_MCS6 = 0x136,
|
||||
RTW_DATA_RATE_VHT_NSS4_MCS7 = 0x137,
|
||||
RTW_DATA_RATE_VHT_NSS4_MCS8 = 0x138,
|
||||
RTW_DATA_RATE_VHT_NSS4_MCS9 = 0x139,
|
||||
RTW_DATA_RATE_HE_NSS1_MCS0 = 0x180,
|
||||
RTW_DATA_RATE_HE_NSS1_MCS1 = 0x181,
|
||||
RTW_DATA_RATE_HE_NSS1_MCS2 = 0x182,
|
||||
RTW_DATA_RATE_HE_NSS1_MCS3 = 0x183,
|
||||
RTW_DATA_RATE_HE_NSS1_MCS4 = 0x184,
|
||||
RTW_DATA_RATE_HE_NSS1_MCS5 = 0x185,
|
||||
RTW_DATA_RATE_HE_NSS1_MCS6 = 0x186,
|
||||
RTW_DATA_RATE_HE_NSS1_MCS7 = 0x187,
|
||||
RTW_DATA_RATE_HE_NSS1_MCS8 = 0x188,
|
||||
RTW_DATA_RATE_HE_NSS1_MCS9 = 0x189,
|
||||
RTW_DATA_RATE_HE_NSS1_MCS10 = 0x18A,
|
||||
RTW_DATA_RATE_HE_NSS1_MCS11 = 0x18B,
|
||||
RTW_DATA_RATE_HE_NSS2_MCS0 = 0x190,
|
||||
RTW_DATA_RATE_HE_NSS2_MCS1 = 0x191,
|
||||
RTW_DATA_RATE_HE_NSS2_MCS2 = 0x192,
|
||||
RTW_DATA_RATE_HE_NSS2_MCS3 = 0x193,
|
||||
RTW_DATA_RATE_HE_NSS2_MCS4 = 0x194,
|
||||
RTW_DATA_RATE_HE_NSS2_MCS5 = 0x195,
|
||||
RTW_DATA_RATE_HE_NSS2_MCS6 = 0x196,
|
||||
RTW_DATA_RATE_HE_NSS2_MCS7 = 0x197,
|
||||
RTW_DATA_RATE_HE_NSS2_MCS8 = 0x198,
|
||||
RTW_DATA_RATE_HE_NSS2_MCS9 = 0x199,
|
||||
RTW_DATA_RATE_HE_NSS2_MCS10 = 0x19A,
|
||||
RTW_DATA_RATE_HE_NSS2_MCS11 = 0x19B,
|
||||
RTW_DATA_RATE_HE_NSS3_MCS0 = 0x1A0,
|
||||
RTW_DATA_RATE_HE_NSS3_MCS1 = 0x1A1,
|
||||
RTW_DATA_RATE_HE_NSS3_MCS2 = 0x1A2,
|
||||
RTW_DATA_RATE_HE_NSS3_MCS3 = 0x1A3,
|
||||
RTW_DATA_RATE_HE_NSS3_MCS4 = 0x1A4,
|
||||
RTW_DATA_RATE_HE_NSS3_MCS5 = 0x1A5,
|
||||
RTW_DATA_RATE_HE_NSS3_MCS6 = 0x1A6,
|
||||
RTW_DATA_RATE_HE_NSS3_MCS7 = 0x1A7,
|
||||
RTW_DATA_RATE_HE_NSS3_MCS8 = 0x1A8,
|
||||
RTW_DATA_RATE_HE_NSS3_MCS9 = 0x1A9,
|
||||
RTW_DATA_RATE_HE_NSS3_MCS10 = 0x1AA,
|
||||
RTW_DATA_RATE_HE_NSS3_MCS11 = 0x1AB,
|
||||
RTW_DATA_RATE_HE_NSS4_MCS0 = 0x1B0,
|
||||
RTW_DATA_RATE_HE_NSS4_MCS1 = 0x1B1,
|
||||
RTW_DATA_RATE_HE_NSS4_MCS2 = 0x1B2,
|
||||
RTW_DATA_RATE_HE_NSS4_MCS3 = 0x1B3,
|
||||
RTW_DATA_RATE_HE_NSS4_MCS4 = 0x1B4,
|
||||
RTW_DATA_RATE_HE_NSS4_MCS5 = 0x1B5,
|
||||
RTW_DATA_RATE_HE_NSS4_MCS6 = 0x1B6,
|
||||
RTW_DATA_RATE_HE_NSS4_MCS7 = 0x1B7,
|
||||
RTW_DATA_RATE_HE_NSS4_MCS8 = 0x1B8,
|
||||
RTW_DATA_RATE_HE_NSS4_MCS9 = 0x1B9,
|
||||
RTW_DATA_RATE_HE_NSS4_MCS10 = 0x1BA,
|
||||
RTW_DATA_RATE_HE_NSS4_MCS11 = 0x1BB,
|
||||
RTW_DATA_RATE_MAX = 0x1FF
|
||||
};
|
||||
|
||||
enum rtw_gi_ltf {
|
||||
RTW_GILTF_LGI_4XHE32 = 0,
|
||||
RTW_GILTF_SGI_4XHE08 = 1,
|
||||
RTW_GILTF_2XHE16 = 2,
|
||||
RTW_GILTF_2XHE08 = 3,
|
||||
RTW_GILTF_1XHE16 = 4,
|
||||
RTW_GILTF_1XHE08 = 5,
|
||||
RTW_GILTF_MAX
|
||||
};
|
||||
|
||||
|
||||
/* 11ax spec define for HE Trigger Frame, only used for HE Trigger Frame! */
|
||||
enum rtw_gi_ltf_ul_tb {
|
||||
RTW_TB_GILTF_1XHE16 = 0,
|
||||
RTW_TB_GILTF_2XHE16 = 1,
|
||||
RTW_TB_GILTF_4XHE32 = 2,
|
||||
RTW_TB_GILTF_MAX
|
||||
};
|
||||
|
||||
#define RTW_PHL_MAX_RF_PATH 4
|
||||
enum rf_path {
|
||||
RF_PATH_A = 0,
|
||||
RF_PATH_B = 1,
|
||||
RF_PATH_C = 2,
|
||||
RF_PATH_D = 3,
|
||||
RF_PATH_AB,
|
||||
RF_PATH_AC,
|
||||
RF_PATH_AD,
|
||||
RF_PATH_BC,
|
||||
RF_PATH_BD,
|
||||
RF_PATH_CD,
|
||||
RF_PATH_ABC,
|
||||
RF_PATH_ABD,
|
||||
RF_PATH_ACD,
|
||||
RF_PATH_BCD,
|
||||
RF_PATH_ABCD,
|
||||
};
|
||||
|
||||
/*HW SPEC & SW/HW CAP*/
|
||||
#define PROTO_CAP_11B BIT0
|
||||
#define PROTO_CAP_11G BIT1
|
||||
#define PROTO_CAP_11N BIT2
|
||||
#define PROTO_CAP_11AC BIT3
|
||||
#define PROTO_CAP_11AX BIT4
|
||||
#define PROTO_CAP_BIT_NUM 4
|
||||
|
||||
enum wlan_mode {
|
||||
WLAN_MD_INVALID = 0,
|
||||
WLAN_MD_11B = BIT0,
|
||||
WLAN_MD_11A = BIT1,
|
||||
WLAN_MD_11G = BIT2,
|
||||
WLAN_MD_11N = BIT3,
|
||||
WLAN_MD_11AC = BIT4,
|
||||
WLAN_MD_11AX = BIT5,
|
||||
WLAN_MD_11BE = BIT6,
|
||||
|
||||
/* Type for current wireless mode */
|
||||
WLAN_MD_11BG = (WLAN_MD_11B | WLAN_MD_11G),
|
||||
WLAN_MD_11GN = (WLAN_MD_11G | WLAN_MD_11N),
|
||||
WLAN_MD_11AN = (WLAN_MD_11A | WLAN_MD_11N),
|
||||
WLAN_MD_11BN = (WLAN_MD_11B | WLAN_MD_11N),
|
||||
WLAN_MD_11BGN = (WLAN_MD_11B | WLAN_MD_11G | WLAN_MD_11N),
|
||||
WLAN_MD_11BGAC = (WLAN_MD_11B | WLAN_MD_11G | WLAN_MD_11AC),
|
||||
WLAN_MD_11BGAX = (WLAN_MD_11B | WLAN_MD_11G | WLAN_MD_11AX),
|
||||
WLAN_MD_11GAC = (WLAN_MD_11G | WLAN_MD_11AC),
|
||||
WLAN_MD_11GAX = (WLAN_MD_11G | WLAN_MD_11AX),
|
||||
WLAN_MD_11A_AC = (WLAN_MD_11A | WLAN_MD_11AC),
|
||||
WLAN_MD_11A_AX = (WLAN_MD_11A | WLAN_MD_11AX),
|
||||
|
||||
/* Capability -Type for registry default wireless mode */
|
||||
WLAN_MD_11AGN = (WLAN_MD_11A | WLAN_MD_11G | WLAN_MD_11N ),
|
||||
WLAN_MD_11ABGN = (WLAN_MD_11A | WLAN_MD_11B | WLAN_MD_11G | WLAN_MD_11N ),
|
||||
WLAN_MD_11ANAC = (WLAN_MD_11A | WLAN_MD_11N | WLAN_MD_11AC),
|
||||
WLAN_MD_11BGNAC = (WLAN_MD_11B | WLAN_MD_11G | WLAN_MD_11N | WLAN_MD_11AC),
|
||||
WLAN_MD_11GNAC = (WLAN_MD_11G | WLAN_MD_11N | WLAN_MD_11AC),
|
||||
WLAN_MD_24G_MIX = (WLAN_MD_11B | WLAN_MD_11G | WLAN_MD_11N | WLAN_MD_11AC | WLAN_MD_11AX),
|
||||
WLAN_MD_5G_MIX = (WLAN_MD_11A | WLAN_MD_11N | WLAN_MD_11AC | WLAN_MD_11AX),
|
||||
WLAN_MD_6G_MIX = (WLAN_MD_11A | WLAN_MD_11AX),
|
||||
WLAN_MD_MAX = (WLAN_MD_24G_MIX|WLAN_MD_5G_MIX),
|
||||
};
|
||||
|
||||
enum band_type {
|
||||
BAND_ON_24G = 0,
|
||||
BAND_ON_5G = 1,
|
||||
BAND_ON_6G = 2,
|
||||
BAND_MAX,
|
||||
};
|
||||
|
||||
/*HW SPEC & SW/HW CAP*/
|
||||
#define BAND_CAP_2G BIT(BAND_ON_24G)
|
||||
#define BAND_CAP_5G BIT(BAND_ON_5G)
|
||||
#define BAND_CAP_6G BIT(BAND_ON_6G)
|
||||
#define BAND_CAP_BIT_NUM 3
|
||||
|
||||
enum channel_width {
|
||||
CHANNEL_WIDTH_20 = 0,
|
||||
CHANNEL_WIDTH_40 = 1,
|
||||
CHANNEL_WIDTH_80 = 2,
|
||||
CHANNEL_WIDTH_160 = 3,
|
||||
CHANNEL_WIDTH_320 = 4,
|
||||
CHANNEL_WIDTH_80_80 = 5,
|
||||
CHANNEL_WIDTH_5 = 6,
|
||||
CHANNEL_WIDTH_10 = 7,
|
||||
CHANNEL_WIDTH_MAX = 8,
|
||||
};
|
||||
|
||||
/*HW SPEC & SW/HW CAP*/
|
||||
#define BW_CAP_20M BIT(CHANNEL_WIDTH_20)
|
||||
#define BW_CAP_40M BIT(CHANNEL_WIDTH_40)
|
||||
#define BW_CAP_80M BIT(CHANNEL_WIDTH_80)
|
||||
#define BW_CAP_160M BIT(CHANNEL_WIDTH_160)
|
||||
#define BW_CAP_320M BIT(CHANNEL_WIDTH_320)
|
||||
#define BW_CAP_80_80M BIT(CHANNEL_WIDTH_80_80)
|
||||
#define BW_CAP_5M BIT(CHANNEL_WIDTH_5)
|
||||
#define BW_CAP_10M BIT(CHANNEL_WIDTH_10)
|
||||
#define BW_CAP_BIT_NUM 8
|
||||
|
||||
|
||||
/*
|
||||
* Represent Extention Channel Offset in HT Capabilities
|
||||
* Secondary Channel Offset
|
||||
* 0 -SCN, 1 -SCA, 2 -RSVD, 3 - SCB
|
||||
*
|
||||
*/
|
||||
enum chan_offset {
|
||||
CHAN_OFFSET_NO_EXT = 0, /*SCN - no secondary channel*/
|
||||
CHAN_OFFSET_UPPER = 1, /*SCA - secondary channel above*/
|
||||
CHAN_OFFSET_NO_DEF = 2, /*Reserved*/
|
||||
CHAN_OFFSET_LOWER = 3, /*SCB - secondary channel below*/
|
||||
CHAN_OFFSET_40M_UPPER = 4,
|
||||
CHAN_OFFSET_40M_LOWER = 5,
|
||||
CHAN_OFFSET_80M_UPPER = 6,
|
||||
CHAN_OFFSET_80M_LOWER = 7,
|
||||
};
|
||||
|
||||
enum rf_type {
|
||||
RF_1T1R = 0,
|
||||
RF_1T2R = 1,
|
||||
RF_2T2R = 2,
|
||||
RF_2T3R = 3,
|
||||
RF_2T4R = 4,
|
||||
RF_3T3R = 5,
|
||||
RF_3T4R = 6,
|
||||
RF_4T4R = 7,
|
||||
RF_TYPE_MAX,
|
||||
};
|
||||
|
||||
enum rtw_rf_state {
|
||||
RTW_RF_ON,
|
||||
RTW_RF_OFF,
|
||||
RTW_RF_MAX
|
||||
};
|
||||
|
||||
enum rtw_usb_speed {
|
||||
RTW_USB_SPEED_LOW = 0, /*U2 (2.0)- 1.0 - 1.5 Mbps - 0.192MBs*/
|
||||
RTW_USB_SPEED_FULL = 1, /*U2 (2.0)- 1.1 - 12 Mbps - 1.5MBs*/
|
||||
RTW_USB_SPEED_HIGH = 2, /*U2 (2.0)- 2.1 - 480 Mbps - 60MBs*/
|
||||
RTW_USB_SPEED_SUPER = 3, /*U3 (3.2 Gen 1)- 3.0 - 5 Gbps - 640MBs*/
|
||||
RTW_USB_SPEED_SUPER_10G = 4, /*U3 (3.2 Gen 2)- 3.1 - 10 Gbps - 1280MBs*/
|
||||
RTW_USB_SPEED_SUPER_20G = 5, /*U3 (3.2 Gen 2x2)- 3.2 - 20 Gbps - 2560MBs*/
|
||||
|
||||
/* keep last */
|
||||
RTW_USB_SPEED_MAX,
|
||||
RTW_USB_SPEED_UNKNOWN = RTW_USB_SPEED_MAX,
|
||||
};
|
||||
|
||||
#define USB_SUPER_SPEED_BULK_SIZE 1024 /* usb 3.0 */
|
||||
#define USB_HIGH_SPEED_BULK_SIZE 512 /* usb 2.0 */
|
||||
#define USB_FULL_SPEED_BULK_SIZE 64 /* usb 1.1 */
|
||||
|
||||
#define IV_LENGTH 8
|
||||
|
||||
enum rtw_enc_algo {
|
||||
RTW_ENC_NONE,
|
||||
RTW_ENC_WEP40,
|
||||
RTW_ENC_WEP104,
|
||||
RTW_ENC_TKIP,
|
||||
RTW_ENC_WAPI,
|
||||
RTW_ENC_GCMSMS4,
|
||||
RTW_ENC_CCMP,
|
||||
RTW_ENC_CCMP256,
|
||||
RTW_ENC_GCMP,
|
||||
RTW_ENC_GCMP256,
|
||||
RTW_ENC_BIP_CCMP128,
|
||||
RTW_ENC_MAX
|
||||
};
|
||||
|
||||
enum rtw_sec_ent_mode {
|
||||
RTW_SEC_ENT_MODE_0, /* No key */
|
||||
RTW_SEC_ENT_MODE_1, /* WEP */
|
||||
RTW_SEC_ENT_MODE_2, /* 2 unicast + 3 multicast + 2 BIP keys */
|
||||
RTW_SEC_ENT_MODE_3, /* 2 unicast + 4 multicast + 1 BIP keys */
|
||||
};
|
||||
|
||||
enum rtw_sec_key_type {
|
||||
RTW_SEC_KEY_UNICAST,
|
||||
RTW_SEC_KEY_MULTICAST,
|
||||
RTW_SEC_KEY_BIP,
|
||||
RTW_SEC_KEY_MAX
|
||||
};
|
||||
|
||||
/**
|
||||
* Figure 27-7 + Table 9-31h from Ax Spec D4.2
|
||||
* B7-B1:
|
||||
* RU26 : 0 1 2 3 4 5 6 7 8 9 10 ... 36
|
||||
* RU52 : 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
|
||||
* RU106 : 53 54 55 56 57 58 59 60
|
||||
* RU242 : 61 62 63 64
|
||||
* RU484 : 65 66
|
||||
* RU996 : 67
|
||||
* RU996x2: 68
|
||||
**/
|
||||
enum rtw_he_ru_idx {
|
||||
/* 20MHz - 1 */
|
||||
RTW_HE_RU26_1 = 0,
|
||||
RTW_HE_RU26_2,
|
||||
RTW_HE_RU26_3,
|
||||
RTW_HE_RU26_4,
|
||||
RTW_HE_RU26_5,
|
||||
RTW_HE_RU26_6,
|
||||
RTW_HE_RU26_7,
|
||||
RTW_HE_RU26_8,
|
||||
RTW_HE_RU26_9,
|
||||
/* 20MHz - 2 */
|
||||
RTW_HE_RU26_10,
|
||||
RTW_HE_RU26_11,
|
||||
RTW_HE_RU26_12,
|
||||
RTW_HE_RU26_13,
|
||||
RTW_HE_RU26_14,
|
||||
RTW_HE_RU26_15,
|
||||
RTW_HE_RU26_16,
|
||||
RTW_HE_RU26_17,
|
||||
RTW_HE_RU26_18,
|
||||
/* Center 26-tone */
|
||||
RTW_HE_RU26_19,
|
||||
/* 20MHz - 3 */
|
||||
RTW_HE_RU26_20,
|
||||
RTW_HE_RU26_21,
|
||||
RTW_HE_RU26_22,
|
||||
RTW_HE_RU26_23,
|
||||
RTW_HE_RU26_24,
|
||||
RTW_HE_RU26_25,
|
||||
RTW_HE_RU26_26,
|
||||
RTW_HE_RU26_27,
|
||||
RTW_HE_RU26_28,
|
||||
/* 20MHz - 4 */
|
||||
RTW_HE_RU26_29,
|
||||
RTW_HE_RU26_30,
|
||||
RTW_HE_RU26_31,
|
||||
RTW_HE_RU26_32,
|
||||
RTW_HE_RU26_33,
|
||||
RTW_HE_RU26_34,
|
||||
RTW_HE_RU26_35,
|
||||
RTW_HE_RU26_36,
|
||||
RTW_HE_RU26_37 = 36,
|
||||
/* 20MHz - 1 */
|
||||
RTW_HE_RU52_1 = 37,
|
||||
RTW_HE_RU52_2,
|
||||
RTW_HE_RU52_3,
|
||||
RTW_HE_RU52_4,
|
||||
/* 20MHz - 2 */
|
||||
RTW_HE_RU52_5,
|
||||
RTW_HE_RU52_6,
|
||||
RTW_HE_RU52_7,
|
||||
RTW_HE_RU52_8,
|
||||
/* 20MHz - 3 */
|
||||
RTW_HE_RU52_9,
|
||||
RTW_HE_RU52_10,
|
||||
RTW_HE_RU52_11,
|
||||
RTW_HE_RU52_12,
|
||||
/* 20MHz - 4 */
|
||||
RTW_HE_RU52_13,
|
||||
RTW_HE_RU52_14,
|
||||
RTW_HE_RU52_15,
|
||||
RTW_HE_RU52_16 = 52,
|
||||
/* 20MHz - 1 */
|
||||
RTW_HE_RU106_1 = 53,
|
||||
RTW_HE_RU106_2,
|
||||
/* 20MHz - 2 */
|
||||
RTW_HE_RU106_3,
|
||||
RTW_HE_RU106_4,
|
||||
/* 20MHz - 3 */
|
||||
RTW_HE_RU106_5,
|
||||
RTW_HE_RU106_6,
|
||||
/* 20MHz - 4 */
|
||||
RTW_HE_RU106_7,
|
||||
RTW_HE_RU106_8 = 60,
|
||||
/* 20MHz */
|
||||
RTW_HE_RU242_1 = 61,
|
||||
RTW_HE_RU242_2,
|
||||
RTW_HE_RU242_3,
|
||||
RTW_HE_RU242_4 = 64,
|
||||
/* 40MHz */
|
||||
RTW_HE_RU484_1 = 65,
|
||||
RTW_HE_RU484_2 = 66,
|
||||
/* 80MHz */
|
||||
RTW_HE_RU996_1 = 67,
|
||||
/* 160MHz */
|
||||
RTW_HE_RU2x996_1 = 68,
|
||||
};
|
||||
|
||||
enum rtw_protect_mode {
|
||||
RTW_PROTECT_DISABLE = 0,
|
||||
RTW_PROTECT_RTS = 1,
|
||||
RTW_PROTECT_CTS2SELF = 2,
|
||||
RTW_PROTECT_HW_RTS = 3
|
||||
};
|
||||
|
||||
enum rtw_ac {
|
||||
RTW_AC_BE = 0,
|
||||
RTW_AC_BK = 1,
|
||||
RTW_AC_VI = 2,
|
||||
RTW_AC_VO = 3,
|
||||
RTW_AC_MAX
|
||||
};
|
||||
|
||||
enum rtw_edcca_mode {
|
||||
RTW_EDCCA_NORMAL,
|
||||
RTW_EDCCA_ETSI,
|
||||
RTW_EDCCA_JP,
|
||||
RTW_EDCCA_FCC,
|
||||
RTW_EDCCA_MAX
|
||||
};
|
||||
|
||||
enum rtw_mac_pwr_st {
|
||||
RTW_MAC_PWR_NONE = 0,
|
||||
RTW_MAC_PWR_OFF = 1,
|
||||
RTW_MAC_PWR_ON = 2,
|
||||
RTW_MAC_PWR_LPS = 3,
|
||||
RTW_MAC_PWR_MAX = 0x4
|
||||
};
|
||||
|
||||
enum rtw_pcie_bus_func_cap_t {
|
||||
RTW_PCIE_BUS_FUNC_DISABLE = 0,
|
||||
RTW_PCIE_BUS_FUNC_ENABLE = 1,
|
||||
RTW_PCIE_BUS_FUNC_DEFAULT = 2,
|
||||
RTW_PCIE_BUS_FUNC_IGNORE = 3
|
||||
};
|
||||
|
||||
/* follow mac's definetion, mac_ax_sw_io_mode*/
|
||||
enum rtw_gpio_mode {
|
||||
RTW_AX_SW_IO_MODE_INPUT,
|
||||
RTW_AX_SW_IO_MODE_OUTPUT_OD,
|
||||
RTW_AX_SW_IO_MODE_OUTPUT_PP,
|
||||
RTW_AX_SW_IO_MODE_MAX
|
||||
};
|
||||
|
||||
enum rtw_p2p_app_type {
|
||||
RTW_P2P_APP_NONE = 0,
|
||||
RTW_P2P_APP_UNKNOWN = 1,
|
||||
RTW_P2P_APP_GC = 2,
|
||||
RTW_P2P_APP_GO_HOTSPOT =3,
|
||||
RTW_P2P_APP_GO_SRC = 4,
|
||||
RTW_P2P_APP_GO_SINK = 5,
|
||||
RTW_P2P_APP_GO_SRC_SINK = 6,
|
||||
RTW_P2P_SESSION_MAX
|
||||
};
|
||||
|
||||
/*MAC_AX_PCIE_L0SDLY_IGNORE = 0xFF, MAC_AX_PCIE_L1DLY_IGNORE = 0xFF, MAC_AX_PCIE_CLKDLY_IGNORE = 0xFF */
|
||||
#define RTW_PCIE_BUS_ASPM_DLY_IGNORE 0xFF /* Fully controlled by HW */
|
||||
|
||||
#define RTW_FRAME_TYPE_MGNT 0
|
||||
#define RTW_FRAME_TYPE_CTRL 1
|
||||
#define RTW_FRAME_TYPE_DATA 2
|
||||
#define RTW_FRAME_TYPE_EXT_RSVD 3
|
||||
/* Association Related PKT Type + SubType */
|
||||
|
||||
#define FRAME_OFFSET_FRAME_CONTROL 0
|
||||
#define FRAME_OFFSET_DURATION 2
|
||||
#define FRAME_OFFSET_ADDRESS1 4
|
||||
#define FRAME_OFFSET_ADDRESS2 10
|
||||
#define FRAME_OFFSET_ADDRESS3 16
|
||||
#define FRAME_OFFSET_SEQUENCE 22
|
||||
#define FRAME_OFFSET_ADDRESS4 24
|
||||
#define PHL_GET_80211_HDR_TYPE(_hdr) LE_BITS_TO_2BYTE((u8 *)_hdr, 2, 6)
|
||||
#define PHL_GET_80211_HDR_MORE_FRAG(_hdr) LE_BITS_TO_2BYTE((u8 *)_hdr, 10, 1)
|
||||
#define PHL_GET_80211_HDR_RETRY(_hdr) LE_BITS_TO_2BYTE((u8 *)_hdr, 11, 1)
|
||||
#define PHL_GET_80211_HDR_FRAG_NUM(_hdr) LE_BITS_TO_2BYTE((u8 *)_hdr + 22, 0, 4)
|
||||
#define PHL_GET_80211_HDR_SEQUENCE(_hdr) LE_BITS_TO_2BYTE((u8 *)_hdr + 22, 4, 12)
|
||||
#define PHL_GET_80211_HDR_ADDRESS2(_d, _hdr, _val) \
|
||||
_os_mem_cpy(_d, (u8 *)_val, (u8 *)_hdr + FRAME_OFFSET_ADDRESS2, 6)
|
||||
#define PHL_GET_80211_HDR_ADDRESS3(_d, _hdr, _val) \
|
||||
_os_mem_cpy(_d, (u8 *)_val, (u8 *)_hdr + FRAME_OFFSET_ADDRESS3, 6)
|
||||
|
||||
#define RTW_FRAME_TYPE_BEACON 32
|
||||
#define RTW_FRAME_TYPE_PROBE_RESP 20
|
||||
#define RTW_FRAME_TYPE_ASOC_REQ 0
|
||||
#define RTW_FRAME_TYPE_ASOC_RESP 4
|
||||
#define RTW_FRAME_TYPE_REASOC_REQ 8
|
||||
#define RTW_FRAME_TYPE_REASOC_RESP 12
|
||||
#define RTW_FRAME_TYPE_ACK 53
|
||||
#define RTW_FRAME_TYPE_MAX 0xFF
|
||||
#define RTW_IS_ASOC_PKT(_TYPE) \
|
||||
((_TYPE == RTW_FRAME_TYPE_REASOC_RESP) || \
|
||||
(_TYPE == RTW_FRAME_TYPE_REASOC_REQ) || \
|
||||
(_TYPE == RTW_FRAME_TYPE_ASOC_RESP) || \
|
||||
(_TYPE == RTW_FRAME_TYPE_ASOC_REQ)) ? true : false
|
||||
|
||||
#define RTW_IS_ASOC_REQ_PKT(_TYPE) \
|
||||
((_TYPE == RTW_FRAME_TYPE_REASOC_REQ) || \
|
||||
(_TYPE == RTW_FRAME_TYPE_ASOC_REQ)) ? true : false
|
||||
|
||||
#define RTW_IS_BEACON_OR_PROBE_RESP_PKT(_TYPE) \
|
||||
((_TYPE == RTW_FRAME_TYPE_BEACON) || \
|
||||
(_TYPE == RTW_FRAME_TYPE_PROBE_RESP)) ? true : false
|
||||
|
||||
#define TU 1024 /* Time Unit (TU): 1024 us*/
|
||||
|
||||
#define RTW_MAX_ETH_PKT_LEN 1536
|
||||
|
||||
#define WL_SEQ_MASK 0xfff /* PHL_RXSC_AMPDU */
|
||||
|
||||
#define RX_DESC_PPDU_T_LCCK 0
|
||||
#define RX_DESC_PPDU_T_SCCK 1
|
||||
#define RX_DESC_PPDU_T_OFDM 2
|
||||
#define RX_DESC_PPDU_T_HT 3
|
||||
#define RX_DESC_PPDU_T_HTGF 4
|
||||
#define RX_DESC_PPDU_T_VHT_SU 5
|
||||
#define RX_DESC_PPDU_T_VHT_MU 6
|
||||
#define RX_DESC_PPDU_T_HE_SU 7
|
||||
#define RX_DESC_PPDU_T_HE_ERSU 8
|
||||
#define RX_DESC_PPDU_T_HE_MU 9
|
||||
#define RX_DESC_PPDU_T_HE_TB 10
|
||||
#define RX_DESC_PPDU_T_UNKNOWN 15
|
||||
|
||||
#endif /*_RTW_GENERAL_DEF_H_*/
|
||||
+666
@@ -0,0 +1,666 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2020 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in the
|
||||
* file called LICENSE.
|
||||
*
|
||||
* Contact Information:
|
||||
* wlanfae <wlanfae@realtek.com>
|
||||
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
|
||||
* Hsinchu 300, Taiwan.
|
||||
*
|
||||
* Larry Finger <Larry.Finger@lwfinger.net>
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef __HALBB_H__
|
||||
#define __HALBB_H__
|
||||
|
||||
/*@--------------------------[Define] ---------------------------------------*/
|
||||
|
||||
#define ACTIVE_TP_THRESHOLD 1
|
||||
#define BB_WATCH_DOG_PERIOD 2 /*sec*/
|
||||
#define is_sta_active(sta) ((sta) && (sta->active))
|
||||
#define HALBB_SNPRINT_SIZE 200
|
||||
#define HALBB_SNPRINT_SIZE_S 20
|
||||
|
||||
#define BB_EFUSE_BAND_NUM 5
|
||||
#define IC_LNA_NUM 7
|
||||
#define IC_TIA_NUM 2
|
||||
#define IC_LNA_OP1DB_NUM 7
|
||||
#define IC_TIA_LNA_OP1DB_NUM 8
|
||||
#define EFUSE_OFST_NUM 1
|
||||
#define WB_GIDX_ELNA_NUM 16
|
||||
#define GS_IDX_NUM 2
|
||||
#define G_ELNA_NUM 2
|
||||
|
||||
/*@--------------------------[Enum]------------------------------------------*/
|
||||
|
||||
enum bb_trx_state_t {
|
||||
BB_TX_STATE = 0,
|
||||
BB_RX_STATE = 1,
|
||||
BB_BI_DIR_STATE = 2
|
||||
};
|
||||
|
||||
enum bb_trafic_t {
|
||||
TRAFFIC_NO_TP = 0,
|
||||
TRAFFIC_ULTRA_LOW = 1,
|
||||
TRAFFIC_LOW = 2,
|
||||
TRAFFIC_MID = 3,
|
||||
TRAFFIC_HIGH = 4
|
||||
};
|
||||
|
||||
enum efuse_bit_mask {
|
||||
LOW_MASK = 0,
|
||||
HIGH_MASK = 1
|
||||
};
|
||||
|
||||
/*For 2G/5G/6G*/
|
||||
enum mcc_band {
|
||||
MCC_BAND_1 = 0,
|
||||
MCC_BAND_2,
|
||||
MCC_BAND_NUM
|
||||
};
|
||||
|
||||
enum mr_band {
|
||||
MR_BAND_1 = 0,
|
||||
MR_BAND_2 = 1,
|
||||
MR_BAND_3 = 2,
|
||||
MR_BAND_NUM
|
||||
};
|
||||
|
||||
enum bb_mcc_t {
|
||||
BB_MCC_DISABLE = 0,
|
||||
BB_MCC_ENABLE = 1,
|
||||
BB_MCC_INVALID
|
||||
};
|
||||
|
||||
enum halbb_mcc_reg {
|
||||
SEG0R_PD_LOWER_BOUND = 0,
|
||||
NUM_MAX_REG_CNT
|
||||
};
|
||||
|
||||
enum halbb_mr_err_code{
|
||||
BB_MRDM_DISABLE = 0,
|
||||
BB_MRDM_REG_OVERFLOW = 1,
|
||||
BB_MRDM_CLR_CH = 2,
|
||||
BB_MRDM_SEARCH_CH_FAIL = 3,
|
||||
BB_MRDM_ONE_CH_ONLY = 4,
|
||||
BB_MRDM_SWITCH_CR = 5,
|
||||
BB_MRDM_START = 6,
|
||||
BB_MRDM_ERR_MAX
|
||||
};
|
||||
/*@--------------------------[Structure]-------------------------------------*/
|
||||
|
||||
struct halbb_pause_lv {
|
||||
s8 lv_fa_cnt;
|
||||
s8 lv_dig;
|
||||
s8 lv_env_mntr;
|
||||
s8 lv_cfo;
|
||||
s8 lv_edcca;
|
||||
s8 lv_path_div;
|
||||
s8 lv_ant_div;
|
||||
};
|
||||
|
||||
struct bb_func_hooker_info {
|
||||
void (*pause_bb_dm_handler)(struct bb_info *bb, u32 *val_buf, u8 val_len);
|
||||
};
|
||||
|
||||
struct bb_iot_info {
|
||||
u8 is_linked_cmw500:1;
|
||||
u8 patch_id_00000000:1;
|
||||
u8 rsvd:6;
|
||||
};
|
||||
|
||||
struct bb_path_info {
|
||||
/*[Path info]*/
|
||||
u8 tx_path_en; /*TX path enable*/
|
||||
u8 rx_path_en; /*RX path enable*/
|
||||
#ifdef HALBB_COMPILE_ABOVE_4SS
|
||||
enum bb_path tx_4ss_path_map; /*@Use N-X for 4STS rate*/
|
||||
#endif
|
||||
#ifdef HALBB_COMPILE_ABOVE_3SS
|
||||
enum bb_path tx_3ss_path_map; /*@Use N-X for 3STS rate*/
|
||||
#endif
|
||||
#ifdef HALBB_COMPILE_ABOVE_2SS
|
||||
enum bb_path tx_2ss_path_map; /*@Use N-X for 2STS rate*/
|
||||
#endif
|
||||
enum bb_path tx_1ss_path_map; /*@Use N-X for 1STS rate*/
|
||||
};
|
||||
|
||||
struct bb_link_info {
|
||||
/*[Link Info]*/
|
||||
bool is_linked;
|
||||
bool is_linked_pre;
|
||||
bool first_connect;
|
||||
bool first_disconnect;
|
||||
enum bb_trx_state_t txrx_state_all;
|
||||
enum bb_bw_type bb_bw;
|
||||
/*[One Entry TP Info]*/
|
||||
bool is_one_entry_only;
|
||||
u32 one_entry_macid;
|
||||
u32 first_entry_macid;
|
||||
u32 one_entry_tp;
|
||||
u32 one_entry_tp_pre;
|
||||
u16 tp_active_th;
|
||||
bool one_entry_tp_active_occur;
|
||||
bool is_match_bssid;
|
||||
/*[Client Number]*/
|
||||
u8 num_linked_client;
|
||||
u8 num_linked_client_pre;
|
||||
u8 num_active_client;
|
||||
u8 num_active_client_pre;
|
||||
/*[TP & Traffic]*/
|
||||
u8 traffic_load;
|
||||
u8 traffic_load_pre;
|
||||
u16 tx_rate; /*from the first sta*/
|
||||
u16 rx_rate_plurality;
|
||||
u16 rx_rate_plurality_mu;
|
||||
u16 rx_utility;
|
||||
u16 tx_utility;
|
||||
u16 avg_phy_rate; /*Rx avg phy rate*/
|
||||
u16 tx_avg_phy_rate; /*Tx avg phy rate*/
|
||||
u32 tx_tp; /*@Mbps*/
|
||||
u32 rx_tp; /*@Mbps*/
|
||||
u32 total_tp; /*@Mbps*/
|
||||
u16 consecutive_idle_time; /*@unit: second*/
|
||||
u16 wlan_mode_bitmap; /*enum wlan_mode*/
|
||||
/*[at least one macid BFer & BFee chk]*/
|
||||
bool at_least_one_bfer; /*at least one macid Tx BFer*/
|
||||
bool at_least_one_bfee; /*at least one macid Rx BFee*/
|
||||
};
|
||||
|
||||
struct bb_ch_info {
|
||||
u8 fc_ch_idx;
|
||||
bool is_2g;
|
||||
u8 rssi_min; /*U(8.1), external rssi (from antenna)*/
|
||||
u16 rssi_min_macid;
|
||||
u8 pre_rssi_min;
|
||||
u8 rssi_max; /*U(8.1), external rssi (from antenna)*/
|
||||
u16 rssi_max_macid;
|
||||
u8 rxsc_160;
|
||||
u8 rxsc_80;
|
||||
u8 rxsc_40;
|
||||
u8 rxsc_20;
|
||||
u8 rxsc_l;
|
||||
u8 is_noisy;
|
||||
u8 rf_central_ch_cfg; /*report in phy-sts*/
|
||||
s8 ext_loss[HALBB_MAX_PATH]; /*S(8.2), update when switching ch*/
|
||||
s8 ext_loss_avg; /*S(8.2), update when switching ch*/
|
||||
u8 int_rssi_min; /*U(8.1), internal rssi (from ADC output) = external rssi - ext_loss*/
|
||||
u8 int_rssi_max; /*U(8.1), internal rssi (from ADC output) = external rssi - ext_loss*/
|
||||
u8 drv_op_ch[MR_BAND_NUM];
|
||||
u8 drv_op_bw[MR_BAND_NUM];
|
||||
u8 drv_op_band[MR_BAND_NUM];
|
||||
};
|
||||
|
||||
struct bb_cmn_backup_info {
|
||||
u8 cur_tx_path;
|
||||
u8 cur_rx_path;
|
||||
s16 cur_tx_pwr;
|
||||
u8 cur_pd_lower_bound;
|
||||
u8 last_rpl;
|
||||
u32 last_rssi;
|
||||
u16 last_cfo;
|
||||
s32 cck_ps_th_bk;
|
||||
s32 cck_rssi_ofst_bk;
|
||||
s32 cck_sbd_th_bk;
|
||||
u32 cur_rfmode_a_12ac;
|
||||
u32 cur_rfmode_a_12b0;
|
||||
u32 cur_rfmode_b_32ac;
|
||||
u32 cur_rfmode_b_32b0;
|
||||
struct rssi_physts last_rssi_rpt;
|
||||
struct rxevm_physts last_rxevm_rpt;
|
||||
};
|
||||
|
||||
struct bb_gain_info {
|
||||
s8 lna_gain[BB_GAIN_BAND_NUM][HALBB_MAX_PATH][IC_LNA_NUM];
|
||||
s8 tia_gain[BB_GAIN_BAND_NUM][HALBB_MAX_PATH][IC_TIA_NUM];
|
||||
s8 lna_gain_bypass[BB_GAIN_BAND_NUM][HALBB_MAX_PATH][IC_LNA_NUM];
|
||||
s8 lna_op1db[BB_GAIN_BAND_NUM][HALBB_MAX_PATH][IC_LNA_NUM];
|
||||
s8 tia_lna_op1db[BB_GAIN_BAND_NUM][HALBB_MAX_PATH][IC_LNA_NUM + 1]; // TIA0_LNA0~6 + TIA1_LNA6
|
||||
s8 efuse_ofst[BB_GAIN_BAND_NUM][HALBB_MAX_PATH][EFUSE_OFST_NUM];
|
||||
s8 rpl_ofst_20[BB_GAIN_BAND_NUM][HALBB_MAX_PATH];
|
||||
s8 rpl_ofst_40[BB_GAIN_BAND_NUM][HALBB_MAX_PATH][BB_RXSC_NUM_40];
|
||||
s8 rpl_ofst_80[BB_GAIN_BAND_NUM][HALBB_MAX_PATH][BB_RXSC_NUM_80];
|
||||
s8 rpl_ofst_160[BB_GAIN_BAND_NUM][HALBB_MAX_PATH][BB_RXSC_NUM_160];
|
||||
u32 wb_gidx_elna[BB_GAIN_BAND_NUM][HALBB_MAX_PATH]; // {bit(15) ~ bit(0)}: {wb_gidx_15_elna ~ wb_gidx_0_elna}
|
||||
u8 wb_gidx_lna_tia[BB_GAIN_BAND_NUM][HALBB_MAX_PATH][WB_GIDX_ELNA_NUM];
|
||||
u32 gs_idx[BB_GAIN_BAND_NUM][HALBB_MAX_PATH][GS_IDX_NUM];
|
||||
u8 g_elna[BB_GAIN_BAND_NUM][HALBB_MAX_PATH][G_ELNA_NUM];
|
||||
};
|
||||
|
||||
struct bb_efuse_info{
|
||||
bool normal_efuse_check;
|
||||
bool hidden_efuse_check;
|
||||
s8 gain_offset[HALBB_MAX_PATH][BB_BAND_NUM_MAX + 1]; // S(8,0)
|
||||
s8 gain_cs[HALBB_MAX_PATH][BB_BAND_NUM_MAX]; // S(8,0)
|
||||
s8 gain_cg[HALBB_MAX_PATH][BB_BAND_NUM_MAX]; // S(8,0)
|
||||
s8 hidden_efuse[BB_HIDE_EFUSE_SIZE];
|
||||
|
||||
s8 lna_err_2g[HALBB_MAX_PATH][7]; // S(6,2)
|
||||
s8 lna_err_5g[HALBB_MAX_PATH][7]; // S(6,2)
|
||||
|
||||
s8 frontend_loss[HALBB_MAX_PATH];
|
||||
s8 rpl_bias_comp[HALBB_MAX_PATH];
|
||||
s8 rssi_bias_comp[HALBB_MAX_PATH];
|
||||
|
||||
s8 efuse_ofst[HW_PHY_MAX]; // 8852A:S(5,2) 8852B:S(8,4)
|
||||
s8 efuse_ofst_path[HALBB_MAX_PATH]; // 8852C: S(8,4)
|
||||
s8 efuse_ofst_tb[HW_PHY_MAX]; // 8852A:S(7,4) 8852B:S(8,4)
|
||||
s8 efuse_ofst_tb_path[HALBB_MAX_PATH]; // 8852C: S(8,4)
|
||||
s8 rpl_ofst_cck; // 8852D: S(8,0)
|
||||
|
||||
u8 efuse_ft; // 8192XB: U(8,0)
|
||||
u8 efuse_adc_td; // 8192XB: U(2,0)
|
||||
|
||||
s8 cck_rpl_ofst_ref;
|
||||
};
|
||||
|
||||
struct vht_mu_cr_backup_table {
|
||||
u32 muic_en_a;
|
||||
u32 lpbw_sw_symb0_a;
|
||||
u32 ch_tracking_symb0_a;
|
||||
u32 lpbw_sel_d1_a;
|
||||
u32 ch_tracking_symb1_a;
|
||||
u32 ch_tracking_a1_a;
|
||||
u32 lpbw_sel_p1_a;
|
||||
u32 noise_tracking_en_a;
|
||||
};
|
||||
|
||||
struct bb_cmn_dbg_info {
|
||||
bool cmn_log_2_cnsl_en;
|
||||
bool cmn_log_2_drv_statistic_en;
|
||||
};
|
||||
|
||||
struct bb_cmn_info {
|
||||
enum wlan_mode wlan_mode_max;
|
||||
u8 bb_dm_number;
|
||||
bool cck_blk_en;
|
||||
enum phl_phy_idx cck_phy_map;
|
||||
bool bb_dbcc_en;
|
||||
bool ic_dual_phy_support;
|
||||
bool ic_dbcc_support;
|
||||
bool lbk_verify_en;
|
||||
bool watchdog_io_saving_en;
|
||||
bool scan_in_drv;
|
||||
enum halbb_drv_type bb_drv_type;
|
||||
#ifdef HALBB_COMPILE_IC_DBCC_MLO
|
||||
enum mlo_dbcc_mode_type bb_mlo_dbcc_mode_t;
|
||||
#endif
|
||||
#ifdef HALBB_RA_SUPPORT
|
||||
struct bb_ra_info bb_ra_i[PHL_MAX_STA_NUM];
|
||||
struct bb_ra_drv_info bb_ra_drv_i;
|
||||
struct bb_ra_dbg_info bb_ra_dbg_i;
|
||||
#endif
|
||||
#ifdef HALBB_PSD_SUPPORT
|
||||
struct bb_psd_info bb_psd_i;
|
||||
#endif
|
||||
#ifdef HALBB_LA_MODE_SUPPORT
|
||||
struct bb_la_mode_info bb_la_mode_i;
|
||||
#endif
|
||||
#ifdef HALBB_SNIF_SUPPORT
|
||||
struct bb_snif_info bb_snif_i;
|
||||
#endif
|
||||
#ifdef HALBB_DYN_CSI_RSP_SUPPORT
|
||||
struct bf_ch_raw_info bf_ch_raw_i;
|
||||
#endif
|
||||
struct bb_spur_info bb_spur_i;
|
||||
struct bb_echo_cmd_info bb_echo_cmd_i;
|
||||
struct bb_func_hooker_info bb_func_hooker_i;
|
||||
struct bb_cmn_dbg_info bb_cmn_dbg_i;
|
||||
#ifdef HALBB_FW_OFLD_SUPPORT
|
||||
u8 bbcr_fwofld_state;
|
||||
bool skip_io_init_en;
|
||||
bool is_io_ofld_success;
|
||||
#endif
|
||||
bool bb_fwofld_in_progress;
|
||||
u32 bb_fwofld_sup_bitmap; /*enum fw_ofld_type.For HALBB to control DBCC-OFLD manully*/
|
||||
u32 bb_fwofld_start_time;
|
||||
struct bb_dbg_cr_info bb_dbg_cr_i;
|
||||
struct bb_physts_cr_info bb_physts_cr_i;
|
||||
#ifdef HALBB_STATISTICS_SUPPORT
|
||||
struct bb_stat_cr_info bb_stat_cr_i;
|
||||
#endif
|
||||
#ifdef HALBB_DIG_SUPPORT
|
||||
struct bb_dig_cr_info bb_dig_cr_i;
|
||||
#endif
|
||||
#ifdef HALBB_ENV_MNTR_SUPPORT
|
||||
struct bb_env_mntr_cr_info bb_env_mntr_cr_i;
|
||||
#endif
|
||||
#ifdef HALBB_EDCCA_SUPPORT
|
||||
struct bb_edcca_cr_info bb_edcca_cr_i;
|
||||
#endif
|
||||
#ifdef HALBB_DFS_SUPPORT
|
||||
struct bb_dfs_cr_info bb_dfs_cr_i;
|
||||
#endif
|
||||
#ifdef HALBB_ANT_DIV_SUPPORT
|
||||
struct bb_antdiv_cr_info bb_antdiv_cr_i;
|
||||
#endif
|
||||
#ifdef HALBB_PMAC_TX_SUPPORT
|
||||
struct bb_plcp_cr_info bb_plcp_cr_i;
|
||||
#endif
|
||||
struct bb_rpt_info bb_rpt_i;
|
||||
#ifdef HALBB_CH_INFO_SUPPORT
|
||||
struct bb_ch_info_cr_info bb_ch_info_cr_i; /*CR callback table*/
|
||||
#endif
|
||||
#ifdef HALBB_CFO_TRK_SUPPORT
|
||||
struct bb_cfo_trk_cr_info bb_cfo_trk_cr_i;
|
||||
#endif
|
||||
#ifdef HALBB_UL_TB_CTRL_SUPPORT
|
||||
struct bb_ul_tb_cr_info bb_ul_tb_cr_i;
|
||||
#endif
|
||||
#ifdef HALBB_SR_SUPPORT
|
||||
struct bb_spatial_reuse_cr_info bb_spatial_reuse_cr_i;
|
||||
#endif
|
||||
#ifdef HALBB_SNIF_SUPPORT
|
||||
struct bb_snif_cr_info bb_snif_cr_i;
|
||||
#endif
|
||||
struct bb_hw_cfg_cr_info bb_hw_cfg_cr_i;
|
||||
};
|
||||
|
||||
#define PD_IDX_MIN 0
|
||||
#define INVALID_INIT_VAL 0xff
|
||||
|
||||
#ifdef HALBB_MCC_SUPPORT
|
||||
struct halbb_mcc_dm {
|
||||
enum bb_mcc_t mcc_pre_status_en;
|
||||
u8 mcc_reg_id[NUM_MAX_REG_CNT];
|
||||
u8 sta_cnt[MR_BAND_NUM];
|
||||
u16 mcc_dm_reg[NUM_MAX_REG_CNT];
|
||||
u16 mcc_dm_mask[NUM_MAX_REG_CNT];
|
||||
u16 mcc_dm_val[NUM_MAX_REG_CNT][MR_BAND_NUM];
|
||||
/*mcc DIG*/
|
||||
u8 rssi_min[MR_BAND_NUM];
|
||||
/* need to be config by driver*/
|
||||
enum bb_mcc_t mcc_status_en;
|
||||
u8 mr_num;
|
||||
u8 softap_macid;
|
||||
struct rtw_chan_def mcc_rf_ch[MR_BAND_NUM];
|
||||
};
|
||||
/**
|
||||
* @struct _mcc_h2c_
|
||||
* @brief _mcc_h2c_
|
||||
*
|
||||
*/
|
||||
struct mcc_h2c_reg_content {
|
||||
// MCCDM
|
||||
u8 addr_lsb;
|
||||
u8 addr_msb;
|
||||
u8 bmask_lsb;
|
||||
u8 bmask_msb;
|
||||
u8 val_lsb;
|
||||
u8 val_msb;
|
||||
u8 rsvd0;
|
||||
u8 rsvd1;
|
||||
};
|
||||
|
||||
#if PLATFOM_IS_LITTLE_ENDIAN
|
||||
struct mcc_h2c {
|
||||
// MCCDM
|
||||
u8 reg_cnt;
|
||||
|
||||
u8 mcc_dm_en: 1;
|
||||
u8 mcc_idx: 2;
|
||||
u8 mcc_set: 1;
|
||||
u8 phy0_en: 1;
|
||||
u8 phy1_en: 1;
|
||||
u8 rsvd0: 2;
|
||||
|
||||
u8 center_ch;
|
||||
u8 band_type;
|
||||
struct mcc_h2c_reg_content mcc_reg_content[NUM_MAX_REG_CNT];
|
||||
};
|
||||
#else
|
||||
struct mcc_h2c {
|
||||
// MCCDM
|
||||
u8 reg_cnt;
|
||||
|
||||
u8 rsvd0: 2;
|
||||
u8 phy1_en: 1;
|
||||
u8 phy0_en: 1;
|
||||
u8 mcc_set: 1;
|
||||
u8 mcc_idx: 2;
|
||||
u8 mcc_dm_en: 1;
|
||||
|
||||
u8 center_ch;
|
||||
u8 band_type;
|
||||
struct mcc_h2c_reg_content mcc_reg_content[NUM_MAX_REG_CNT];
|
||||
};
|
||||
#endif
|
||||
#endif
|
||||
|
||||
struct bb_scan_h2c_info {
|
||||
u8 scan_mode;
|
||||
u8 op_ch_band;
|
||||
u8 op_ch;
|
||||
u8 scan_ofdm_pd;
|
||||
u8 op_ch_ofdm_pd;
|
||||
u8 op_ch_idx;
|
||||
u8 phy_idx;
|
||||
u8 scan_cck_pd;
|
||||
u8 op_ch_cck_pd;
|
||||
u8 rsvd0;
|
||||
u8 rsvd1;
|
||||
u8 rsvd2;
|
||||
};
|
||||
|
||||
struct bb_scan_c2h_rpt {
|
||||
u8 phy_idx;
|
||||
u8 band;
|
||||
u8 center_ch;
|
||||
u8 ofdm_pd_idx;
|
||||
u8 cck_pd_idx;
|
||||
u8 rsvd0;
|
||||
u8 rsvd1;
|
||||
u8 rsvd2;
|
||||
};
|
||||
|
||||
struct bb_info {
|
||||
struct rtw_phl_com_t *phl_com;
|
||||
struct rtw_hal_com_t *hal_com;
|
||||
struct rtw_phl_stainfo_t *phl_sta_info[PHL_MAX_STA_NUM];
|
||||
u16 phl2bb_macid_table[PHL_MAX_STA_NUM];
|
||||
bool sta_exist[PHL_MAX_STA_NUM];
|
||||
/*[DBCC]*/
|
||||
#ifdef HALBB_DBCC_SUPPORT
|
||||
struct bb_info *bb_phy_hooker;
|
||||
#endif
|
||||
enum phl_phy_idx bb_phy_idx;
|
||||
struct bb_cmn_info *bb_cmn_hooker;
|
||||
/*[Common Info]*/
|
||||
u32 bb0_cr_offset;
|
||||
u32 bb0_mcu_cr_offset;
|
||||
struct bb_gain_info bb_gain_i;
|
||||
struct bb_gain_gen2_info bb_gain_gen2_i;
|
||||
struct bb_efuse_info bb_efuse_i;
|
||||
enum bb_ic_t ic_type;
|
||||
enum bb_ic_sub_t ic_sub_type;
|
||||
u32 a_die_id;
|
||||
u32 a_die_cv;
|
||||
u8 a_die_num;
|
||||
enum bb_cr_t cr_type;
|
||||
enum bb_80211spec_t bb_80211spec;
|
||||
u8 num_ss; /*SS*/
|
||||
u8 num_rf_path; /*STS*/
|
||||
u8 num_tx_path; /*MAX TX PATH*/
|
||||
u16 bb_sta_cnt;
|
||||
/*[System Info]*/
|
||||
bool is_mp_mode_pre;
|
||||
enum bb_watchdog_mode_t bb_watchdog_mode;
|
||||
bool bb_cmn_info_init_ready;
|
||||
bool bb_dm_init_ready;
|
||||
u32 bb_sys_up_time;
|
||||
bool bb_watchdog_en;
|
||||
u8 bb_watchdog_period; /*2s, 4s, 8s...,254s*/
|
||||
bool bb_ic_api_en;
|
||||
u8 pre_dbg_priority;
|
||||
char dbg_buf[HALBB_SNPRINT_SIZE];
|
||||
/*[DM Info]*/
|
||||
bool is_noisy;
|
||||
bool adv_bb_dm_en;
|
||||
u64 support_ability; /*HALBB function Supportability*/
|
||||
u64 manual_support_ability;
|
||||
u32 pause_ability; /*HALBB function pause Supportability*/
|
||||
struct halbb_pause_lv pause_lv_table;
|
||||
/*[FW Info]*/
|
||||
u8 fwofld_last_cmd;
|
||||
u64 fw_dbg_component;
|
||||
/*[Drv Dbg Info]*/
|
||||
u64 dbg_component;
|
||||
u64 mcu_dbg_component;
|
||||
u8 cmn_dbg_msg_period;
|
||||
u16 cmn_dbg_msg_component;
|
||||
u8 cmn_dbg_msg_cnt;
|
||||
bool is_disable_phy_api;
|
||||
/*[Dummy]*/
|
||||
bool bool_dummy;
|
||||
u8 u8_dummy;
|
||||
u16 u16_dummy;
|
||||
u32 u32_dummy;
|
||||
/*[Link Info]*/
|
||||
enum rf_path tx_path; /*PMAC Tx Path*/
|
||||
enum rf_path rx_path;
|
||||
/*[pmac]*/
|
||||
bool dyn_pmac_tri_en;
|
||||
bool pmac_tri_en;
|
||||
bool pwr_comp_en;
|
||||
u32 pmac_tri_idx;
|
||||
u32 pmac_pwr_ofst;
|
||||
/*[btc]*/
|
||||
bool bt_en; /*bt_en=1 when is_share_ant=0 and is_2g, backup for ch_bw switch*/
|
||||
/*[Ch_Trk WR]*/
|
||||
bool pre_ch_trk_state;
|
||||
/*[npath enable]*/
|
||||
bool npath_en;
|
||||
|
||||
/*@=== [HALBB Structure] ============================================*/
|
||||
struct bb_hw_cfg_info bb_hw_cfg_i;
|
||||
#ifdef BB_8852A_2_SUPPORT
|
||||
struct bb_8852a_2_info bb_8852a_2_i;
|
||||
struct bb_h2c_fw_cmw bb_fw_cmw_i;
|
||||
struct vht_mu_cr_backup_table vht_mu_backup_val;
|
||||
#endif
|
||||
#ifdef HALBB_DBCC_SUPPORT
|
||||
struct bb_dbcc_info bb_dbcc_i;
|
||||
#endif
|
||||
#ifdef HALBB_ENV_MNTR_SUPPORT
|
||||
struct bb_env_mntr_info bb_env_mntr_i;
|
||||
#endif
|
||||
#ifdef HALBB_EDCCA_SUPPORT
|
||||
struct bb_edcca_info bb_edcca_i;
|
||||
#endif
|
||||
#ifdef HALBB_DFS_SUPPORT
|
||||
struct bb_dfs_info bb_dfs_i;
|
||||
#endif
|
||||
#ifdef HALBB_STATISTICS_SUPPORT
|
||||
struct bb_stat_info bb_stat_i;
|
||||
#endif
|
||||
#ifdef HALBB_DIG_SUPPORT
|
||||
struct bb_dig_info bb_dig_i;
|
||||
#endif
|
||||
#ifdef HALBB_CFO_TRK_SUPPORT
|
||||
struct bb_cfo_trk_info bb_cfo_trk_i;
|
||||
#endif
|
||||
#ifdef HALBB_UL_TB_CTRL_SUPPORT
|
||||
struct bb_ul_tb_info bb_ul_tb_i;
|
||||
#endif
|
||||
#ifdef HALBB_PHYSTS_PARSING_SUPPORT
|
||||
struct bb_physts_info bb_physts_i;
|
||||
struct bb_rxd_info bb_rxd_i;
|
||||
#endif
|
||||
#ifdef HALBB_LA_MODE_SUPPORT
|
||||
struct bb_la_mode_info bb_la_mode_i;
|
||||
#endif
|
||||
|
||||
#ifdef HALBB_PWR_CTRL_SUPPORT
|
||||
struct bb_pwr_ctrl_info bb_pwr_ctrl_i;
|
||||
struct bb_dyncca_info bb_dyncca_i;
|
||||
#endif
|
||||
|
||||
#ifdef HALBB_PMAC_TX_SUPPORT
|
||||
struct bb_plcp_info bb_plcp_i;
|
||||
#endif
|
||||
struct bb_link_info bb_link_i;
|
||||
struct bb_path_info bb_path_i;
|
||||
struct bb_ch_info bb_ch_i;
|
||||
struct bb_api_info bb_api_i;
|
||||
struct bb_iot_info bb_iot_i;
|
||||
struct bb_dbg_info bb_dbg_i;
|
||||
struct bb_c2h_fw_tx_rpt bb_fwtx_c2h_i;
|
||||
struct bb_h2c_fw_tx_setting bb_fwtx_h2c_i;
|
||||
struct bb_h2c_fw_edcca bb_fw_edcca_i;
|
||||
struct bb_h2c_ehtsig_sigb bb_h2c_ehtsig_sigb_i;
|
||||
struct bb_fw_dbg_cmn_info bb_fwdbg_i;
|
||||
struct bb_cmn_rpt_info bb_cmn_rpt_i;
|
||||
struct bb_ra_tx_hist_c2h_rpt bb_tx_hist_rpt_i;
|
||||
struct rxevm_physts rxevm;
|
||||
struct bb_cmn_backup_info bb_cmn_backup_i;
|
||||
struct bb_spur_info bb_spur_i;
|
||||
#ifdef HALBB_CH_INFO_SUPPORT
|
||||
struct bb_ch_rpt_info bb_ch_rpt_i;
|
||||
#endif
|
||||
#ifdef HALBB_AUTO_DBG_SUPPORT
|
||||
struct bb_auto_dbg_info bb_auto_dbg_i;
|
||||
#endif
|
||||
#ifdef HALBB_ANT_DIV_SUPPORT
|
||||
struct bb_antdiv_info bb_ant_div_i;
|
||||
#endif
|
||||
#ifdef HALBB_DYN_L2H_SUPPORT
|
||||
struct bb_dyn_l2h_info bb_dyn_l2h_i;
|
||||
#endif
|
||||
#ifdef HALBB_PATH_DIV_SUPPORT
|
||||
struct bb_pathdiv_info bb_path_div_i;
|
||||
#endif
|
||||
#ifdef HALBB_SR_SUPPORT
|
||||
struct bb_spatial_reuse_info bb_sr_i;
|
||||
#endif
|
||||
/*@=== [HALBB Timer] ================================================*/
|
||||
#ifdef HALBB_RUA_SUPPORT
|
||||
/*struct rtw_rua_tbl rtw_rua_t;*/
|
||||
#endif
|
||||
#ifdef HALBB_MCC_SUPPORT
|
||||
struct halbb_mcc_dm mcc_dm;
|
||||
#endif
|
||||
#ifdef HALBB_DYN_1R_CCA_SUPPORT
|
||||
struct bb_dyn_1r_cca_info bb_dyn_1r_cca_i;
|
||||
#endif
|
||||
#ifdef HALBB_DYN_DTR_SUPPORT
|
||||
struct bb_dyn_dtr_info bb_dyn_dtr_i;
|
||||
#endif
|
||||
#ifdef HALBB_FW_OFLD_SUPPORT
|
||||
enum phl_msg_evt_id bb_phl_evt;
|
||||
#endif
|
||||
#ifdef HALBB_DV_PXP_DBG_SUPPORT
|
||||
struct bb_dv_pxp_dbg_info bb_dv_pxp_dbg_i;
|
||||
#endif
|
||||
struct halbb_plcp_info plcp_in;
|
||||
struct halbb_pmac_info pmac_in;
|
||||
struct halbb_lbk_info bb_lbk_i;
|
||||
struct bb_scan_h2c_info bb_scan_h2c_i;
|
||||
};
|
||||
|
||||
|
||||
/*@--------------------------[Prptotype]-------------------------------------*/
|
||||
u8 halbb_get_rssi_min(struct bb_info *bb);
|
||||
void halbb_cmn_info_self_reset(struct bb_info *bb);
|
||||
void halbb_sta_info_dbg(struct bb_info *bb, char input[][16], u32 *_used,
|
||||
char *output, u32 *_out_len);
|
||||
void halbb_supportability_dbg(struct bb_info *bb, char input[][16], u32 *_used,
|
||||
char *output, u32 *_out_len);
|
||||
void halbb_pause_func_init(struct bb_info *bb);
|
||||
void halbb_pause_func_dbg(struct bb_info *bb, char input[][16], u32 *_used,
|
||||
char *output, u32 *_out_len);
|
||||
void halbb_store_data(struct bb_info *bb);
|
||||
u32 halbb_scan_ofld_c2h(struct bb_info *bb_0, u16 len, u8 *c2h);
|
||||
#endif
|
||||
@@ -0,0 +1,516 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2020 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in the
|
||||
* file called LICENSE.
|
||||
*
|
||||
* Contact Information:
|
||||
* wlanfae <wlanfae@realtek.com>
|
||||
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
|
||||
* Hsinchu 300, Taiwan.
|
||||
*
|
||||
* Larry Finger <Larry.Finger@lwfinger.net>
|
||||
*
|
||||
*****************************************************************************/
|
||||
#include "../halbb_precomp.h"
|
||||
|
||||
#ifdef BB_8852B_SUPPORT
|
||||
|
||||
bool halbb_chk_pkg_valid_8852b(struct bb_info *bb, u8 bb_ver, u8 rf_ver)
|
||||
{
|
||||
bool valid = true;
|
||||
|
||||
#if 0
|
||||
if (bb_ver >= X && rf_ver >= Y)
|
||||
valid = true;
|
||||
else if (bb_ver < X && rf_ver < Y)
|
||||
valid = true;
|
||||
else
|
||||
valid = false;
|
||||
#endif
|
||||
|
||||
if (!valid) {
|
||||
/*halbb_set_reg(bb, 0x1c3c, (BIT(0) | BIT(1)), 0x0);*/
|
||||
BB_WARNING("[%s] Pkg_ver{bb, rf}={%d, %d} disable all BB block\n",
|
||||
__func__, bb_ver, rf_ver);
|
||||
}
|
||||
|
||||
return valid;
|
||||
}
|
||||
|
||||
bool halbb_chk_tx_idle_8852b(struct bb_info *bb, enum phl_phy_idx phy_idx)
|
||||
{
|
||||
u8 tx_state = 0;
|
||||
bool idle = false;
|
||||
u32 dbg_port = 0x30002;
|
||||
|
||||
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
|
||||
|
||||
if (phy_idx == HW_PHY_1)
|
||||
return false;
|
||||
|
||||
if (halbb_bb_dbg_port_racing(bb, DBGPORT_PRI_3)) {
|
||||
halbb_dbg_port_sel(bb, (u16)(dbg_port & 0xffff),
|
||||
(u8)((dbg_port & 0xff0000) >> 16), 0x0, 0x1);
|
||||
BB_DBG(bb, DBG_PHY_CONFIG,
|
||||
"*Set dbg_port=(0x%x)\n", dbg_port);
|
||||
} else {
|
||||
dbg_port = halbb_get_bb_dbg_port_idx(bb);
|
||||
BB_DBG(bb, DBG_PHY_CONFIG,
|
||||
"[Set dbg_port fail!] Curr-DbgPort=0x%x\n", dbg_port);
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
/* Release DBG port */
|
||||
halbb_release_bb_dbg_port(bb);
|
||||
|
||||
tx_state = (u8)(halbb_get_bb_dbg_port_val(bb) & 0x3f);
|
||||
|
||||
if (tx_state == 0)
|
||||
idle = true;
|
||||
else
|
||||
idle = false;
|
||||
|
||||
return idle;
|
||||
}
|
||||
|
||||
void halbb_stop_pmac_tx_8852b(struct bb_info *bb,
|
||||
struct halbb_pmac_info *tx_info,
|
||||
enum phl_phy_idx phy_idx)
|
||||
{
|
||||
if (tx_info->is_cck) { // CCK
|
||||
if (tx_info->mode == CONT_TX) {
|
||||
halbb_set_reg(bb, 0x2300, BIT(26), 1);
|
||||
halbb_set_reg(bb, 0x2338, BIT(17), 0);
|
||||
halbb_set_reg(bb, 0x2300, BIT(28), 0);
|
||||
halbb_set_reg(bb, 0x2300, BIT(26), 0);
|
||||
} else if (tx_info->mode == PKTS_TX) {
|
||||
halbb_set_reg_cmn(bb, 0x9c4, BIT(4), 0, phy_idx);
|
||||
}
|
||||
} else { // OFDM
|
||||
if (tx_info->mode == CONT_TX)
|
||||
halbb_set_reg_cmn(bb, 0x9c4, BIT(0), 0, phy_idx);
|
||||
else if (tx_info->mode == PKTS_TX)
|
||||
halbb_set_reg_cmn(bb, 0x9c4, BIT(4), 0, phy_idx);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void halbb_start_pmac_tx_8852b(struct bb_info *bb,
|
||||
struct halbb_pmac_info *tx_info,
|
||||
enum halbb_pmac_mode mode, u32 pkt_cnt,u16 period,
|
||||
enum phl_phy_idx phy_idx)
|
||||
{
|
||||
if (mode == CONT_TX) {
|
||||
if (tx_info->is_cck) {
|
||||
halbb_set_reg(bb, 0x2338, BIT(17), 1);
|
||||
halbb_set_reg(bb, 0x2300, BIT(28), 0);
|
||||
} else {
|
||||
halbb_set_reg_cmn(bb, 0x9c4, BIT(0), 1, phy_idx);
|
||||
}
|
||||
} else if (mode == PKTS_TX) {
|
||||
/*Tx_N_PACKET_EN */
|
||||
halbb_set_reg_cmn(bb, 0x9c4, BIT(4), 1, phy_idx);
|
||||
/*Tx_N_PERIOD */
|
||||
halbb_set_reg_cmn(bb, 0x9c4, 0xffffff00, period, phy_idx);
|
||||
/*Tx_N_PACKET */
|
||||
halbb_set_reg_cmn(bb, 0x9c8, 0xffffffff, pkt_cnt, phy_idx);
|
||||
} else if (mode == CCK_CARRIER_SIPPRESSION_TX) {
|
||||
if (tx_info->is_cck) {
|
||||
/*Carrier Suppress Tx*/
|
||||
halbb_set_reg(bb, 0x2338, BIT(18), 1);
|
||||
/*Disable scrambler at payload part*/
|
||||
halbb_set_reg(bb, 0x2304, BIT(26), 1);
|
||||
} else {
|
||||
return;
|
||||
}
|
||||
/*Tx_N_PACKET_EN */
|
||||
halbb_set_reg_cmn(bb, 0x9c4, BIT(4), 1, phy_idx);
|
||||
/*Tx_N_PERIOD */
|
||||
halbb_set_reg_cmn(bb, 0x9c4, 0xffffff00, period, phy_idx);
|
||||
/*Tx_N_PACKET */
|
||||
halbb_set_reg_cmn(bb, 0x9c8, 0xffffffff, pkt_cnt, phy_idx);
|
||||
}
|
||||
/*Tx_EN */
|
||||
halbb_set_reg_cmn(bb, 0x9c0, BIT(0), 1, phy_idx);
|
||||
halbb_set_reg_cmn(bb, 0x9c0, BIT(0), 0, phy_idx);
|
||||
}
|
||||
|
||||
|
||||
void halbb_set_pmac_tx_8852b(struct bb_info *bb, struct halbb_pmac_info *tx_info,
|
||||
enum phl_phy_idx phy_idx)
|
||||
{
|
||||
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
|
||||
|
||||
if (!tx_info->en_pmac_tx) {
|
||||
halbb_stop_pmac_tx_8852b(bb, tx_info, phy_idx);
|
||||
/* PD hit enable */
|
||||
halbb_set_reg_cmn(bb, 0xc3c, BIT(9), 0, phy_idx);
|
||||
halbb_set_reg(bb, 0x2344, BIT(31), 0);
|
||||
return;
|
||||
}
|
||||
/*Turn on PMAC */
|
||||
/* Tx */
|
||||
halbb_set_reg_cmn(bb, 0x0980, BIT(0), 1, phy_idx);
|
||||
/* Rx */
|
||||
halbb_set_reg_cmn(bb, 0x0980, BIT(16), 1, phy_idx);
|
||||
halbb_set_reg_cmn(bb, 0x0988, 0x3f, 0x3f, phy_idx);
|
||||
|
||||
/* PD hit enable */
|
||||
halbb_set_reg_cmn(bb, 0xc3c, BIT(9), 1, phy_idx);
|
||||
halbb_set_reg(bb, 0x2344, BIT(31), 1);
|
||||
|
||||
/*Protest SW-SI */
|
||||
halbb_set_reg(bb, 0x1200, 0x70000000, 0x7);
|
||||
halbb_set_reg(bb, 0x3200, 0x70000000, 0x7);
|
||||
halbb_delay_us(bb, 1);
|
||||
|
||||
/*BB reset*/
|
||||
halbb_set_reg(bb, 0x704, BIT(1), 0x0);
|
||||
halbb_set_reg(bb, 0x1200, 0x70000000, 0x0);
|
||||
halbb_set_reg(bb, 0x3200, 0x70000000, 0x0);
|
||||
halbb_set_reg(bb, 0x704, BIT(1), 0x1);
|
||||
|
||||
//halbb_bb_reset_all_8852b(bb, HW_PHY_0);
|
||||
|
||||
halbb_start_pmac_tx_8852b(bb, tx_info, tx_info->mode, tx_info->tx_cnt,
|
||||
tx_info->period, phy_idx);
|
||||
}
|
||||
|
||||
void halbb_set_tmac_tx_8852b(struct bb_info *bb, enum phl_phy_idx phy_idx)
|
||||
{
|
||||
/* To do: 0x0d80[16] [25] / 0x0d88[5:0] Should be set to default value in parameter package*/
|
||||
/* Turn on TMAC */
|
||||
halbb_set_reg_cmn(bb, 0x0980, BIT(0), 0, phy_idx);
|
||||
halbb_set_reg_cmn(bb, 0x0980, BIT(16), 0, phy_idx);
|
||||
halbb_set_reg_cmn(bb, 0x0988, 0xfff, 0, phy_idx);
|
||||
halbb_set_reg_cmn(bb, 0x0994, 0xf0, 0, phy_idx);
|
||||
|
||||
// PDP bypass from TMAC
|
||||
halbb_set_reg_cmn(bb, 0x09a4, BIT(10), 0, phy_idx);
|
||||
// TMAC Tx path
|
||||
halbb_set_reg_cmn(bb, 0x09a4, 0x1c, 0, phy_idx);
|
||||
// TMAC Tx power
|
||||
halbb_set_reg_cmn(bb, 0x09a4, BIT(16), 0, phy_idx);
|
||||
}
|
||||
|
||||
void halbb_ic_hw_setting_init_8852b(struct bb_info *bb)
|
||||
{
|
||||
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
|
||||
|
||||
if(phl_is_mp_mode(bb->phl_com)) {
|
||||
// r_en_sound_wo_ndp
|
||||
halbb_set_reg(bb, 0xd7c, BIT(1), 1);
|
||||
halbb_set_reg(bb, 0x2d7c, BIT(1), 1);
|
||||
} else {
|
||||
// r_en_sound_wo_ndp
|
||||
halbb_set_reg(bb, 0xd7c, BIT(1), 0);
|
||||
halbb_set_reg(bb, 0x2d7c, BIT(1), 0);
|
||||
}
|
||||
|
||||
if (bb->hal_com->cv != CAV) {
|
||||
//set minimum UL txpwr requirement to -10dBm
|
||||
halbb_write_mask_pwr_reg_cmn(bb, HW_PHY_0, 0xd240, 0x3fe00, 0x1d8);
|
||||
halbb_write_mask_pwr_reg_cmn(bb, HW_PHY_1, 0xd240, 0x3fe00, 0x1d8);
|
||||
//set UL txpwr compensation to 0dB
|
||||
halbb_write_mask_pwr_reg_cmn(bb, HW_PHY_0, 0xd290, 0x1f, 0);
|
||||
halbb_write_mask_pwr_reg_cmn(bb, HW_PHY_1, 0xd290, 0x1f, 0);
|
||||
}
|
||||
}
|
||||
|
||||
void halbb_ic_hw_setting_8852b(struct bb_info *bb)
|
||||
{
|
||||
bool btg_en;
|
||||
struct bb_env_mntr_info *env = &bb->bb_env_mntr_i;
|
||||
struct bb_link_info *link = &bb->bb_link_i;
|
||||
struct rtw_phl_stainfo_t *sta = NULL;
|
||||
struct rtw_rssi_info *sta_rssi = NULL;
|
||||
#ifdef HALBB_STATISTICS_SUPPORT
|
||||
u32 cnt_diff = 0;
|
||||
struct bb_stat_info *stat = &bb->bb_stat_i;
|
||||
struct bb_cca_info *cca = &stat->bb_cca_i;
|
||||
struct bb_fa_info *fa = &stat->bb_fa_i;
|
||||
#endif
|
||||
u16 rssi_a = 0;
|
||||
u16 rssi_b = 0;
|
||||
u16 rssi_path_diff = 0;
|
||||
u32 id = bb->phl_com->id.id & 0xFFFF;
|
||||
|
||||
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
|
||||
|
||||
if (!link->is_linked)
|
||||
return;
|
||||
|
||||
if (!link->is_one_entry_only)
|
||||
return;
|
||||
|
||||
sta = bb->phl_sta_info[link->one_entry_macid];
|
||||
sta_rssi = &sta->hal_sta->rssi_stat;
|
||||
rssi_a = sta_rssi->rssi_ma_path[0];
|
||||
rssi_b = sta_rssi->rssi_ma_path[1];
|
||||
rssi_path_diff = DIFF_2(rssi_a, rssi_b) >> 5;
|
||||
|
||||
btg_en = (bb->hal_com->band[0].cur_chandef.band == BAND_ON_24G) &&
|
||||
((bb->rx_path == RF_PATH_B) || (bb->rx_path == RF_PATH_AB)) ? true : false;
|
||||
|
||||
if (btg_en && bb->bb_link_i.is_linked && (bb->bb_ch_i.rssi_min < (75 << 1))) {// if rssi < -35 dbm
|
||||
halbb_set_reg(bb, 0x4aa4, BIT(18), 0x0);
|
||||
BB_DBG(bb, DBG_PHY_CONFIG, "[BT] BTG enable, Is linked\n");
|
||||
BB_DBG(bb, DBG_PHY_CONFIG, "[BT][RSSI] rssi_min=0x%x\n", bb->bb_ch_i.rssi_min >> 1);
|
||||
} else {
|
||||
halbb_set_reg(bb, 0x4aa4, BIT(18), 0x1);
|
||||
BB_DBG(bb, DBG_PHY_CONFIG, "[BT] btg_en=%d, is_linked=%d\n", btg_en, bb->bb_link_i.is_linked);
|
||||
BB_DBG(bb, DBG_PHY_CONFIG, "[BT][RSSI] rssi_min=0x%x\n", bb->bb_ch_i.rssi_min >> 1);
|
||||
}
|
||||
|
||||
// for wrc
|
||||
if ((bb->hal_com->band[0].cur_chandef.band == BAND_ON_5G) && (id == 0x112))
|
||||
halbb_set_reg(bb, 0x4408, BIT(25), 0x1);
|
||||
else
|
||||
halbb_set_reg(bb, 0x4408, BIT(25), 0x0);
|
||||
|
||||
if (rssi_path_diff > 15) {
|
||||
halbb_set_reg(bb, 0x4964, BIT(31), 0);
|
||||
BB_DBG(bb, DBG_PHY_CONFIG,
|
||||
"rssi(a,b)=(%d,%d),rssi_diff=(%d),ant_wgt_normalize_mode_OFF\n",
|
||||
rssi_a, rssi_b, rssi_path_diff);
|
||||
} else {
|
||||
halbb_set_reg(bb, 0x4964, BIT(31), 1);
|
||||
BB_DBG(bb, DBG_PHY_CONFIG,
|
||||
"rssi(a,b)=(%d,%d),rssi_diff=(%d),ant_wgt_normalize_mode_ON\n",
|
||||
rssi_a, rssi_b, rssi_path_diff);
|
||||
}
|
||||
#ifdef HALBB_STATISTICS_SUPPORT
|
||||
cnt_diff = cca->cnt_ofdm_cca - fa->cnt_ofdm_fail;
|
||||
#endif
|
||||
// dynamic setting for anti-interference
|
||||
/* if (env->nhm_ratio > 20) {
|
||||
halbb_set_reg(bb, 0x46F8, 0xffffffff, 0x13c6);
|
||||
halbb_set_reg(bb, 0x4440, BIT(31), 0x1);
|
||||
}
|
||||
*/
|
||||
}
|
||||
|
||||
bool halbb_set_pd_lower_bound_8852b(struct bb_info *bb, u8 bound,
|
||||
enum channel_width bw,
|
||||
enum phl_phy_idx phy_idx)
|
||||
{
|
||||
/*
|
||||
Range of bound value:
|
||||
BW20: 95~33
|
||||
BW40: 92~30
|
||||
BW80: 89~27
|
||||
*/
|
||||
#ifdef HALBB_DIG_TDMA_SUPPORT
|
||||
struct bb_dig_info *bb_dig = &bb->bb_dig_i;
|
||||
struct bb_dig_op_unit *bb_dig_u = bb_dig->p_cur_dig_unit;
|
||||
#endif
|
||||
u8 bw_attenuation = 0;
|
||||
u8 subband_filter_atteniation = 7;
|
||||
u8 bound_idx = 0;
|
||||
bool rpt = true;
|
||||
|
||||
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
|
||||
|
||||
if (bound == 0) {
|
||||
halbb_set_reg_cmn(bb, 0x4860, BIT(30), 0, phy_idx);
|
||||
BB_DBG(bb, DBG_PHY_CONFIG,
|
||||
"[PD Bound] Set Boundary to default!\n");
|
||||
return true;
|
||||
}
|
||||
|
||||
bb->bb_cmn_backup_i.cur_pd_lower_bound = bound;
|
||||
|
||||
if ((bw == CHANNEL_WIDTH_20) || (bw == CHANNEL_WIDTH_10) || (bw == CHANNEL_WIDTH_5)) {
|
||||
bw_attenuation = 0;
|
||||
} else if (bw == CHANNEL_WIDTH_40) {
|
||||
bw_attenuation = 3;
|
||||
} else if (bw == CHANNEL_WIDTH_80) {
|
||||
bw_attenuation = 6;
|
||||
} else {
|
||||
BB_DBG(bb, DBG_PHY_CONFIG,
|
||||
"[PD Bound] Only support BW20/40/80 !\n");
|
||||
return false;
|
||||
}
|
||||
|
||||
bound += (bw_attenuation + subband_filter_atteniation);
|
||||
// If Boundary dbm is odd, set it to even number
|
||||
bound = bound % 2 ? bound + 1 : bound;
|
||||
|
||||
if (bound < 40) {
|
||||
BB_DBG(bb, DBG_PHY_CONFIG,
|
||||
"[PD Bound] Threshold too high, set to highest level!\n");
|
||||
bound = 40;
|
||||
rpt = false;
|
||||
}
|
||||
|
||||
if (bound > 102) {
|
||||
BB_DBG(bb, DBG_PHY_CONFIG,
|
||||
"[PD Bound] Threshold too low, disable PD lower bound function!\n");
|
||||
halbb_set_reg_cmn(bb, 0x4860, BIT(30), 0, phy_idx);
|
||||
return true;
|
||||
}
|
||||
|
||||
bound_idx = (102 - bound) >> 1;
|
||||
|
||||
halbb_set_reg_cmn(bb, 0x4860, 0x7c0, bound_idx, phy_idx);
|
||||
halbb_set_reg_cmn(bb, 0x4860, BIT(30), 1, phy_idx);
|
||||
|
||||
BB_DBG(bb, DBG_PHY_CONFIG, "[PD Bound] Set Boundary Success!\n");
|
||||
|
||||
#ifdef HALBB_DIG_TDMA_SUPPORT
|
||||
if ((bb_dig->dig_mode != DIG_TDMA) && (bb_dig->dig_mode != DIG_TDMA_ADV))
|
||||
return rpt;
|
||||
|
||||
if (bb_dig_u->state_identifier == DIG_TDMA_LOW)
|
||||
bb_dig->dig_state_l_i.pd_low_th = bound;
|
||||
else
|
||||
bb_dig->dig_state_h_i.pd_low_th = bound;
|
||||
#endif
|
||||
|
||||
return rpt;
|
||||
}
|
||||
|
||||
bool halbb_set_pd_lower_bound_cck_8852b(struct bb_info *bb, u8 bound,
|
||||
enum channel_width bw,
|
||||
enum phl_phy_idx phy_idx)
|
||||
{
|
||||
#ifdef HALBB_DIG_TDMA_SUPPORT
|
||||
struct bb_dig_info *bb_dig = &bb->bb_dig_i;
|
||||
struct bb_dig_op_unit *bb_dig_u = bb_dig->p_cur_dig_unit;
|
||||
#endif
|
||||
u8 bw_attenuation = 0;
|
||||
u8 subband_filter_atteniation = 5;
|
||||
s8 bound_tmp = 0;
|
||||
|
||||
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
|
||||
|
||||
if (bb->hal_com->cv < CBV) {
|
||||
BB_DBG(bb, DBG_PHY_CONFIG, "[PD Bound] CCK pd_lower_bound CV not support!\n");
|
||||
return false;
|
||||
}
|
||||
|
||||
if (bound == 0) {
|
||||
halbb_set_reg_cmn(bb, 0x23b0, BIT(23), 0, phy_idx);
|
||||
BB_DBG(bb, DBG_PHY_CONFIG,
|
||||
"[PD Bound] Set Boundary to default!\n");
|
||||
return true;
|
||||
}
|
||||
|
||||
if ((bw == CHANNEL_WIDTH_20) || (bw == CHANNEL_WIDTH_10) || (bw == CHANNEL_WIDTH_5)) {
|
||||
bw_attenuation = 0;
|
||||
}
|
||||
else if (bw == CHANNEL_WIDTH_40) {
|
||||
bw_attenuation = 3;
|
||||
}
|
||||
else if (bw == CHANNEL_WIDTH_80) {
|
||||
bw_attenuation = 6;
|
||||
}
|
||||
else {
|
||||
BB_DBG(bb, DBG_PHY_CONFIG,
|
||||
"[PD Bound] Only support BW20/40/80 !\n");
|
||||
return true;
|
||||
}
|
||||
|
||||
bound += (bw_attenuation + subband_filter_atteniation);
|
||||
bound_tmp = (-1) * MIN_2(bound, 128);
|
||||
|
||||
halbb_set_reg_cmn(bb, 0x23b0, 0xff000000, bound_tmp, phy_idx);
|
||||
halbb_set_reg_cmn(bb, 0x23b4, 0xff000000, 0x7f, phy_idx);
|
||||
halbb_set_reg_cmn(bb, 0x23b0, BIT(23), 1, phy_idx);
|
||||
|
||||
BB_DBG(bb, DBG_PHY_CONFIG, "[PD Bound] Set CCK Boundary Success!\n");
|
||||
|
||||
#ifdef HALBB_DIG_TDMA_SUPPORT
|
||||
if ((bb_dig->dig_mode != DIG_TDMA) && (bb_dig->dig_mode != DIG_TDMA_ADV))
|
||||
return true;
|
||||
|
||||
if (bb_dig_u->state_identifier == DIG_TDMA_LOW)
|
||||
bb_dig->dig_state_l_i.rssi_nocca_low_th= bound_tmp;
|
||||
else
|
||||
bb_dig->dig_state_h_i.rssi_nocca_low_th = bound_tmp;
|
||||
#endif
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
u8 halbb_querry_pd_lower_bound_8852b(struct bb_info *bb, bool get_en_info, enum phl_phy_idx phy_idx)
|
||||
{
|
||||
u8 tmp;
|
||||
|
||||
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
|
||||
|
||||
if (get_en_info)
|
||||
tmp = (u8)halbb_get_reg_cmn(bb, 0x4860, BIT(30), phy_idx);
|
||||
else
|
||||
tmp = bb->bb_cmn_backup_i.cur_pd_lower_bound;
|
||||
|
||||
return tmp;
|
||||
}
|
||||
|
||||
void halbb_pop_en_8852b(struct bb_info *bb, bool en, enum phl_phy_idx phy_idx)
|
||||
{
|
||||
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
|
||||
|
||||
if (en) {
|
||||
halbb_set_reg_cmn(bb, 0x47D4, BIT(8), 1, phy_idx);
|
||||
|
||||
} else {
|
||||
halbb_set_reg_cmn(bb, 0x47D4, BIT(8), 0, phy_idx);
|
||||
}
|
||||
}
|
||||
|
||||
bool halbb_querry_pop_en_8852b(struct bb_info *bb, enum phl_phy_idx phy_idx)
|
||||
{
|
||||
bool en;
|
||||
|
||||
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
|
||||
|
||||
en = (bool)halbb_get_reg_cmn(bb, 0x47D4, BIT(8), phy_idx);
|
||||
|
||||
return en;
|
||||
}
|
||||
|
||||
void halbb_dyn_mu_bypass_vht_sigb_8852b(struct bb_info *bb)
|
||||
{
|
||||
struct bb_cmn_rpt_info *cmn_rpt = &bb->bb_cmn_rpt_i;
|
||||
struct bb_pkt_cnt_mu_info *pkt_cnt = &cmn_rpt->bb_pkt_cnt_mu_i;
|
||||
u8 offset = 0;
|
||||
u32 vht_mu_pkt_th = 10;
|
||||
u32 vht_mu_pkt = 0;
|
||||
|
||||
for (offset = 0; offset < VHT_RATE_NUM; offset++) {
|
||||
vht_mu_pkt += pkt_cnt->pkt_cnt_vht[offset];
|
||||
}
|
||||
if (vht_mu_pkt > vht_mu_pkt_th) {
|
||||
halbb_set_reg(bb, 0x4414, BIT(5), 1); // loop filter bandwidth selection slicer for 1st step to 2nd step
|
||||
halbb_set_reg(bb, 0x4400, 0x07000000, 0x3); // channel tracking coefficients selection slicer for 1st step to 2nd step
|
||||
halbb_set_reg(bb, 0x4404, 0x000f8000, 0x1f); // data tracking loop filter bandwidth selection for 2nd step
|
||||
halbb_set_reg(bb, 0x4404, 0x0000001f, 0x4); // channel tracking coefficients selection slicer for 2nd step to 3rd step
|
||||
halbb_set_reg(bb, 0x43f8, 0x00fc0000, 0x0); // channel tracking coefficients for 2nd step
|
||||
halbb_set_reg(bb, 0x440c, 0x000f8000, 0x1f); // pilot tracking loop filter bandwidth selection for 2nd step
|
||||
halbb_set_reg(bb, 0x43f8, BIT(30), 0); // enable noise variance tracking
|
||||
} else {
|
||||
halbb_set_reg(bb, 0x4414, BIT(5), 0); // loop filter bandwidth selection slicer for 1st step to 2nd step
|
||||
halbb_set_reg(bb, 0x4400, 0x07000000, 0x4); // channel tracking coefficients selection slicer for 1st step to 2nd step
|
||||
halbb_set_reg(bb, 0x4404, 0x000f8000, 0x1); // data tracking loop filter bandwidth selection for 2nd step
|
||||
halbb_set_reg(bb, 0x4404, 0x0000001f, 0x8); // channel tracking coefficients selection slicer for 2nd step to 3rd step
|
||||
halbb_set_reg(bb, 0x43f8, 0x00fc0000, 0x4); // channel tracking coefficients for 2nd step
|
||||
halbb_set_reg(bb, 0x440c, 0x000f8000, 0x1); // pilot tracking loop filter bandwidth selection for 2nd step
|
||||
halbb_set_reg(bb, 0x43fc, BIT(30), 1); // enable noise variance tracking
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,54 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2020 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in the
|
||||
* file called LICENSE.
|
||||
*
|
||||
* Contact Information:
|
||||
* wlanfae <wlanfae@realtek.com>
|
||||
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
|
||||
* Hsinchu 300, Taiwan.
|
||||
*
|
||||
* Larry Finger <Larry.Finger@lwfinger.net>
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __HALBB_8852B_H__
|
||||
#define __HALBB_8852B_H__
|
||||
#ifdef BB_8852B_SUPPORT
|
||||
|
||||
#include "../halbb_pmac_setting_ex.h"
|
||||
|
||||
struct bb_info;
|
||||
|
||||
bool halbb_chk_pkg_valid_8852b(struct bb_info *bb, u8 bb_ver, u8 rf_ver);
|
||||
void halbb_set_pmac_tx_8852b(struct bb_info *bb, struct halbb_pmac_info *tx_info,
|
||||
enum phl_phy_idx phy_idx);
|
||||
|
||||
void halbb_set_tmac_tx_8852b(struct bb_info *bb, enum phl_phy_idx phy_idx);
|
||||
void halbb_ic_hw_setting_init_8852b(struct bb_info *bb);
|
||||
void halbb_ic_hw_setting_8852b(struct bb_info *bb);
|
||||
|
||||
bool halbb_set_pd_lower_bound_8852b(struct bb_info *bb, u8 bound,
|
||||
enum channel_width bw,
|
||||
enum phl_phy_idx phy_idx);
|
||||
bool halbb_set_pd_lower_bound_cck_8852b(struct bb_info *bb, u8 bound,
|
||||
enum channel_width bw,
|
||||
enum phl_phy_idx phy_idx);
|
||||
u8 halbb_querry_pd_lower_bound_8852b(struct bb_info *bb, bool get_en_info,
|
||||
enum phl_phy_idx phy_idx);
|
||||
void halbb_pop_en_8852b(struct bb_info *bb, bool en, enum phl_phy_idx phy_idx);
|
||||
bool halbb_querry_pop_en_8852b(struct bb_info *bb, enum phl_phy_idx phy_idx);
|
||||
void halbb_dyn_mu_bypass_vht_sigb_8852b(struct bb_info *bb);
|
||||
bool halbb_chk_tx_idle_8852b(struct bb_info *bb, enum phl_phy_idx phy_idx);
|
||||
#endif
|
||||
#endif /* __HALBB_8852b_H__ */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,270 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2020 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in the
|
||||
* file called LICENSE.
|
||||
*
|
||||
* Contact Information:
|
||||
* wlanfae <wlanfae@realtek.com>
|
||||
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
|
||||
* Hsinchu 300, Taiwan.
|
||||
*
|
||||
* Larry Finger <Larry.Finger@lwfinger.net>
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __HALBB_8852B_API_H__
|
||||
#define __HALBB_8852B_API_H__
|
||||
#ifdef BB_8852B_SUPPORT
|
||||
#ifdef HALBB_CONFIG_RUN_IN_DRV
|
||||
#include "../halbb_api.h"
|
||||
#endif
|
||||
|
||||
/*@--------------------------[Define]-------------------------------------*/
|
||||
#define INVALID_RF_DATA 0xffffffff
|
||||
#define BB_PATH_MAX_8852B 2
|
||||
#define GAIN_HIDE_EFUSE_A_2G_8852B 0x5BB
|
||||
#define GAIN_HIDE_EFUSE_A_5GL_8852B 0x5BA
|
||||
#define GAIN_HIDE_EFUSE_A_5GM_8852B 0x5B9
|
||||
#define GAIN_HIDE_EFUSE_A_5GH_8852B 0x5B8
|
||||
#define GAIN_HIDE_EFUSE_B_2G_8852B 0x590
|
||||
#define GAIN_HIDE_EFUSE_B_5GL_8852B 0x58F
|
||||
#define GAIN_HIDE_EFUSE_B_5GM_8852B 0x58E
|
||||
#define GAIN_HIDE_EFUSE_B_5GH_8852B 0x58D
|
||||
#define GAIN_HIDE_EFUSE_A_6GH_0_8852BP 0x5B7
|
||||
#define GAIN_HIDE_EFUSE_A_6GH_1_8852BP 0x5B6
|
||||
#define GAIN_HIDE_EFUSE_A_6GH_2_8852BP 0x5B5
|
||||
#define GAIN_HIDE_EFUSE_A_6GH_3_8852BP 0x5B4
|
||||
#define GAIN_HIDE_EFUSE_A_6GH_4_8852BP 0x5B3
|
||||
#define GAIN_HIDE_EFUSE_A_6GH_5_8852BP 0x5B2
|
||||
#define GAIN_HIDE_EFUSE_A_6GH_6_8852BP 0x5B1
|
||||
#define GAIN_HIDE_EFUSE_A_6GH_7_8852BP 0x5B0
|
||||
#define GAIN_HIDE_EFUSE_B_6GH_0_8852BP 0x58C
|
||||
#define GAIN_HIDE_EFUSE_B_6GH_1_8852BP 0x58B
|
||||
#define GAIN_HIDE_EFUSE_B_6GH_2_8852BP 0x58A
|
||||
#define GAIN_HIDE_EFUSE_B_6GH_3_8852BP 0x589
|
||||
#define GAIN_HIDE_EFUSE_B_6GH_4_8852BP 0x588
|
||||
#define GAIN_HIDE_EFUSE_B_6GH_5_8852BP 0x587
|
||||
#define GAIN_HIDE_EFUSE_B_6GH_6_8852BP 0x586
|
||||
#define GAIN_HIDE_EFUSE_B_6GH_7_8852BP 0x585
|
||||
|
||||
/*@--------------------------[Enum]------------------------------------------*/
|
||||
/*@--------------------------[Structure]-------------------------------------*/
|
||||
struct bb_h2c_lps_info_8852b {
|
||||
u8 central_ch;
|
||||
u8 pri_ch;
|
||||
u8 bw;
|
||||
u8 band_type;
|
||||
};
|
||||
/*@--------------------------[Prptotype]-------------------------------------*/
|
||||
struct bb_info;
|
||||
u8 halbb_ex_cn_report_8852b(struct bb_info *bb);
|
||||
|
||||
u8 halbb_ex_evm_1ss_report_8852b(struct bb_info *bb);
|
||||
u8 halbb_ex_evm_max_report_8852b(struct bb_info *bb);
|
||||
u8 halbb_ex_evm_min_report_8852b(struct bb_info *bb);
|
||||
|
||||
bool halbb_set_pwr_ul_tb_ofst_8852b(struct bb_info *bb,
|
||||
s16 pw_ofst, enum phl_phy_idx phy_idx);
|
||||
bool halbb_lps_info_8852b(struct bb_info *bb, u16 mac_id);
|
||||
bool halbb_lps_cmn_info_8852b(struct bb_info *bb);
|
||||
void halbb_digital_cfo_comp_8852b(struct bb_info *bb, s32 curr_cfo);
|
||||
|
||||
void halbb_tx_triangular_shap_cfg_8852b(struct bb_info *bb, u8 shape_idx,
|
||||
enum phl_phy_idx phy_idx);
|
||||
void halbb_tx_dfir_shap_cck_8852b(struct bb_info *bb, u8 ch, u8 shape_idx,
|
||||
enum phl_phy_idx phy_idx);
|
||||
void halbb_bb_reset_all_8852b(struct bb_info * bb, enum phl_phy_idx phy_idx);
|
||||
bool halbb_spur_location_8852b(struct bb_info *bb, u8 central_ch,
|
||||
enum channel_width bw, enum band_type band,
|
||||
u32 *intf);
|
||||
bool halbb_ctrl_bw_ch_8852b(struct bb_info *bb, u8 pri_ch, u8 central_ch,
|
||||
enum channel_width bw, enum band_type band,
|
||||
enum phl_phy_idx phy_idx);
|
||||
|
||||
bool halbb_ctrl_rx_path_8852b(struct bb_info *bb, enum rf_path rx_path);
|
||||
|
||||
bool halbb_ctrl_tx_path_pmac_8852b(struct bb_info *bb, enum rf_path tx_path);
|
||||
bool halbb_ctrl_tx_path_tmac_8852b(struct bb_info *bb, enum rf_path tx_path_1sts);
|
||||
bool halbb_ctrl_tx_path_8852b(struct bb_info *bb, enum rf_path tx_path);
|
||||
|
||||
#ifdef HALBB_CONFIG_RUN_IN_DRV
|
||||
|
||||
void halbb_gpio_ctrl_dump_8852b(struct bb_info *bb);
|
||||
|
||||
void halbb_gpio_rfm_8852b(struct bb_info *bb, enum bb_path path,
|
||||
enum bb_rfe_src_sel src, bool dis_tx_gnt_wl,
|
||||
bool active_tx_opt, bool act_bt_en, u8 rfm_output_val);
|
||||
|
||||
void halbb_gpio_trsw_table_8852b(struct bb_info *bb, enum bb_path path,
|
||||
bool path_en, bool trsw_tx,
|
||||
bool trsw_rx, bool trsw, bool trsw_b);
|
||||
|
||||
void halbb_gpio_setting_8852b(struct bb_info *bb, u8 gpio_idx,
|
||||
enum bb_path path, bool inv,
|
||||
enum bb_rfe_src_sel src);
|
||||
|
||||
void halbb_gpio_setting_all_8852b(struct bb_info *bb, u8 rfe_idx);
|
||||
|
||||
void halbb_gpio_setting_init_8852b(struct bb_info *bb);
|
||||
|
||||
void halbb_bb_reset_8852b(struct bb_info *bb, enum phl_phy_idx phy_idx);
|
||||
|
||||
void halbb_dfs_en_8852b(struct bb_info *bb, bool en);
|
||||
|
||||
void halbb_adc_en_8852b(struct bb_info *bb, bool en);
|
||||
|
||||
bool halbb_adc_cfg_8852bt(struct bb_info *bb, enum channel_width bw,
|
||||
enum rf_path path);
|
||||
|
||||
bool halbb_adc_cfg_8852bpt(struct bb_info *bb, enum channel_width bw,
|
||||
enum rf_path path);
|
||||
|
||||
void halbb_tssi_cont_en_8852b(struct bb_info *bb, bool en, enum rf_path path);
|
||||
|
||||
void halbb_bb_reset_en_8852b(struct bb_info *bb, bool en, enum phl_phy_idx phy_idx);
|
||||
|
||||
u32 halbb_read_rf_reg_8852b_a(struct bb_info *bb, enum rf_path path,
|
||||
u32 reg_addr, u32 bit_mask);
|
||||
|
||||
u32 halbb_read_rf_reg_8852b_d(struct bb_info *bb, enum rf_path path,
|
||||
u32 reg_addr, u32 bit_mask);
|
||||
|
||||
u32 halbb_read_rf_reg_8852b(struct bb_info *bb, enum rf_path path, u32 reg_addr,
|
||||
u32 bit_mask);
|
||||
|
||||
bool halbb_write_rf_reg_8852b_a(struct bb_info *bb, enum rf_path path,
|
||||
u32 reg_addr, u32 bit_mask, u32 data);
|
||||
|
||||
bool halbb_write_rf_reg_8852b_d(struct bb_info *bb, enum rf_path path,
|
||||
u32 reg_addr, u32 bit_mask, u32 data);
|
||||
|
||||
bool halbb_write_rf_reg_8852b(struct bb_info *bb, enum rf_path path, u32 reg_addr,
|
||||
u32 bit_mask, u32 data);
|
||||
|
||||
bool halbb_ctrl_bw_8852b(struct bb_info *bb, u8 pri_ch, enum channel_width bw,
|
||||
enum phl_phy_idx phy_idx);
|
||||
|
||||
bool halbb_ctrl_ch_8852b(struct bb_info *bb, u8 central_ch, enum band_type band,
|
||||
enum phl_phy_idx phy_idx);
|
||||
|
||||
void halbb_ctrl_cck_en_8852b(struct bb_info *bb, bool cck_en,
|
||||
enum phl_phy_idx phy_idx);
|
||||
|
||||
void halbb_ctrl_trx_path_8852b(struct bb_info *bb, enum rf_path tx_path,
|
||||
u8 tx_nss, enum rf_path rx_path, u8 rx_nss);
|
||||
|
||||
void halbb_tssi_bb_reset_8852b(struct bb_info *bb);
|
||||
|
||||
bool halbb_ctrl_sco_cck_8852b(struct bb_info *bb, u8 pri_ch);
|
||||
|
||||
bool halbb_bw_setting_8852b(struct bb_info *bb, enum channel_width bw,
|
||||
enum rf_path path);
|
||||
|
||||
bool halbb_ch_setting_8852b(struct bb_info *bb, u8 central_ch, enum rf_path path,
|
||||
bool *is_2g_ch);
|
||||
|
||||
void halbb_ctrl_rf_mode_8852b(struct bb_info *bb, enum phl_rf_mode mode);
|
||||
|
||||
void halbb_ctrl_rf_mode_rx_path_8852b(struct bb_info *bb, enum rf_path rx_path);
|
||||
|
||||
bool halbb_ctrl_ch2_80p80_8852b(struct bb_info *bb, u8 central_ch);
|
||||
|
||||
void halbb_ctrl_rx_cca_8852b(struct bb_info *bb, bool cca_en, enum phl_phy_idx phy_idx);
|
||||
|
||||
void halbb_ctrl_ofdm_en_8852b(struct bb_info *bb, bool ofdm_en,
|
||||
enum phl_phy_idx phy_idx);
|
||||
bool halbb_set_txpwr_dbm_8852b(struct bb_info *bb, s16 power_dbm,
|
||||
enum phl_phy_idx phy_idx);
|
||||
|
||||
void halbb_reset_bb_hw_cnt_8852b(struct bb_info *bb);
|
||||
|
||||
s16 halbb_get_txpwr_dbm_8852b(struct bb_info *bb, enum phl_phy_idx phy_idx);
|
||||
|
||||
s16 halbb_get_txinfo_txpwr_dbm_8852b(struct bb_info *bb);
|
||||
|
||||
bool halbb_set_cck_txpwr_idx_8852b(struct bb_info *bb, u16 power_idx,
|
||||
enum rf_path tx_path);
|
||||
u16 halbb_get_cck_txpwr_idx_8852b(struct bb_info *bb, enum rf_path tx_path);
|
||||
|
||||
s16 halbb_get_cck_ref_dbm_8852b(struct bb_info *bb, enum rf_path tx_path);
|
||||
|
||||
bool halbb_set_ofdm_txpwr_idx_8852b(struct bb_info *bb, u16 power_idx,
|
||||
enum rf_path tx_path);
|
||||
|
||||
u16 halbb_get_ofdm_txpwr_idx_8852b(struct bb_info *bb, enum rf_path tx_path);
|
||||
|
||||
s16 halbb_get_ofdm_ref_dbm_8852b(struct bb_info *bb, enum rf_path tx_path);
|
||||
|
||||
void halbb_backup_info_8852b(struct bb_info *bb, enum phl_phy_idx phy_idx);
|
||||
|
||||
bool halbb_cfg_lbk_8852b(struct bb_info *bb, bool lbk_en, bool is_dgt_lbk,
|
||||
enum rf_path tx_path, enum rf_path rx_path,
|
||||
enum channel_width bw, enum phl_phy_idx phy_idx);
|
||||
|
||||
bool halbb_cfg_lbk_cck_8852b(struct bb_info *bb, bool lbk_en, bool is_dgt_lbk,
|
||||
enum rf_path tx_path, enum rf_path rx_path,
|
||||
enum channel_width bw, enum phl_phy_idx phy_idx);
|
||||
|
||||
void halbb_restore_info_8852b(struct bb_info *bb, enum phl_phy_idx phy_idx);
|
||||
|
||||
void halbb_ctrl_btg_8852b(struct bb_info *bb, bool btg);
|
||||
|
||||
void halbb_ctrl_btc_preagc_8852b(struct bb_info *bb, bool bt_en);
|
||||
|
||||
bool halbb_set_txsc_8852b(struct bb_info *bb, u8 txsc, enum phl_phy_idx phy_idx);
|
||||
|
||||
bool halbb_set_bss_color_8852b(struct bb_info *bb, u8 bss_color,
|
||||
enum phl_phy_idx phy_idx);
|
||||
|
||||
bool halbb_set_sta_id_8852b(struct bb_info *bb, u16 sta_id,
|
||||
enum phl_phy_idx phy_idx);
|
||||
|
||||
void halbb_set_igi_8852b(struct bb_info *bb, u8 lna_idx, bool tia_idx,
|
||||
u8 rxbb_idx, enum rf_path path);
|
||||
void halbb_set_tx_pow_ref_8852b(struct bb_info *bb, s16 pw_dbm_ofdm,
|
||||
s16 pw_dbm_cck, s8 ofst,
|
||||
u8 base_cw_0db, u16 tssi_16dBm_cw,
|
||||
u16 *ofdm_cw, u16 *cck_cw,
|
||||
enum phl_phy_idx phy_idx);
|
||||
void halbb_dump_bb_reg_8852b(struct bb_info *bb, u32 *_used, char *output,
|
||||
u32 *_out_len, bool dump_2_buff);
|
||||
void halbb_dbgport_dump_all_8852b(struct bb_info *bb, u32 *_used, char *output,
|
||||
u32 *_out_len);
|
||||
void halbb_physts_brk_fail_pkt_rpt_8852b(struct bb_info *bb, bool enable,
|
||||
enum phl_phy_idx phy_idx);
|
||||
|
||||
bool halbb_rf_write_bb_reg_8852b(struct bb_info *bb, u32 addr, u32 mask, u32 data);
|
||||
|
||||
void halbb_pre_agc_en_8852b(struct bb_info *bb, bool enable);
|
||||
void halbb_agc_fix_gain_8852b(struct bb_info *bb, bool enable, enum rf_path path);
|
||||
void halbb_agc_tia_shrink_8852b(struct bb_info *bb, bool shrink_en,
|
||||
bool shrink_init, enum rf_path path);
|
||||
void halbb_agc_step_en_8852b(struct bb_info *bb, bool pre_pd_agc_en,
|
||||
bool linear_agc_en, bool post_pd_agc_en,
|
||||
bool nlgc_agc_en, enum rf_path path);
|
||||
void halbb_set_gain_error_8852b(struct bb_info *bb, u8 central_ch, enum band_type band_type);
|
||||
void halbb_set_efuse_8852b(struct bb_info *bb, u8 central_ch, enum phl_phy_idx phy_idx);
|
||||
void halbb_get_efuse_ofst_init_8852b(struct bb_info *bb);
|
||||
void halbb_get_normal_efuse_init_8852b(struct bb_info *bb);
|
||||
void halbb_get_hide_efuse_init_8852b(struct bb_info *bb);
|
||||
void halbb_set_rxsc_rpl_comp_8852b(struct bb_info *bb, u8 central_ch, enum band_type band_type);
|
||||
void halbb_normal_efuse_verify_8852b(struct bb_info *bb, s8 rx_gain_offset,
|
||||
enum rf_path rx_path,
|
||||
enum phl_phy_idx phy_idx);
|
||||
void halbb_normal_efuse_verify_cck_8852b(struct bb_info *bb, s8 rx_gain_offset,
|
||||
enum rf_path rx_path,
|
||||
enum phl_phy_idx phy_idx);
|
||||
void halbb_nvar_src_sel_8852b(struct bb_info *bb, bool is_BF);
|
||||
#endif
|
||||
#endif
|
||||
#endif /* __INC_PHYDM_API_H_8852A__ */
|
||||
@@ -0,0 +1,35 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2020 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in the
|
||||
* file called LICENSE.
|
||||
*
|
||||
* Contact Information:
|
||||
* wlanfae <wlanfae@realtek.com>
|
||||
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
|
||||
* Hsinchu 300, Taiwan.
|
||||
*
|
||||
* Larry Finger <Larry.Finger@lwfinger.net>
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __HALBB_8852B_API_EX_H__
|
||||
#define __HALBB_8852B_API_EX_H__
|
||||
#ifdef BB_8852B_SUPPORT
|
||||
|
||||
/*@--------------------------[Prptotype]-------------------------------------*/
|
||||
struct bb_info;
|
||||
|
||||
u16 halbb_cfg_cmac_tx_ant_8852b(struct bb_info *bb, enum rf_path tx_path);
|
||||
|
||||
#endif
|
||||
#endif /* __INC_PHYDM_API_H_8852A__ */
|
||||
@@ -0,0 +1,61 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2020 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in the
|
||||
* file called LICENSE.
|
||||
*
|
||||
* Contact Information:
|
||||
* wlanfae <wlanfae@realtek.com>
|
||||
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
|
||||
* Hsinchu 300, Taiwan.
|
||||
*
|
||||
* Larry Finger <Larry.Finger@lwfinger.net>
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __HALBB_8852B_FWOFLD_API_H__
|
||||
#define __HALBB_8852B_FWOFLD_API_H__
|
||||
#ifdef BB_8852B_SUPPORT
|
||||
#ifdef HALBB_CONFIG_RUN_IN_DRV
|
||||
#include "../halbb_api.h"
|
||||
#include "../halbb_fwofld_ex.h"
|
||||
#endif
|
||||
|
||||
|
||||
/*@--------------------------[Define] ---------------------------------------*/
|
||||
|
||||
/*@--------------------------[Enum]------------------------------------------*/
|
||||
|
||||
/*@--------------------------[Structure]-------------------------------------*/
|
||||
|
||||
|
||||
struct bb_info;
|
||||
/*@--------------------------[Prptotype]-------------------------------------*/
|
||||
#ifdef HALBB_FW_OFLD_SUPPORT
|
||||
void halbb_fwofld_bb_reset_8852b(struct bb_info *bb, enum phl_phy_idx phy_idx);
|
||||
bool halbb_fwcfg_bb_phy_8852b(struct bb_info *bb, u32 addr, u32 data,
|
||||
enum phl_phy_idx phy_idx);
|
||||
bool halbb_fwofld_ctrl_ch_8852b(struct bb_info *bb, u8 central_ch, enum band_type band,
|
||||
enum phl_phy_idx phy_idx);
|
||||
bool halbb_fwofld_ctrl_bw_ch_8852b(struct bb_info *bb, u8 pri_ch, u8 central_ch,
|
||||
enum channel_width bw, enum band_type band,
|
||||
enum phl_phy_idx phy_idx);
|
||||
void halbb_fwofld_ctrl_cck_en_8852b(struct bb_info *bb, bool cck_en,
|
||||
enum phl_phy_idx phy_idx);
|
||||
void halbb_fwofld_set_efuse_8852b(struct bb_info *bb, u8 central_ch, enum phl_phy_idx phy_idx);
|
||||
void halbb_fwofld_set_gain_error_8852b(struct bb_info *bb, u8 central_ch, enum band_type band_type);
|
||||
void halbb_fwofld_set_rxsc_rpl_comp_8852b(struct bb_info *bb, u8 central_ch, enum band_type band_type);
|
||||
void halbb_fwofld_set_pmac_tx_8852b(struct bb_info *bb, struct halbb_pmac_info *tx_info,
|
||||
enum phl_phy_idx phy_idx);
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,369 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in the
|
||||
* file called LICENSE.
|
||||
*
|
||||
* Contact Information:
|
||||
* wlanfae <wlanfae@realtek.com>
|
||||
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
|
||||
* Hsinchu 300, Taiwan.
|
||||
*
|
||||
* Larry Finger <Larry.Finger@lwfinger.net>
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#include "../halbb_precomp.h"
|
||||
#include "halbb_hwimg_raw_data_8852b.h"
|
||||
#include "halbb_hwimg_raw_data_8852bp.h"
|
||||
#include "halbb_hwimg_raw_data_8852bt.h"
|
||||
#include "halbb_hwimg_raw_data_8852bpt.h"
|
||||
#include "halbb_hwimg_raw_data_8852b_gain.h"
|
||||
|
||||
#ifdef BB_8852B_SUPPORT
|
||||
|
||||
#if 0
|
||||
bool halbb_sel_headline_8852b(struct bb_info *bb, u32 *array, u32 array_len,
|
||||
u8 *headline_size, u8 *headline_idx)
|
||||
{
|
||||
bool case_match = false;
|
||||
u32 cut_drv = (u32)bb->hal_com->cv;
|
||||
u32 rfe_drv = (u32)bb->phl_com->dev_cap.rfe_type;
|
||||
u32 cut_para = 0, rfe_para = 0;
|
||||
u32 compare_target = 0;
|
||||
u32 cut_max = 0;
|
||||
u32 i = 0;
|
||||
|
||||
*headline_idx = 0;
|
||||
*headline_size = 0;
|
||||
|
||||
if (bb->bb_dbg_i.cr_dbg_mode_en) {
|
||||
rfe_drv = bb->bb_dbg_i.rfe_type_curr_dbg;
|
||||
cut_drv = bb->bb_dbg_i.cut_curr_dbg;
|
||||
}
|
||||
|
||||
BB_DBG(bb, DBG_INIT, "{RFE, Cart}={%d, %d}, dbg_en=%d\n",
|
||||
rfe_drv, cut_drv, bb->bb_dbg_i.cr_dbg_mode_en);
|
||||
|
||||
while ((i + 1) < array_len) {
|
||||
if ((array[i] >> 28) != 0xf) {
|
||||
*headline_size = (u8)i;
|
||||
break;
|
||||
}
|
||||
BB_DBG(bb, DBG_INIT, "array[%02d]=0x%08x, array[%02d]=0x%08x\n",
|
||||
i, array[i], i+1, array[i+1]);
|
||||
i += 2;
|
||||
}
|
||||
|
||||
BB_DBG(bb, DBG_INIT, "headline_size=%d\n", i);
|
||||
|
||||
if (i == 0)
|
||||
return true;
|
||||
|
||||
/*case_idx:1 {RFE:Match, CV:Match}*/
|
||||
compare_target = ((rfe_drv & 0xff) << 16) | (cut_drv & 0xff);
|
||||
BB_DBG(bb, DBG_INIT, "[1] CHK {RFE:Match, CV:Match}\n");
|
||||
for (i = 0; i < *headline_size; i += 2) {
|
||||
if ((array[i] & 0x0fffffff) == compare_target) {
|
||||
*headline_idx = (u8)(i >> 1);
|
||||
return true;
|
||||
}
|
||||
}
|
||||
BB_DBG(bb, DBG_INIT, "\t fail\n");
|
||||
|
||||
/*case_idx:2 {RFE:Match, CV:Dont care}*/
|
||||
compare_target = ((rfe_drv & 0xff) << 16) | (DONT_CARE_8852B & 0xff);
|
||||
BB_DBG(bb, DBG_INIT, "[2] CHK {RFE:Match, CV:Dont_Care}\n");
|
||||
for (i = 0; i < *headline_size; i += 2) {
|
||||
if ((array[i] & 0x0fffffff) == compare_target) {
|
||||
*headline_idx = (u8)(i >> 1);
|
||||
return true;
|
||||
}
|
||||
}
|
||||
BB_DBG(bb, DBG_INIT, "\t fail\n");
|
||||
|
||||
/*case_idx:3 {RFE:Match, CV:Max_in_Table}*/
|
||||
BB_DBG(bb, DBG_INIT, "[3] CHK {RFE:Match, CV:Max_in_Table}\n");
|
||||
for (i = 0; i < *headline_size; i += 2) {
|
||||
rfe_para = (array[i] & 0x00ff0000) >> 16;
|
||||
cut_para = array[i] & 0x0ff;
|
||||
if (rfe_para == rfe_drv) {
|
||||
if (cut_para >= cut_max) {
|
||||
cut_max = cut_para;
|
||||
*headline_idx = (u8)(i >> 1);
|
||||
BB_DBG(bb, DBG_INIT, "cut_max:%d\n", cut_max);
|
||||
case_match = true;
|
||||
}
|
||||
}
|
||||
}
|
||||
if (case_match) {
|
||||
return true;
|
||||
}
|
||||
BB_DBG(bb, DBG_INIT, "\t fail\n");
|
||||
|
||||
/*case_idx:4 {RFE:Dont Care, CV:Max_in_Table}*/
|
||||
BB_DBG(bb, DBG_INIT, "[4] CHK {RFE:Dont_Care, CV:Max_in_Table}\n");
|
||||
for (i = 0; i < *headline_size; i += 2) {
|
||||
rfe_para = (array[i] & 0x00ff0000) >> 16;
|
||||
cut_para = array[i] & 0x0ff;
|
||||
if (rfe_para == DONT_CARE_8852B) {
|
||||
if (cut_para >= cut_max) {
|
||||
cut_max = cut_para;
|
||||
*headline_idx = (u8)(i >> 1);
|
||||
BB_DBG(bb, DBG_INIT, "cut_max:%d\n", cut_max);
|
||||
case_match = true;
|
||||
}
|
||||
}
|
||||
}
|
||||
if (case_match) {
|
||||
return true;
|
||||
}
|
||||
BB_DBG(bb, DBG_INIT, "\t fail\n");
|
||||
|
||||
/*case_idx:5 {RFE:Not_Match, CV:Not_Match}*/
|
||||
BB_DBG(bb, DBG_INIT, "[5] CHK {RFE:Not_Match, CV:Not_Match}\n");
|
||||
BB_DBG(bb, DBG_INIT, "\t all fail\n");
|
||||
return false;
|
||||
}
|
||||
#endif
|
||||
|
||||
void halbb_flag_2_default_8852b(bool *is_matched, bool *find_target)
|
||||
{
|
||||
*is_matched = true;
|
||||
*find_target = false;
|
||||
}
|
||||
|
||||
bool halbb_cfg_bbcr_ax_8852b(struct bb_info *bb, bool is_form_folder,
|
||||
u32 folder_len, u32 *folder_array,
|
||||
enum phl_phy_idx phy_idx)
|
||||
{
|
||||
bool is_matched, find_target;
|
||||
u32 cfg_target = 0, cfg_para = 0;
|
||||
u32 i = 0;
|
||||
u32 array_len = 0;
|
||||
u32 *array = NULL;
|
||||
u32 v1 = 0, v2 = 0;
|
||||
u8 h_size = 0;
|
||||
u8 h_idx = 0;
|
||||
bool ret = false;
|
||||
|
||||
BB_DBG(bb, DBG_INIT, "===> %s\n", __func__);
|
||||
|
||||
if (is_form_folder) {
|
||||
array_len = folder_len;
|
||||
array = folder_array;
|
||||
} else if (bb->ic_sub_type == BB_IC_SUB_TYPE_8852B_8852BP) {
|
||||
array_len = sizeof(array_mp_8852bp_phy_reg) / sizeof(u32);
|
||||
array = (u32 *)array_mp_8852bp_phy_reg;
|
||||
} else if (bb->ic_sub_type == BB_IC_SUB_TYPE_8852B_8852BT) {
|
||||
array_len = sizeof(array_mp_8852bt_phy_reg) / sizeof(u32);
|
||||
array = (u32 *)array_mp_8852bt_phy_reg;
|
||||
} else if (bb->ic_sub_type == BB_IC_SUB_TYPE_8852B_8852BPT) {
|
||||
array_len = sizeof(array_mp_8852bpt_phy_reg) / sizeof(u32);
|
||||
array = (u32 *)array_mp_8852bpt_phy_reg;
|
||||
} else {
|
||||
array_len = sizeof(array_mp_8852b_phy_reg) / sizeof(u32);
|
||||
array = (u32 *)array_mp_8852b_phy_reg;
|
||||
}
|
||||
|
||||
BB_DBG(bb, DBG_INIT, "BBCR_form_folder=%d, len=%d, phy_idx=%d\n",
|
||||
is_form_folder, array_len, phy_idx);
|
||||
|
||||
if (!halbb_sel_headline(bb, array, array_len, &h_size, &h_idx)) {
|
||||
BB_WARNING("[%s]Invalid BB CR Pkg\n", __func__);
|
||||
return false;
|
||||
}
|
||||
BB_DBG(bb, DBG_INIT, "h_size = %d, h_idx = %d\n", h_size, h_idx);
|
||||
|
||||
if (h_size != 0) {
|
||||
cfg_target = array[h_idx << 1] & 0x0fffffff;
|
||||
}
|
||||
|
||||
i += h_size;
|
||||
|
||||
BB_DBG(bb, DBG_INIT, "cfg_target = 0x%x\n", cfg_target);
|
||||
BB_DBG(bb, DBG_INIT, "array[i] = 0x%x, array[i+1] = 0x%x\n", array[i], array[i + 1]);
|
||||
|
||||
halbb_flag_2_default_8852b(&is_matched, &find_target);
|
||||
#ifdef HALBB_FW_OFLD_SUPPORT
|
||||
if (halbb_check_fw_ofld(bb))
|
||||
BB_DBG(bb, DBG_FW_INFO, "Becareful it is fwofld mode in BB init !!");
|
||||
#endif
|
||||
while ((i + 1) < array_len) {
|
||||
v1 = array[i];
|
||||
v2 = array[i + 1];
|
||||
i += 2;
|
||||
|
||||
switch (v1 >> 28) {
|
||||
case IF_8852B:
|
||||
case ELSE_IF_8852B:
|
||||
cfg_para = v1 & 0x0fffffff;
|
||||
BB_DBG(bb, DBG_INIT, "*if (rfe=%d, cart=%d)\n",
|
||||
(cfg_para & 0xff0000) >> 16, cfg_para & 0xff);
|
||||
break;
|
||||
case ELSE_8852B:
|
||||
BB_DBG(bb, DBG_INIT, "*else\n");
|
||||
is_matched = false;
|
||||
if (!find_target) {
|
||||
BB_WARNING("Init BBCR Fail in Reg 0x%x\n", array[i]);
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
case END_8852B:
|
||||
BB_DBG(bb, DBG_INIT, "*endif\n");
|
||||
halbb_flag_2_default_8852b(&is_matched, &find_target);
|
||||
break;
|
||||
case CHK_8852B:
|
||||
/*Check this para meets driver's requirement or not*/
|
||||
if (find_target) {
|
||||
BB_DBG(bb, DBG_INIT, "\t skip\n");
|
||||
is_matched = false;
|
||||
break;
|
||||
}
|
||||
|
||||
if (cfg_para == cfg_target) {
|
||||
is_matched = true;
|
||||
find_target = true;
|
||||
} else {
|
||||
is_matched = false;
|
||||
find_target = false;
|
||||
}
|
||||
BB_DBG(bb, DBG_INIT, "\t match=%d\n", is_matched);
|
||||
break;
|
||||
default:
|
||||
if (is_matched)
|
||||
#ifdef HALBB_FW_OFLD_SUPPORT
|
||||
ret = halbb_fwcfg_bb_phy_8852b(bb, v1, v2, phy_idx);
|
||||
#else
|
||||
halbb_cfg_bb_phy_8852b(bb, v1, v2, phy_idx);
|
||||
#endif
|
||||
break;
|
||||
}
|
||||
}
|
||||
BB_DBG(bb, DBG_INIT, "BBCR Init Success\n\n");
|
||||
#ifdef HALBB_FW_OFLD_SUPPORT
|
||||
return ret;
|
||||
#else
|
||||
return true;
|
||||
#endif
|
||||
}
|
||||
|
||||
bool halbb_cfg_bb_gain_ax_8852b(struct bb_info *bb, bool is_form_folder,
|
||||
u32 folder_len, u32 *folder_array)
|
||||
{
|
||||
bool is_matched, find_target;
|
||||
u32 cfg_target = 0, cfg_para = 0;
|
||||
u32 i = 0;
|
||||
u32 array_len = 0;
|
||||
u32 *array = NULL;
|
||||
u32 v1 = 0, v2 = 0;
|
||||
u8 h_size = 0;
|
||||
u8 h_idx = 0;
|
||||
|
||||
BB_DBG(bb, DBG_INIT, "===> %s\n", __func__);
|
||||
|
||||
if (is_form_folder) {
|
||||
array_len = folder_len;
|
||||
array = folder_array;
|
||||
} else if (bb->ic_sub_type == BB_IC_SUB_TYPE_8852B_8852BP) {
|
||||
array_len = sizeof(array_mp_8852bp_phy_reg_gain) / sizeof(u32);
|
||||
array = (u32 *)array_mp_8852bp_phy_reg_gain;
|
||||
} else if (bb->ic_sub_type == BB_IC_SUB_TYPE_8852B_8852BT) {
|
||||
array_len = sizeof(array_mp_8852bt_phy_reg_gain) / sizeof(u32);
|
||||
array = (u32 *)array_mp_8852bt_phy_reg_gain;
|
||||
} else if (bb->ic_sub_type == BB_IC_SUB_TYPE_8852B_8852BPT) {
|
||||
array_len = sizeof(array_mp_8852bpt_phy_reg_gain) / sizeof(u32);
|
||||
array = (u32 *)array_mp_8852bpt_phy_reg_gain;
|
||||
} else {
|
||||
array_len = sizeof(array_mp_8852b_phy_reg_gain) / sizeof(u32);
|
||||
array = (u32 *)array_mp_8852b_phy_reg_gain;
|
||||
}
|
||||
|
||||
BB_DBG(bb, DBG_INIT, "GAIN_TABLE_form_folder=%d, len=%d\n",
|
||||
is_form_folder, array_len);
|
||||
|
||||
if (!halbb_sel_headline(bb, array, array_len, &h_size, &h_idx)) {
|
||||
BB_WARNING("[%s]Invalid BB CR Pkg\n", __func__);
|
||||
return false;
|
||||
}
|
||||
BB_DBG(bb, DBG_INIT, "h_size = %d, h_idx = %d\n", h_size, h_idx);
|
||||
|
||||
if (h_size != 0) {
|
||||
cfg_target = array[h_idx << 1] & 0x0fffffff;
|
||||
}
|
||||
|
||||
i += h_size;
|
||||
|
||||
BB_DBG(bb, DBG_INIT, "cfg_target = 0x%x\n", cfg_target);
|
||||
BB_DBG(bb, DBG_INIT, "array[i] = 0x%x, array[i+1] = 0x%x\n", array[i], array[i + 1]);
|
||||
|
||||
halbb_flag_2_default_8852b(&is_matched, &find_target);
|
||||
while ((i + 1) < array_len) {
|
||||
v1 = array[i];
|
||||
v2 = array[i + 1];
|
||||
i += 2;
|
||||
|
||||
switch (v1 >> 28) {
|
||||
case IF_8852B:
|
||||
case ELSE_IF_8852B:
|
||||
cfg_para = v1 & 0x0fffffff;
|
||||
BB_DBG(bb, DBG_INIT, "*if (rfe=%d, cart=%d)\n",
|
||||
(cfg_para & 0xff0000) >> 16, cfg_para & 0xff);
|
||||
break;
|
||||
case ELSE_8852B:
|
||||
BB_DBG(bb, DBG_INIT, "*else\n");
|
||||
is_matched = false;
|
||||
if (!find_target) {
|
||||
BB_WARNING("Init BBCR Fail in Reg 0x%x\n", array[i]);
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
case END_8852B:
|
||||
BB_DBG(bb, DBG_INIT, "*endif\n");
|
||||
halbb_flag_2_default_8852b(&is_matched, &find_target);
|
||||
break;
|
||||
case CHK_8852B:
|
||||
/*Check this para meets driver's requirement or not*/
|
||||
if (find_target) {
|
||||
BB_DBG(bb, DBG_INIT, "\t skip\n");
|
||||
is_matched = false;
|
||||
break;
|
||||
}
|
||||
|
||||
if (cfg_para == cfg_target) {
|
||||
is_matched = true;
|
||||
find_target = true;
|
||||
} else {
|
||||
is_matched = false;
|
||||
find_target = false;
|
||||
}
|
||||
BB_DBG(bb, DBG_INIT, "\t match=%d\n", is_matched);
|
||||
break;
|
||||
default:
|
||||
if (is_matched)
|
||||
halbb_cfg_bb_gain_8852b(bb, v1, v2);
|
||||
break;
|
||||
}
|
||||
}
|
||||
BB_DBG(bb, DBG_INIT, "BBCR gain Init Success\n\n");
|
||||
return true;
|
||||
}
|
||||
|
||||
u32
|
||||
halbb_get_8852b_phy_reg_ver(void)
|
||||
{
|
||||
return (u32)BB_REG_RELEASE_VERSION_8852B;
|
||||
}
|
||||
|
||||
#endif /* end of HWIMG_SUPPORT*/
|
||||
|
||||
@@ -0,0 +1,50 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in the
|
||||
* file called LICENSE.
|
||||
*
|
||||
* Contact Information:
|
||||
* wlanfae <wlanfae@realtek.com>
|
||||
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
|
||||
* Hsinchu 300, Taiwan.
|
||||
*
|
||||
* Larry Finger <Larry.Finger@lwfinger.net>
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef _HALBB_HW_IMG_8852B_H_
|
||||
#define _HALBB_HW_IMG_8852B_H_
|
||||
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
* phy_reg.TXT
|
||||
******************************************************************************/
|
||||
#define DONT_CARE_8852B 0xff
|
||||
|
||||
#define IF_8852B 0x8
|
||||
#define ELSE_IF_8852B 0x9
|
||||
#define ELSE_8852B 0xa
|
||||
#define END_8852B 0xb
|
||||
#define CHK_8852B 0x4
|
||||
|
||||
bool halbb_cfg_bbcr_ax_8852b(struct bb_info *bb, bool is_form_folder,
|
||||
u32 folder_len, u32 *folder_array,
|
||||
enum phl_phy_idx phy_idx);
|
||||
bool halbb_cfg_bb_gain_ax_8852b(struct bb_info *bb, bool is_form_folder,
|
||||
u32 folder_len, u32 *folder_array);
|
||||
u32 halbb_get_8852b_phy_reg_ver(void);
|
||||
|
||||
#endif /* end of HWIMG_SUPPORT*/
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
+31
@@ -0,0 +1,31 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2020 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in the
|
||||
* file called LICENSE.
|
||||
*
|
||||
* Contact Information:
|
||||
* wlanfae <wlanfae@realtek.com>
|
||||
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
|
||||
* Hsinchu 300, Taiwan.
|
||||
*
|
||||
* Larry Finger <Larry.Finger@lwfinger.net>
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
/*Image2HeaderVersion: R3 2.0.1.2*/
|
||||
#ifndef _HALBB_HWIMG_RAW_DATA_8852B_GAIN_H
|
||||
#define _HALBB_HWIMG_RAW_DATA_8852B_GAIN_H
|
||||
|
||||
|
||||
#endif /* _HALBB_HWIMG_RAW_DATA_8852B_GAIN_H */
|
||||
File diff suppressed because it is too large
Load Diff
+1288
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,154 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in the
|
||||
* file called LICENSE.
|
||||
*
|
||||
* Contact Information:
|
||||
* wlanfae <wlanfae@realtek.com>
|
||||
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
|
||||
* Hsinchu 300, Taiwan.
|
||||
*
|
||||
* Larry Finger <Larry.Finger@lwfinger.net>
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#include "../halbb_precomp.h"
|
||||
#ifdef BB_8852B_SUPPORT
|
||||
|
||||
void halbb_cfg_rf_reg_8852b(struct bb_info *bb, u32 addr, u32 data,
|
||||
enum rf_path rf_path, u32 reg_addr)
|
||||
{
|
||||
}
|
||||
|
||||
void halbb_cfg_rf_radio_a_8852b(struct bb_info *bb, u32 addr, u32 data)
|
||||
{
|
||||
}
|
||||
|
||||
void halbb_cfg_rf_radio_b_8852b(struct bb_info *bb, u32 addr, u32 data)
|
||||
{
|
||||
}
|
||||
|
||||
void halbb_cfg_bb_phy_8852b(struct bb_info *bb, u32 addr, u32 data,
|
||||
enum phl_phy_idx phy_idx)
|
||||
{
|
||||
#ifdef HALBB_DBCC_SUPPORT
|
||||
u32 ofst = 0;
|
||||
#endif
|
||||
|
||||
if (addr == 0xfe) {
|
||||
halbb_delay_ms(bb, 50);
|
||||
BB_DBG(bb, DBG_INIT, "Delay 50 ms\n");
|
||||
} else if (addr == 0xfd) {
|
||||
halbb_delay_ms(bb, 5);
|
||||
BB_DBG(bb, DBG_INIT, "Delay 5 ms\n");
|
||||
} else if (addr == 0xfc) {
|
||||
halbb_delay_ms(bb, 1);
|
||||
BB_DBG(bb, DBG_INIT, "Delay 1 ms\n");
|
||||
} else if (addr == 0xfb) {
|
||||
halbb_delay_us(bb, 50);
|
||||
BB_DBG(bb, DBG_INIT, "Delay 50 us\n");
|
||||
} else if (addr == 0xfa) {
|
||||
halbb_delay_us(bb, 5);
|
||||
BB_DBG(bb, DBG_INIT, "Delay 5 us\n");
|
||||
} else if (addr == 0xf9) {
|
||||
halbb_delay_us(bb, 1);
|
||||
BB_DBG(bb, DBG_INIT, "Delay 1 us\n");
|
||||
} else {
|
||||
#ifdef HALBB_DBCC_SUPPORT
|
||||
if ((bb->hal_com->dbcc_en || bb->bb_dbg_i.cr_dbg_mode_en) &&
|
||||
phy_idx == HW_PHY_1) {
|
||||
ofst = halbb_phy0_to_phy1_ofst(bb, addr, phy_idx);
|
||||
if (ofst == 0)
|
||||
return;
|
||||
addr += ofst;
|
||||
} else {
|
||||
phy_idx = HW_PHY_0;
|
||||
}
|
||||
BB_DBG(bb, DBG_INIT, "[REG][%d]0x%04X = 0x%08X\n", phy_idx, addr, data);
|
||||
#else
|
||||
BB_DBG(bb, DBG_INIT, "[REG]0x%04X = 0x%08X\n", addr, data);
|
||||
#endif
|
||||
|
||||
halbb_set_reg(bb, addr, MASKDWORD, data);
|
||||
}
|
||||
}
|
||||
|
||||
void halbb_cfg_bb_gain_8852b(struct bb_info *bb, u32 addr, u32 data)
|
||||
{
|
||||
struct bb_gain_info *gain = &bb->bb_gain_i;
|
||||
u8 cfg_type = (u8)((addr & 0xff000000) >> 24);
|
||||
enum bb_band_t band_idx = (enum bb_band_t)((addr & 0xff0000) >> 16);
|
||||
u8 path = (u8)((addr & 0xff00) >> 8);
|
||||
u8 type;
|
||||
u8 i = 0;
|
||||
|
||||
if (band_idx >= BB_GAIN_BAND_NUM)
|
||||
return;
|
||||
|
||||
if (path >= HALBB_MAX_PATH)
|
||||
return;
|
||||
|
||||
if (addr == 0xfe) {
|
||||
halbb_delay_ms(bb, 50);
|
||||
BB_DBG(bb, DBG_INIT, "Delay 50 ms\n");
|
||||
} else if (addr == 0xfd) {
|
||||
halbb_delay_ms(bb, 5);
|
||||
BB_DBG(bb, DBG_INIT, "Delay 5 ms\n");
|
||||
} else if (addr == 0xfc) {
|
||||
halbb_delay_ms(bb, 1);
|
||||
BB_DBG(bb, DBG_INIT, "Delay 1 ms\n");
|
||||
} else if (addr == 0xfb) {
|
||||
halbb_delay_us(bb, 50);
|
||||
BB_DBG(bb, DBG_INIT, "Delay 50 us\n");
|
||||
} else if (addr == 0xfa) {
|
||||
halbb_delay_us(bb, 5);
|
||||
BB_DBG(bb, DBG_INIT, "Delay 5 us\n");
|
||||
} else if (addr == 0xf9) {
|
||||
halbb_delay_us(bb, 1);
|
||||
BB_DBG(bb, DBG_INIT, "Delay 1 us\n");
|
||||
} else if (cfg_type ==0) { /*GAIN ERROR*/
|
||||
type = (u8)(addr & 0xff);
|
||||
if (type == 0) {
|
||||
for (i = 0; i < 4; i++)
|
||||
gain->lna_gain[band_idx][path][i] = (data >> (8 * i)) & 0xff;
|
||||
} else if (type == 1) {
|
||||
for (i = 0; i < 3; i++)
|
||||
gain->lna_gain[band_idx][path][4 + i] = (data >> (8 * i)) & 0xff;
|
||||
} else if (type == 2) {
|
||||
for (i = 0; i < 2; i++)
|
||||
gain->tia_gain[band_idx][path][i] = (data >> (8 * i)) & 0xff;
|
||||
}
|
||||
|
||||
if ((band_idx >= 4) && (band_idx <= 7)) { /*Avoid phy_reg_gain does not support band_idx 8~11*/
|
||||
if (type == 0) {
|
||||
for (i = 0; i < 4; i++)
|
||||
gain->lna_gain[band_idx + 4][path][i] = (data >> (8 * i)) & 0xff;
|
||||
} else if (type == 1) {
|
||||
for (i = 0; i < 3; i++)
|
||||
gain->lna_gain[band_idx + 4][path][4 + i] = (data >> (8 * i)) & 0xff;
|
||||
} else if (type == 2) {
|
||||
for (i = 0; i < 2; i++)
|
||||
gain->tia_gain[band_idx + 4][path][i] = (data >> (8 * i)) & 0xff;
|
||||
}
|
||||
}
|
||||
} else if (cfg_type == 1) { /*RPL Offset*/
|
||||
halbb_cfg_bb_rpl_ofst(bb, band_idx, path, addr, data);
|
||||
if ((band_idx >= 4) && (band_idx <= 7)) /*Avoid phy_reg_gain does not support band_idx 8~11*/
|
||||
halbb_cfg_bb_rpl_ofst(bb, band_idx + 4, path, addr, data);
|
||||
} else {
|
||||
BB_WARNING("cfg_type=%d\n", cfg_type);
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,34 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in the
|
||||
* file called LICENSE.
|
||||
*
|
||||
* Contact Information:
|
||||
* wlanfae <wlanfae@realtek.com>
|
||||
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
|
||||
* Hsinchu 300, Taiwan.
|
||||
*
|
||||
* Larry Finger <Larry.Finger@lwfinger.net>
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef _HALBB_REG_CFG_8852B_H_
|
||||
#define _HALBB_REG_CFG_8852B_H_
|
||||
|
||||
#ifdef BB_8852B_SUPPORT
|
||||
|
||||
void halbb_cfg_bb_phy_8852b(struct bb_info *bb, u32 addr, u32 data,
|
||||
enum phl_phy_idx phy_idx);
|
||||
void halbb_cfg_bb_gain_8852b(struct bb_info *bb, u32 addr, u32 data);
|
||||
#endif
|
||||
#endif /* RTL8852B_SUPPORT*/
|
||||
@@ -0,0 +1,30 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in the
|
||||
* file called LICENSE.
|
||||
*
|
||||
* Contact Information:
|
||||
* wlanfae <wlanfae@realtek.com>
|
||||
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
|
||||
* Hsinchu 300, Taiwan.
|
||||
*
|
||||
* Larry Finger <Larry.Finger@lwfinger.net>
|
||||
*
|
||||
*****************************************************************************/
|
||||
/*RTL8852B BB Parameters*/
|
||||
#ifndef _HALBB_VERSION_8852B_H_
|
||||
#define _HALBB_VERSION_8852B_H_
|
||||
#define BB_REG_RELEASE_DATE_8852B 20221220
|
||||
#define BB_REG_RELEASE_VERSION_8852B 31
|
||||
#endif
|
||||
@@ -0,0 +1,30 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in the
|
||||
* file called LICENSE.
|
||||
*
|
||||
* Contact Information:
|
||||
* wlanfae <wlanfae@realtek.com>
|
||||
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
|
||||
* Hsinchu 300, Taiwan.
|
||||
*
|
||||
* Larry Finger <Larry.Finger@lwfinger.net>
|
||||
*
|
||||
*****************************************************************************/
|
||||
/*RTL8852BP BB Parameters*/
|
||||
#ifndef _HALBB_VERSION_8852BP_H_
|
||||
#define _HALBB_VERSION_8852BP_H_
|
||||
#define BB_REG_RELEASE_DATE_8852BP 20230417
|
||||
#define BB_REG_RELEASE_VERSION_8852BP 5
|
||||
#endif
|
||||
@@ -0,0 +1,30 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in the
|
||||
* file called LICENSE.
|
||||
*
|
||||
* Contact Information:
|
||||
* wlanfae <wlanfae@realtek.com>
|
||||
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
|
||||
* Hsinchu 300, Taiwan.
|
||||
*
|
||||
* Larry Finger <Larry.Finger@lwfinger.net>
|
||||
*
|
||||
*****************************************************************************/
|
||||
/*RTL8852BPT BB Parameters*/
|
||||
#ifndef _HALBB_VERSION_8852BPT_H_
|
||||
#define _HALBB_VERSION_8852BPT_H_
|
||||
#define BB_REG_RELEASE_DATE_8852BPT 20240223
|
||||
#define BB_REG_RELEASE_VERSION_8852BPT 3
|
||||
#endif
|
||||
@@ -0,0 +1,30 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in the
|
||||
* file called LICENSE.
|
||||
*
|
||||
* Contact Information:
|
||||
* wlanfae <wlanfae@realtek.com>
|
||||
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
|
||||
* Hsinchu 300, Taiwan.
|
||||
*
|
||||
* Larry Finger <Larry.Finger@lwfinger.net>
|
||||
*
|
||||
*****************************************************************************/
|
||||
/*RTL8852BT BB Parameters*/
|
||||
#ifndef _HALBB_VERSION_8852BT_H_
|
||||
#define _HALBB_VERSION_8852BT_H_
|
||||
#define BB_REG_RELEASE_DATE_8852BT 20240205
|
||||
#define BB_REG_RELEASE_VERSION_8852BT 7
|
||||
#endif
|
||||
@@ -0,0 +1,486 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2020 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in the
|
||||
* file called LICENSE.
|
||||
*
|
||||
* Contact Information:
|
||||
* wlanfae <wlanfae@realtek.com>
|
||||
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
|
||||
* Hsinchu 300, Taiwan.
|
||||
*
|
||||
* Larry Finger <Larry.Finger@lwfinger.net>
|
||||
*
|
||||
*****************************************************************************/
|
||||
#include "../halbb_precomp.h"
|
||||
|
||||
#ifdef BB_8852C_SUPPORT
|
||||
|
||||
void halbb_bfee_en_8852c(struct bb_info *bb, bool csi_en)
|
||||
{
|
||||
if (csi_en) {
|
||||
rtw_hal_mac_ax_init_bf_role(bb->hal_com, 0, HW_PHY_0);
|
||||
rtw_hal_mac_ax_init_bf_role(bb->hal_com, 0, HW_PHY_1);
|
||||
} else {
|
||||
rtw_hal_mac_ax_deinit_bfee(bb->hal_com, HW_PHY_0);
|
||||
rtw_hal_mac_ax_deinit_bfee(bb->hal_com, HW_PHY_1);
|
||||
}
|
||||
}
|
||||
|
||||
bool halbb_chk_pkg_valid_8852c(struct bb_info *bb, u8 bb_ver, u8 rf_ver)
|
||||
{
|
||||
bool valid = true;
|
||||
|
||||
#if 0
|
||||
if (bb_ver >= X && rf_ver >= Y)
|
||||
valid = true;
|
||||
else if (bb_ver < X && rf_ver < Y)
|
||||
valid = true;
|
||||
else
|
||||
valid = false;
|
||||
#endif
|
||||
|
||||
if (!valid) {
|
||||
/*halbb_set_reg(bb, 0x1c3c, (BIT(0) | BIT(1)), 0x0);*/
|
||||
BB_WARNING("[%s] Pkg_ver{bb, rf}={%d, %d} disable all BB block\n",
|
||||
__func__, bb_ver, rf_ver);
|
||||
}
|
||||
|
||||
return valid;
|
||||
}
|
||||
|
||||
bool halbb_chk_tx_idle_8852c(struct bb_info *bb, enum phl_phy_idx phy_idx)
|
||||
{
|
||||
u8 tx_state = 0;
|
||||
bool idle = false;
|
||||
u32 dbg_port = 0x30002;
|
||||
|
||||
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
|
||||
|
||||
if (phy_idx == HW_PHY_1)
|
||||
dbg_port = 0x30005;
|
||||
|
||||
if (halbb_bb_dbg_port_racing(bb, DBGPORT_PRI_3)) {
|
||||
halbb_dbg_port_sel(bb, (u16)(dbg_port & 0xffff),
|
||||
(u8)((dbg_port & 0xff0000) >> 16), 0x0, 0x1);
|
||||
BB_DBG(bb, DBG_PHY_CONFIG,
|
||||
"*Set dbg_port=(0x%x)\n", dbg_port);
|
||||
} else {
|
||||
dbg_port = halbb_get_bb_dbg_port_idx(bb);
|
||||
BB_DBG(bb, DBG_PHY_CONFIG,
|
||||
"[Set dbg_port fail!] Curr-DbgPort=0x%x\n", dbg_port);
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
/* Release DBG port */
|
||||
halbb_release_bb_dbg_port(bb);
|
||||
|
||||
tx_state = (u8)(halbb_get_bb_dbg_port_val(bb) & 0x3f);
|
||||
|
||||
if (tx_state == 0)
|
||||
idle = true;
|
||||
else
|
||||
idle = false;
|
||||
|
||||
return idle;
|
||||
}
|
||||
|
||||
void halbb_stop_pmac_tx_8852c(struct bb_info *bb,
|
||||
struct halbb_pmac_info *tx_info,
|
||||
enum phl_phy_idx phy_idx)
|
||||
{
|
||||
if (tx_info->is_cck) { // CCK
|
||||
if (tx_info->mode == CONT_TX) {
|
||||
halbb_set_reg(bb, 0x231c, BIT(1), 1);
|
||||
halbb_set_reg(bb, 0x2318, BIT(8), 0);
|
||||
halbb_set_reg(bb, 0x231c, BIT(21), 0);
|
||||
halbb_set_reg(bb, 0x231c, BIT(1), 0);
|
||||
} else if (tx_info->mode == PKTS_TX) {
|
||||
halbb_set_reg_cmn(bb, 0x9c4, BIT(4), 0, phy_idx);
|
||||
} else if (tx_info->mode == CCK_CARRIER_SIPPRESSION_TX) {
|
||||
halbb_set_reg_cmn(bb, 0x9c4, BIT(4), 0, phy_idx);
|
||||
/*Carrier Suppress Tx*/
|
||||
halbb_set_reg(bb, 0x2318, BIT(9), 0);
|
||||
/*Enable scrambler at payload part*/
|
||||
halbb_set_reg(bb, 0x231c, BIT(7), 0);
|
||||
}
|
||||
} else { // OFDM
|
||||
if (tx_info->mode == CONT_TX)
|
||||
halbb_set_reg_cmn(bb, 0x9c4, BIT(0), 0, phy_idx);
|
||||
else if (tx_info->mode == PKTS_TX)
|
||||
halbb_set_reg_cmn(bb, 0x9c4, BIT(4), 0, phy_idx);
|
||||
}
|
||||
}
|
||||
|
||||
void halbb_start_pmac_tx_8852c(struct bb_info *bb,
|
||||
struct halbb_pmac_info *tx_info,
|
||||
enum halbb_pmac_mode mode, u32 pkt_cnt,u16 period,
|
||||
enum phl_phy_idx phy_idx)
|
||||
{
|
||||
if (mode == CONT_TX) {
|
||||
if (tx_info->is_cck) {
|
||||
halbb_set_reg(bb, 0x2318, BIT(8), 1);
|
||||
halbb_set_reg(bb, 0x231c, BIT(21), 1);
|
||||
} else {
|
||||
halbb_set_reg_cmn(bb, 0x9c4, BIT(0), 1, phy_idx);
|
||||
}
|
||||
} else if (mode == PKTS_TX) {
|
||||
/*Tx_N_PACKET_EN */
|
||||
halbb_set_reg_cmn(bb, 0x9c4, BIT(4), 1, phy_idx);
|
||||
/*Tx_N_PERIOD */
|
||||
halbb_set_reg_cmn(bb, 0x9c4, 0xffffff00, period, phy_idx);
|
||||
/*Tx_N_PACKET */
|
||||
halbb_set_reg_cmn(bb, 0x9c8, 0xffffffff, pkt_cnt, phy_idx);
|
||||
} else if (mode == CCK_CARRIER_SIPPRESSION_TX) {
|
||||
if (tx_info->is_cck) {
|
||||
/*Carrier Suppress Tx*/
|
||||
halbb_set_reg(bb, 0x2318, BIT(9), 1);
|
||||
/*Disable scrambler at payload part*/
|
||||
halbb_set_reg(bb, 0x231c, BIT(7), 1);
|
||||
} else {
|
||||
return;
|
||||
}
|
||||
/*Tx_N_PACKET_EN */
|
||||
halbb_set_reg_cmn(bb, 0x9c4, BIT(4), 1, phy_idx);
|
||||
/*Tx_N_PERIOD */
|
||||
halbb_set_reg_cmn(bb, 0x9c4, 0xffffff00, period, phy_idx);
|
||||
/*Tx_N_PACKET */
|
||||
halbb_set_reg_cmn(bb, 0x9c8, 0xffffffff, pkt_cnt, phy_idx);
|
||||
}
|
||||
/*Tx_EN */
|
||||
halbb_set_reg_cmn(bb, 0x9c0, BIT(0), 1, phy_idx);
|
||||
halbb_set_reg_cmn(bb, 0x9c0, BIT(0), 0, phy_idx);
|
||||
}
|
||||
|
||||
void halbb_set_pmac_tx_8852c(struct bb_info *bb_0, struct halbb_pmac_info *tx_info,
|
||||
enum phl_phy_idx phy_idx)
|
||||
{
|
||||
struct bb_info *bb = bb_0;
|
||||
|
||||
#ifdef HALBB_DBCC_SUPPORT
|
||||
HALBB_GET_PHY_PTR(bb_0, bb, phy_idx);
|
||||
#endif
|
||||
|
||||
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
|
||||
|
||||
if (!tx_info->en_pmac_tx) {
|
||||
halbb_stop_pmac_tx_8852c(bb, tx_info, phy_idx);
|
||||
/* PD hit enable */
|
||||
halbb_set_reg_cmn(bb, 0xc3c, BIT(9), 0, phy_idx);
|
||||
if (bb->bb_ch_i.is_2g)
|
||||
halbb_set_reg(bb, 0x2320, BIT(0), 0);
|
||||
return;
|
||||
}
|
||||
/*Turn on PMAC */
|
||||
/* Tx */
|
||||
halbb_set_reg_cmn(bb, 0x0980, BIT(0), 1, phy_idx);
|
||||
/* Rx */
|
||||
halbb_set_reg_cmn(bb, 0x0980, BIT(16), 1, phy_idx);
|
||||
halbb_set_reg_cmn(bb, 0x0988, 0x3f, 0x3f, phy_idx);
|
||||
|
||||
/* PD hit enable */
|
||||
halbb_set_reg_cmn(bb, 0x704, BIT(1), 0, phy_idx);
|
||||
halbb_set_reg_cmn(bb, 0xc3c, BIT(9), 1, phy_idx);
|
||||
if (tx_info->cck_lbk_en) {
|
||||
halbb_set_reg(bb, 0x2320, BIT(0), 0);
|
||||
} else {
|
||||
if (bb->bb_ch_i.is_2g)
|
||||
halbb_set_reg(bb, 0x2320, BIT(0), 1);
|
||||
}
|
||||
halbb_set_reg_cmn(bb, 0x704, BIT(1), 1, phy_idx);
|
||||
|
||||
halbb_start_pmac_tx_8852c(bb, tx_info, tx_info->mode, tx_info->tx_cnt,
|
||||
tx_info->period, phy_idx);
|
||||
|
||||
BB_DBG(bb, DBG_PHY_CONFIG, "[PMAC Tx] cck_lbk_en=%d\n", tx_info->cck_lbk_en);
|
||||
}
|
||||
|
||||
void halbb_set_tmac_tx_8852c(struct bb_info *bb, enum phl_phy_idx phy_idx)
|
||||
{
|
||||
/* To do: 0x0d80[16] [25] / 0x0d88[5:0] Should be set to default value in parameter package*/
|
||||
/* Turn on TMAC */
|
||||
halbb_set_reg_cmn(bb, 0x0980, BIT(0), 0, phy_idx);
|
||||
halbb_set_reg_cmn(bb, 0x0980, BIT(16), 0, phy_idx);
|
||||
halbb_set_reg_cmn(bb, 0x0988, 0xfff, 0, phy_idx);
|
||||
halbb_set_reg_cmn(bb, 0x0994, 0xf0, 0, phy_idx);
|
||||
// PDP bypass from TMAC
|
||||
halbb_set_reg_cmn(bb, 0x09a4, BIT(10), 0, phy_idx);
|
||||
// TMAC Tx path
|
||||
halbb_set_reg_cmn(bb, 0x09a4, 0x1c, 0, phy_idx);
|
||||
// TMAC Tx power
|
||||
halbb_set_reg_cmn(bb, 0x09a4, BIT(16), 0, phy_idx);
|
||||
// TMAC Tx OFDM triangular shaping filter
|
||||
halbb_set_reg_cmn(bb, 0x09a4, BIT(31), 0, phy_idx);
|
||||
}
|
||||
|
||||
void halbb_dpd_bypass_8852c(struct bb_info *bb, bool pdp_bypass,
|
||||
enum phl_phy_idx phy_idx)
|
||||
{
|
||||
halbb_set_reg_cmn(bb, 0x09a4, BIT(10), 1, phy_idx);
|
||||
halbb_set_reg_cmn(bb, 0x45b8, BIT(16), pdp_bypass, phy_idx);
|
||||
}
|
||||
|
||||
void halbb_ic_hw_setting_init_8852c(struct bb_info *bb)
|
||||
{
|
||||
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
|
||||
//Set dbcc_80p80_sel_evm_rpt_en
|
||||
halbb_set_reg(bb, 0xa10, BIT(0), 1);
|
||||
halbb_set_reg(bb, 0x2a10, BIT(0), 1);
|
||||
|
||||
if (bb->hal_com->cv != CAV) {
|
||||
//set minimum UL txpwr requirement to -10dBm
|
||||
halbb_write_mask_pwr_reg_cmn(bb, HW_PHY_0, 0xd240, 0x3fe00, 0x1d8);
|
||||
halbb_write_mask_pwr_reg_cmn(bb, HW_PHY_1, 0xd240, 0x3fe00, 0x1d8);
|
||||
//set UL txpwr compensation to 0dB
|
||||
halbb_write_mask_pwr_reg_cmn(bb, HW_PHY_0, 0xd290, 0xff, 0);
|
||||
halbb_write_mask_pwr_reg_cmn(bb, HW_PHY_1, 0xd290, 0xff, 0);
|
||||
}
|
||||
}
|
||||
|
||||
void halbb_ic_hw_setting_8852c(struct bb_info *bb)
|
||||
{
|
||||
bool btg_en;
|
||||
|
||||
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
|
||||
|
||||
btg_en = (bb->hal_com->band[0].cur_chandef.band == BAND_ON_24G) &&
|
||||
((bb->rx_path == RF_PATH_B) || (bb->rx_path == RF_PATH_AB)) ? true : false;
|
||||
|
||||
if (btg_en && bb->bb_link_i.is_linked && (bb->bb_ch_i.rssi_min < (75 << 1))) {// if rssi < -35 dbm
|
||||
halbb_set_reg(bb, 0x4aa4, BIT(18), 0x0);
|
||||
BB_DBG(bb, DBG_PHY_CONFIG, "[BT] BTG enable, Is linked\n");
|
||||
BB_DBG(bb, DBG_PHY_CONFIG, "[BT][RSSI] rssi_min=0x%x\n", bb->bb_ch_i.rssi_min >> 1);
|
||||
} else {
|
||||
halbb_set_reg(bb, 0x4aa4, BIT(18), 0x1);
|
||||
BB_DBG(bb, DBG_PHY_CONFIG, "[BT] btg_en=%d, is_linked=%d\n", btg_en, bb->bb_link_i.is_linked);
|
||||
BB_DBG(bb, DBG_PHY_CONFIG, "[BT][RSSI] rssi_min=0x%x\n", bb->bb_ch_i.rssi_min >> 1);
|
||||
}
|
||||
}
|
||||
|
||||
bool halbb_set_pd_lower_bound_8852c(struct bb_info *bb, u8 bound,
|
||||
enum channel_width bw,
|
||||
enum phl_phy_idx phy_idx)
|
||||
{
|
||||
/*
|
||||
Range of bound value:
|
||||
BW20: 95~33
|
||||
BW40: 92~30
|
||||
BW80: 89~27
|
||||
*/
|
||||
#ifdef HALBB_DIG_TDMA_SUPPORT
|
||||
struct bb_dig_info *bb_dig = &bb->bb_dig_i;
|
||||
struct bb_dig_op_unit *bb_dig_u = bb_dig->p_cur_dig_unit;
|
||||
#endif
|
||||
u8 bw_attenuation = 0;
|
||||
u8 subband_filter_atteniation = 7;
|
||||
u8 bound_idx = 0;
|
||||
bool rpt = true;
|
||||
|
||||
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
|
||||
|
||||
if (bound == 0) {
|
||||
halbb_set_reg_cmn(bb, 0x481C, BIT(29), 0, phy_idx);
|
||||
BB_DBG(bb, DBG_PHY_CONFIG,
|
||||
"[PD Bound] Set Boundary to default!\n");
|
||||
return true;
|
||||
}
|
||||
|
||||
bb->bb_cmn_backup_i.cur_pd_lower_bound = bound;
|
||||
|
||||
if ((bw == CHANNEL_WIDTH_20) || (bw == CHANNEL_WIDTH_10) || (bw == CHANNEL_WIDTH_5)) {
|
||||
bw_attenuation = 0;
|
||||
} else if (bw == CHANNEL_WIDTH_40) {
|
||||
bw_attenuation = 3;
|
||||
} else if (bw == CHANNEL_WIDTH_80) {
|
||||
bw_attenuation = 6;
|
||||
} else if (bw == CHANNEL_WIDTH_160) {
|
||||
bw_attenuation = 9;
|
||||
} else {
|
||||
BB_DBG(bb, DBG_PHY_CONFIG,
|
||||
"[PD Bound] Only support BW5/10/20/40/80/160 !\n");
|
||||
return false;
|
||||
}
|
||||
|
||||
bound += (bw_attenuation + subband_filter_atteniation);
|
||||
// If Boundary dbm is odd, set it to even number
|
||||
bound = bound % 2 ? bound + 1 : bound;
|
||||
|
||||
if (bound < 40) {
|
||||
BB_DBG(bb, DBG_PHY_CONFIG,
|
||||
"[PD Bound] Threshold too high, set to highest level!\n");
|
||||
bound = 40;
|
||||
rpt = false;
|
||||
}
|
||||
|
||||
if (bound > 102) {
|
||||
BB_DBG(bb, DBG_PHY_CONFIG,
|
||||
"[PD Bound] Threshold too low, disable PD lower bound function!\n");
|
||||
halbb_set_reg_cmn(bb, 0x481C, BIT(29), 0, phy_idx);
|
||||
return true;
|
||||
}
|
||||
|
||||
bound_idx = (102 - bound) >> 1;
|
||||
|
||||
halbb_set_reg_cmn(bb, 0x481C, 0x7c0, bound_idx, phy_idx);
|
||||
halbb_set_reg_cmn(bb, 0x481C, BIT(29), 1, phy_idx);
|
||||
|
||||
BB_DBG(bb, DBG_PHY_CONFIG, "[PD Bound] Set Boundary Success!\n");
|
||||
|
||||
#ifdef HALBB_DIG_TDMA_SUPPORT
|
||||
if ((bb_dig->dig_mode != DIG_TDMA) && (bb_dig->dig_mode != DIG_TDMA_ADV))
|
||||
return rpt;
|
||||
|
||||
if (bb_dig_u->state_identifier == DIG_TDMA_LOW)
|
||||
bb_dig->dig_state_l_i.pd_low_th = bound;
|
||||
else
|
||||
bb_dig->dig_state_h_i.pd_low_th = bound;
|
||||
#endif
|
||||
|
||||
return rpt;
|
||||
}
|
||||
|
||||
bool halbb_set_pd_lower_bound_cck_8852c(struct bb_info *bb, u8 bound,
|
||||
enum channel_width bw,
|
||||
enum phl_phy_idx phy_idx)
|
||||
{
|
||||
#ifdef HALBB_DIG_TDMA_SUPPORT
|
||||
struct bb_dig_info *bb_dig = &bb->bb_dig_i;
|
||||
struct bb_dig_op_unit *bb_dig_u = bb_dig->p_cur_dig_unit;
|
||||
#endif
|
||||
struct bb_scan_h2c_info *scan_ofld = &bb->bb_scan_h2c_i;
|
||||
u8 bw_attenuation = 0;
|
||||
u8 subband_filter_atteniation = 5;
|
||||
s8 bound_tmp = 0;
|
||||
|
||||
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
|
||||
|
||||
if (bound == 0 && scan_ofld->scan_mode != BB_P2P_SCAN) {
|
||||
halbb_set_reg_cmn(bb, 0x4b74, BIT(30), 0, phy_idx);
|
||||
BB_DBG(bb, DBG_PHY_CONFIG,
|
||||
"[PD Bound] Set Boundary to default!\n");
|
||||
return true;
|
||||
}
|
||||
if ((bw == CHANNEL_WIDTH_20) || (bw == CHANNEL_WIDTH_10) || (bw == CHANNEL_WIDTH_5)) {
|
||||
bw_attenuation = 0;
|
||||
} else if (bw == CHANNEL_WIDTH_40) {
|
||||
bw_attenuation = 3;
|
||||
} else if (bw == CHANNEL_WIDTH_80) {
|
||||
bw_attenuation = 6;
|
||||
} else if (bw == CHANNEL_WIDTH_160) {
|
||||
bw_attenuation = 9;
|
||||
} else {
|
||||
BB_DBG(bb, DBG_PHY_CONFIG,
|
||||
"[PD Bound] Only support BW5/10/20/40/80/160 !\n");
|
||||
return false;
|
||||
}
|
||||
|
||||
bound += (bw_attenuation + subband_filter_atteniation);
|
||||
bound_tmp = (-1) * MIN_2(bound, 128);
|
||||
|
||||
halbb_set_reg_cmn(bb, 0x4b64, 0xff000000, bound_tmp, phy_idx);
|
||||
halbb_set_reg_cmn(bb, 0x4b64, 0xff0000, 0x7f, phy_idx);
|
||||
halbb_set_reg_cmn(bb, 0x4b74, BIT(30), 1, phy_idx);
|
||||
|
||||
BB_DBG(bb, DBG_PHY_CONFIG, "[PD Bound] Set CCK Boundary Success!\n");
|
||||
|
||||
#ifdef HALBB_DIG_TDMA_SUPPORT
|
||||
if ((bb_dig->dig_mode != DIG_TDMA) && (bb_dig->dig_mode != DIG_TDMA_ADV))
|
||||
return true;
|
||||
|
||||
if (bb_dig_u->state_identifier == DIG_TDMA_LOW)
|
||||
bb_dig->dig_state_l_i.rssi_nocca_low_th= bound_tmp;
|
||||
else
|
||||
bb_dig->dig_state_h_i.rssi_nocca_low_th = bound_tmp;
|
||||
#endif
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
u8 halbb_querry_pd_lower_bound_8852c(struct bb_info *bb, bool get_en_info, enum phl_phy_idx phy_idx)
|
||||
{
|
||||
u8 tmp;
|
||||
|
||||
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
|
||||
|
||||
if (get_en_info)
|
||||
tmp = (u8)halbb_get_reg_cmn(bb, 0x481C, BIT(29), phy_idx);
|
||||
else
|
||||
tmp = bb->bb_cmn_backup_i.cur_pd_lower_bound;
|
||||
|
||||
return tmp;
|
||||
}
|
||||
|
||||
void halbb_pop_en_8852c(struct bb_info *bb, bool en, enum phl_phy_idx phy_idx)
|
||||
{
|
||||
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
|
||||
|
||||
if (en) {
|
||||
halbb_set_reg_cmn(bb, 0x4798, BIT(8), 1, phy_idx);
|
||||
|
||||
halbb_set_reg_cmn(bb, 0xc54, 0x6, 0, phy_idx);
|
||||
halbb_set_reg_cmn(bb, 0xc68, 0xff, 0x50, phy_idx);
|
||||
halbb_set_reg_cmn(bb, 0x4794, 0xF8000, 0xc, phy_idx);
|
||||
halbb_set_reg_cmn(bb, 0x4794, 0x1F00000, 8, phy_idx);
|
||||
halbb_set_reg_cmn(bb, 0x4798, BIT(9), 0, phy_idx);
|
||||
} else {
|
||||
halbb_set_reg_cmn(bb, 0x4798, BIT(8), 0, phy_idx);
|
||||
}
|
||||
}
|
||||
|
||||
bool halbb_querry_pop_en_8852c(struct bb_info *bb, enum phl_phy_idx phy_idx)
|
||||
{
|
||||
bool en;
|
||||
|
||||
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
|
||||
|
||||
en = (bool)halbb_get_reg_cmn(bb, 0x4798, BIT(8), phy_idx);
|
||||
|
||||
return en;
|
||||
}
|
||||
|
||||
u16 halbb_get_per_8852c(struct bb_info *bb, enum phl_phy_idx phy_idx)
|
||||
{
|
||||
u16 per;
|
||||
u32 crc_ok, crc_err, brk_cnt;
|
||||
u32 numer, denomer;
|
||||
|
||||
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
|
||||
|
||||
crc_ok = halbb_mp_get_rx_crc_ok(bb, phy_idx);
|
||||
crc_err = halbb_mp_get_rx_crc_err(bb, phy_idx);
|
||||
brk_cnt = halbb_get_reg_cmn(bb, 0x1a08, MASKHWORD, phy_idx);
|
||||
|
||||
if ((crc_ok > 0xffff) || (crc_err > 0xffff)) {
|
||||
BB_DBG(bb, DBG_DBG_API, "[PER] Value > Brk cnt upper bound!\n");
|
||||
return 0xffff;
|
||||
}
|
||||
|
||||
denomer = crc_ok + crc_err + brk_cnt;
|
||||
numer = crc_err + brk_cnt + (denomer >> 1);
|
||||
per = (u16)HALBB_DIV(numer * 100, denomer);
|
||||
|
||||
return per;
|
||||
}
|
||||
|
||||
u8 halbb_get_losel_8852c(struct bb_info *bb)
|
||||
{
|
||||
u8 tmp = 0;
|
||||
|
||||
BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__);
|
||||
|
||||
tmp = (u8)halbb_get_reg(bb, 0x35c, BIT(11) | BIT(10));
|
||||
return tmp;
|
||||
}
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,57 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2020 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in the
|
||||
* file called LICENSE.
|
||||
*
|
||||
* Contact Information:
|
||||
* wlanfae <wlanfae@realtek.com>
|
||||
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
|
||||
* Hsinchu 300, Taiwan.
|
||||
*
|
||||
* Larry Finger <Larry.Finger@lwfinger.net>
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __HALBB_8852C_H__
|
||||
#define __HALBB_8852C_H__
|
||||
#ifdef BB_8852C_SUPPORT
|
||||
|
||||
#include "../halbb_pmac_setting_ex.h"
|
||||
|
||||
struct bb_info;
|
||||
void halbb_bfee_en_8852c(struct bb_info *bb, bool csi_en);
|
||||
bool halbb_chk_pkg_valid_8852c(struct bb_info *bb, u8 bb_ver, u8 rf_ver);
|
||||
void halbb_set_pmac_tx_8852c(struct bb_info *bb, struct halbb_pmac_info *tx_info,
|
||||
enum phl_phy_idx phy_idx);
|
||||
void halbb_set_tmac_tx_8852c(struct bb_info *bb, enum phl_phy_idx phy_idx);
|
||||
void halbb_dpd_bypass_8852c(struct bb_info *bb, bool pdp_bypass,
|
||||
enum phl_phy_idx phy_idx);
|
||||
void halbb_ic_hw_setting_init_8852c(struct bb_info *bb);
|
||||
void halbb_ic_hw_setting_8852c(struct bb_info *bb);
|
||||
|
||||
bool halbb_set_pd_lower_bound_8852c(struct bb_info *bb, u8 bound,
|
||||
enum channel_width bw,
|
||||
enum phl_phy_idx phy_idx);
|
||||
bool halbb_set_pd_lower_bound_cck_8852c(struct bb_info *bb, u8 bound,
|
||||
enum channel_width bw,
|
||||
enum phl_phy_idx phy_idx);
|
||||
u8 halbb_querry_pd_lower_bound_8852c(struct bb_info *bb, bool get_en_info,
|
||||
enum phl_phy_idx phy_idx);
|
||||
void halbb_pop_en_8852c(struct bb_info *bb, bool en, enum phl_phy_idx phy_idx);
|
||||
bool halbb_querry_pop_en_8852c(struct bb_info *bb, enum phl_phy_idx phy_idx);
|
||||
u16 halbb_get_per_8852c(struct bb_info *bb, enum phl_phy_idx phy_idx);
|
||||
u8 halbb_get_losel_8852c(struct bb_info *bb);
|
||||
bool halbb_chk_tx_idle_8852c(struct bb_info *bb, enum phl_phy_idx phy_idx);
|
||||
|
||||
#endif
|
||||
#endif /* __HALBB_8852C_H__ */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,290 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2020 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in the
|
||||
* file called LICENSE.
|
||||
*
|
||||
* Contact Information:
|
||||
* wlanfae <wlanfae@realtek.com>
|
||||
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
|
||||
* Hsinchu 300, Taiwan.
|
||||
*
|
||||
* Larry Finger <Larry.Finger@lwfinger.net>
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __HALBB_8852C_API_H__
|
||||
#define __HALBB_8852C_API_H__
|
||||
#ifdef BB_8852C_SUPPORT
|
||||
#include "../halbb_api.h"
|
||||
|
||||
/*@--------------------------[Define]-------------------------------------*/
|
||||
#define INVALID_RF_DATA 0xffffffff
|
||||
#define BB_PATH_MAX_8852C 2
|
||||
#define HE_N_USER_MAX_8852C 8
|
||||
|
||||
#define GAIN_HIDE_EFUSE_START_ADDR_8852C 0x585
|
||||
|
||||
#define GAIN_HIDE_EFUSE_A_2G_8852C 0x5BB
|
||||
#define GAIN_HIDE_EFUSE_A_5GL_8852C 0x5BA
|
||||
#define GAIN_HIDE_EFUSE_A_5GM_8852C 0x5B9
|
||||
#define GAIN_HIDE_EFUSE_A_5GH_8852C 0x5B8
|
||||
#define GAIN_HIDE_EFUSE_A_6GH_0_8852C 0x5B7
|
||||
#define GAIN_HIDE_EFUSE_A_6GH_1_8852C 0x5B6
|
||||
#define GAIN_HIDE_EFUSE_A_6GH_2_8852C 0x5B5
|
||||
#define GAIN_HIDE_EFUSE_A_6GH_3_8852C 0x5B4
|
||||
#define GAIN_HIDE_EFUSE_A_6GH_4_8852C 0x5B3
|
||||
#define GAIN_HIDE_EFUSE_A_6GH_5_8852C 0x5B2
|
||||
#define GAIN_HIDE_EFUSE_A_6GH_6_8852C 0x5B1
|
||||
#define GAIN_HIDE_EFUSE_A_6GH_7_8852C 0x5B0
|
||||
#define GAIN_HIDE_EFUSE_B_2G_8852C 0x590
|
||||
#define GAIN_HIDE_EFUSE_B_5GL_8852C 0x58F
|
||||
#define GAIN_HIDE_EFUSE_B_5GM_8852C 0x58E
|
||||
#define GAIN_HIDE_EFUSE_B_5GH_8852C 0x58D
|
||||
#define GAIN_HIDE_EFUSE_B_6GH_0_8852C 0x58C
|
||||
#define GAIN_HIDE_EFUSE_B_6GH_1_8852C 0x58B
|
||||
#define GAIN_HIDE_EFUSE_B_6GH_2_8852C 0x58A
|
||||
#define GAIN_HIDE_EFUSE_B_6GH_3_8852C 0x589
|
||||
#define GAIN_HIDE_EFUSE_B_6GH_4_8852C 0x588
|
||||
#define GAIN_HIDE_EFUSE_B_6GH_5_8852C 0x587
|
||||
#define GAIN_HIDE_EFUSE_B_6GH_6_8852C 0x586
|
||||
#define GAIN_HIDE_EFUSE_B_6GH_7_8852C 0x585
|
||||
|
||||
/*@--------------------------[Feature]---------------------------------------*/
|
||||
/*@--------------------------[Enum]------------------------------------------*/
|
||||
/*@--------------------------[Structure]-------------------------------------*/
|
||||
struct bb_h2c_lps_info_8852c {
|
||||
u8 central_ch;
|
||||
u8 pri_ch;
|
||||
u8 bw;
|
||||
u8 band_type;
|
||||
};
|
||||
/*@--------------------------[Prptotype]-------------------------------------*/
|
||||
struct bb_info;
|
||||
|
||||
u8 halbb_ex_evm_1ss_report_8852c(struct bb_info *bb);
|
||||
u8 halbb_ex_evm_max_report_8852c(struct bb_info *bb);
|
||||
u8 halbb_ex_evm_min_report_8852c(struct bb_info *bb);
|
||||
|
||||
bool halbb_set_vht_mu_user_idx_8852c(struct bb_info *bb, bool en, u8 idx,
|
||||
enum phl_phy_idx phy_idx);
|
||||
bool halbb_set_pwr_ul_tb_ofst_8852c(struct bb_info *bb,
|
||||
s8 pw_ofst, enum phl_phy_idx phy_idx);
|
||||
bool halbb_lps_info_8852c(struct bb_info *bb, u16 mac_id);
|
||||
bool halbb_lps_cmn_info_8852c(struct bb_info *bb);
|
||||
void halbb_digital_cfo_comp_8852c(struct bb_info *bb, s32 curr_cfo);
|
||||
|
||||
void halbb_tx_triangular_shap_cfg_8852c(struct bb_info *bb, u8 shape_idx,
|
||||
enum phl_phy_idx phy_idx);
|
||||
void halbb_set_digital_pwr_comp_8852c(struct bb_info *bb, bool en,
|
||||
enum phl_phy_idx phy_idx);
|
||||
void halbb_tx_dfir_shap_cck_8852c(struct bb_info *bb, u8 ch, u8 shape_idx,
|
||||
enum phl_phy_idx phy_idx);
|
||||
bool halbb_ctrl_bw_ch_8852c(struct bb_info *bb, u8 pri_ch, u8 central_ch,
|
||||
enum channel_width bw, enum band_type band,
|
||||
enum phl_phy_idx phy_idx);
|
||||
void halbb_1r_cca_cr_cfg_8852c(struct bb_info *bb, enum rf_path rx_path);
|
||||
bool halbb_ctrl_rx_path_8852c(struct bb_info *bb, enum rf_path rx_path, bool dbcc_en);
|
||||
bool halbb_ctrl_tx_path_pmac_8852c(struct bb_info *bb, enum rf_path tx_path, bool dbcc_en);
|
||||
bool halbb_ctrl_tx_path_tmac_8852c(struct bb_info *bb, enum rf_path tx_path_1sts, bool dbcc_en);
|
||||
bool halbb_ctrl_tx_path_8852c(struct bb_info *bb, enum rf_path tx_path);
|
||||
#ifdef HALBB_PWR_CTRL_SUPPORT
|
||||
void halbb_tssi_ctrl_set_dbw_table_8852c(struct bb_info *bb);
|
||||
#endif
|
||||
#if 0
|
||||
bool halbb_cfg_rx_path_8852c(struct bb_info *bb, enum rf_path rx_path,
|
||||
u8 rx_nss, enum phl_phy_idx phy_idx);
|
||||
|
||||
bool halbb_cfg_tx_path_8852c(struct bb_info *bb, enum rf_path tx_path,
|
||||
u8 tx_nss,enum phl_phy_idx phy_idx);
|
||||
#endif
|
||||
|
||||
u32 halbb_phy0_to_phy1_ofst_8852c(struct bb_info *bb, u32 addr);
|
||||
|
||||
void halbb_gpio_ctrl_dump_8852c(struct bb_info *bb);
|
||||
|
||||
void halbb_gpio_rfm_8852c(struct bb_info *bb, enum bb_path path,
|
||||
enum bb_rfe_src_sel src, bool dis_tx_gnt_wl,
|
||||
bool active_tx_opt, bool act_bt_en, u8 rfm_output_val);
|
||||
|
||||
void halbb_gpio_trsw_table_8852c(struct bb_info *bb, enum bb_path path,
|
||||
bool path_en, bool trsw_tx,
|
||||
bool trsw_rx, bool trsw, bool trsw_b);
|
||||
|
||||
void halbb_gpio_setting_8852c(struct bb_info *bb, u8 gpio_idx,
|
||||
enum bb_path path, bool inv,
|
||||
enum bb_rfe_src_sel src);
|
||||
|
||||
void halbb_gpio_setting_all_8852c(struct bb_info *bb, u8 rfe_idx);
|
||||
|
||||
void halbb_gpio_setting_init_8852c(struct bb_info *bb);
|
||||
|
||||
void halbb_bb_reset_8852c(struct bb_info *bb, enum phl_phy_idx phy_idx);
|
||||
|
||||
u32 halbb_read_rf_reg_8852c(struct bb_info *bb, enum rf_path path, u32 reg_addr,
|
||||
u32 bit_mask);
|
||||
|
||||
bool halbb_write_rf_reg_8852c(struct bb_info *bb, enum rf_path path, u32 reg_addr,
|
||||
u32 bit_mask, u32 data);
|
||||
|
||||
bool halbb_spur_location_8852c(struct bb_info *bb, u8 central_ch,
|
||||
enum channel_width bw, enum band_type band,
|
||||
u32 *intf);
|
||||
bool halbb_spur_location_for_CSI_8852c(struct bb_info *bb, u8 central_ch,
|
||||
enum channel_width bw, enum band_type band,
|
||||
u32 *intf);
|
||||
|
||||
bool halbb_ctrl_bw_8852c(struct bb_info *bb, u8 pri_ch, enum channel_width bw,
|
||||
bool is_efem, enum phl_phy_idx phy_idx);
|
||||
|
||||
bool halbb_query_cck_en_8852c(struct bb_info *bb, enum phl_phy_idx phy_idx,
|
||||
u8 func_idx);
|
||||
|
||||
void halbb_ctrl_cck_en_8852c(struct bb_info *bb, bool cck_en,
|
||||
enum phl_phy_idx phy_idx, u8 func_idx);
|
||||
|
||||
u16 halbb_cfg_cmac_tx_ant_8852c(struct bb_info *bb, enum rf_path tx_path);
|
||||
|
||||
void halbb_ctrl_trx_path_8852c(struct bb_info *bb, enum rf_path tx_path,
|
||||
u8 tx_nss, enum rf_path rx_path, u8 rx_nss);
|
||||
#if 0
|
||||
void halbb_cfg_trx_path_8852c(struct bb_info *bb, enum rf_path tx_path,
|
||||
u8 tx_nss, enum rf_path rx_path, u8 rx_nss,
|
||||
enum phl_phy_idx phy_idx, bool tmac_en);
|
||||
#endif
|
||||
|
||||
void halbb_dfs_en_8852c(struct bb_info *bb, bool en);
|
||||
|
||||
void halbb_adc_en_8852c(struct bb_info *bb, bool en, enum phl_phy_idx phy_idx);
|
||||
|
||||
void halbb_tssi_cont_en_8852c(struct bb_info *bb, bool en, enum rf_path path);
|
||||
|
||||
void halbb_bb_reset_en_8852c(struct bb_info *bb, bool en, enum phl_phy_idx phy_idx);
|
||||
|
||||
void halbb_fix_rx_htmcs0_8852c(struct bb_info *bb, bool en, enum phl_phy_idx phy_idx);
|
||||
|
||||
void halbb_tssi_bb_reset_8852c(struct bb_info *bb);
|
||||
|
||||
bool halbb_ctrl_sco_cck_8852c(struct bb_info *bb, u8 pri_ch);
|
||||
|
||||
bool halbb_adc_cfg_8852c(struct bb_info *bb, enum channel_width bw, bool is_efem,
|
||||
enum rf_path path);
|
||||
|
||||
void halbb_ctrl_rf_mode_8852c(struct bb_info *bb, enum phl_rf_mode mode);
|
||||
|
||||
bool halbb_ctrl_ch2_80p80_8852c(struct bb_info *bb, u8 central_ch);
|
||||
|
||||
#ifdef HALBB_DBCC_SUPPORT
|
||||
void halbb_ctrl_dbcc_8852c(struct bb_info *bb, bool dbcc_en);
|
||||
|
||||
void halbb_cfg_dbcc_cck_phy_map_8852c(struct bb_info *bb, bool dbcc_en,
|
||||
enum phl_phy_idx cck_phy_map);
|
||||
|
||||
void halbb_cfg_dbcc_8852c(struct bb_info *bb, struct bb_dbcc_cfg_info *cfg);
|
||||
#endif
|
||||
|
||||
void halbb_ctrl_rx_cca_8852c(struct bb_info *bb, bool cca_en, enum phl_phy_idx phy_idx);
|
||||
|
||||
void halbb_ctrl_ofdm_en_8852c(struct bb_info *bb, bool ofdm_en,
|
||||
enum phl_phy_idx phy_idx);
|
||||
bool halbb_set_txpwr_dbm_8852c(struct bb_info *bb, s16 power_dbm,
|
||||
enum phl_phy_idx phy_idx);
|
||||
|
||||
void halbb_reset_bb_hw_cnt_8852c(struct bb_info *bb);
|
||||
|
||||
s16 halbb_get_txpwr_dbm_8852c(struct bb_info *bb, enum phl_phy_idx phy_idx);
|
||||
|
||||
s16 halbb_get_txinfo_txpwr_dbm_8852c(struct bb_info *bb);
|
||||
|
||||
bool halbb_set_cck_txpwr_idx_8852c(struct bb_info *bb, u16 power_idx,
|
||||
enum rf_path tx_path);
|
||||
u16 halbb_get_cck_txpwr_idx_8852c(struct bb_info *bb, enum rf_path tx_path);
|
||||
|
||||
s16 halbb_get_cck_ref_dbm_8852c(struct bb_info *bb, enum rf_path tx_path);
|
||||
|
||||
bool halbb_set_ofdm_txpwr_idx_8852c(struct bb_info *bb, u16 power_idx,
|
||||
enum rf_path tx_path);
|
||||
|
||||
u16 halbb_get_ofdm_txpwr_idx_8852c(struct bb_info *bb, enum rf_path tx_path);
|
||||
|
||||
s16 halbb_get_ofdm_ref_dbm_8852c(struct bb_info *bb, enum rf_path tx_path);
|
||||
|
||||
void halbb_backup_info_8852c(struct bb_info *bb, enum phl_phy_idx phy_idx);
|
||||
|
||||
void halbb_restore_info_8852c(struct bb_info *bb, enum phl_phy_idx phy_idx);
|
||||
|
||||
bool halbb_cfg_lbk_8852c(struct bb_info *bb, bool lbk_en, bool is_dgt_lbk,
|
||||
enum rf_path tx_path, enum rf_path rx_path,
|
||||
enum channel_width bw, enum phl_phy_idx phy_idx);
|
||||
|
||||
bool halbb_cfg_lbk_cck_8852c(struct bb_info *bb, bool lbk_en, bool is_dgt_lbk,
|
||||
enum rf_path tx_path, enum rf_path rx_path,
|
||||
enum channel_width bw, enum phl_phy_idx phy_idx);
|
||||
|
||||
void halbb_ctrl_btg_8852c(struct bb_info *bb, bool btg);
|
||||
|
||||
void halbb_ctrl_btc_preagc_8852c(struct bb_info *bb, bool bt_en);
|
||||
|
||||
bool halbb_set_txsc_8852c(struct bb_info *bb, u8 txsc, enum phl_phy_idx phy_idx);
|
||||
|
||||
bool halbb_set_bss_color_8852c(struct bb_info *bb, u8 bss_color,
|
||||
enum phl_phy_idx phy_idx);
|
||||
|
||||
bool halbb_set_sta_id_8852c(struct bb_info *bb, u16 sta_id,
|
||||
enum phl_phy_idx phy_idx);
|
||||
|
||||
void halbb_set_igi_8852c(struct bb_info *bb, u8 lna_idx, bool tia_idx,
|
||||
u8 rxbb_idx, enum rf_path path);
|
||||
void halbb_set_tx_pow_per_path_lmt_8852c(struct bb_info *bb, s16 pwr_lmt_a, s16 pwr_lmt_b);
|
||||
void halbb_set_tx_pow_ref_8852c(struct bb_info *bb, s16 pw_dbm_ofdm, /*s(9,2)*/
|
||||
s16 pw_dbm_cck, s8 ofst,
|
||||
u8 base_cw_0db, u16 tssi_16dBm_cw,
|
||||
u16 *ofdm_cw, u16 *cck_cw,
|
||||
enum phl_phy_idx phy_idx);
|
||||
void halbb_dump_bb_reg_8852c(struct bb_info *bb, u32 *_used, char *output,
|
||||
u32 *_out_len, bool dump_2_buff, enum bb_frc_phy_dump_reg frc_phy_dump);
|
||||
void halbb_dbgport_dump_all_8852c(struct bb_info *bb, u32 *_used, char *output,
|
||||
u32 *_out_len);
|
||||
void halbb_physts_brk_fail_pkt_rpt_8852c(struct bb_info *bb, bool enable,
|
||||
enum phl_phy_idx phy_idx);
|
||||
|
||||
bool halbb_rf_write_bb_reg_8852c(struct bb_info *bb, u32 addr, u32 mask, u32 data);
|
||||
void halbb_pre_agc_en_8852c(struct bb_info *bb, bool enable);
|
||||
void halbb_agc_fix_gain_8852c(struct bb_info *bb, bool enable, enum rf_path path);
|
||||
void halbb_agc_elna_idx_8852c(struct bb_info *bb, bool elna_idx, enum rf_path path);
|
||||
void halbb_agc_tia_shrink_8852c(struct bb_info *bb, bool shrink_en,
|
||||
bool shrink_init, enum rf_path path);
|
||||
void halbb_agc_step_en_8852c(struct bb_info *bb, bool pre_pd_agc_en,
|
||||
bool linear_agc_en, bool post_pd_agc_en,
|
||||
bool nlgc_agc_en, enum rf_path path);
|
||||
void halbb_get_efuse_ofst_init_8852c(struct bb_info *bb);
|
||||
void halbb_get_normal_efuse_init_8852c(struct bb_info *bb);
|
||||
void halbb_get_hidden_efuse_init_8852c(struct bb_info *bb);
|
||||
void halbb_set_hidden_efuse_8852c(struct bb_info *bb, u8 central_ch, enum band_type band_type, bool is_efem, enum rf_path path);
|
||||
void halbb_set_normal_efuse_8852c(struct bb_info *bb, u8 central_ch, enum band_type band_type, enum rf_path path);
|
||||
void halbb_set_gain_cr_init_8852c(struct bb_info *bb);
|
||||
void halbb_set_gain_error_8852c(struct bb_info *bb, u8 central_ch, enum band_type band, bool is_efem, enum rf_path path);
|
||||
void halbb_set_rxsc_rpl_comp_8852c(struct bb_info* bb, u8 central_ch, enum band_type band_type);
|
||||
void halbb_normal_efuse_verify_8852c(struct bb_info *bb, s8 rx_gain_offset,
|
||||
enum rf_path rx_path,
|
||||
enum phl_phy_idx phy_idx);
|
||||
void halbb_normal_efuse_verify_cck_8852c(struct bb_info *bb, s8 rx_gain_offset,
|
||||
enum rf_path rx_path,
|
||||
enum phl_phy_idx phy_idx);
|
||||
void halbb_show_gain_err_8852c(struct bb_info *bb, char input[][16],
|
||||
u32 *_used, char *output, u32 *_out_len);
|
||||
void halbb_rx_op1db_dbg_8852c(struct bb_info *bb, char input[][16],
|
||||
u32 *_used, char *output, u32 *_out_len);
|
||||
void halbb_clk_en_8852c(struct bb_info *bb, bool en, enum phl_phy_idx phy_idx);
|
||||
void halbb_pwr_en_8852c(struct bb_info *bb, bool en);
|
||||
#endif
|
||||
#endif
|
||||
@@ -0,0 +1,34 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2020 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in the
|
||||
* file called LICENSE.
|
||||
*
|
||||
* Contact Information:
|
||||
* wlanfae <wlanfae@realtek.com>
|
||||
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
|
||||
* Hsinchu 300, Taiwan.
|
||||
*
|
||||
* Larry Finger <Larry.Finger@lwfinger.net>
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __HALBB_8852C_API_EX_H__
|
||||
#define __HALBB_8852C_API_EX_H__
|
||||
#ifdef BB_8852C_SUPPORT
|
||||
|
||||
/*@--------------------------[Prptotype]-------------------------------------*/
|
||||
struct bb_info;
|
||||
|
||||
|
||||
#endif
|
||||
#endif /* __INC_PHYDM_API_H_8852C__ */
|
||||
@@ -0,0 +1,78 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2019 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef _HALBB_XBOX_RA_H_
|
||||
#define _HALBB_XBOX_RA_H_
|
||||
#ifdef BB_8852C_SUPPORT
|
||||
#ifdef HALBB_DCRA_EN
|
||||
|
||||
/*@--------------------------[Define] ---------------------------------------*/
|
||||
|
||||
#define RATE_UP_TH 7
|
||||
|
||||
enum highest_mcs {
|
||||
L0_HIGHEST_MCS = 0x82,
|
||||
L1_HIGHEST_MCS = 0x83,
|
||||
L2_HIGHEST_MCS = 0x86,
|
||||
L3_HIGHEST_MCS = 0x87
|
||||
};
|
||||
|
||||
enum power_setting {
|
||||
power_boost = 0x1E,
|
||||
non_power_boost = 0x14
|
||||
};
|
||||
|
||||
enum msft_rate {
|
||||
MCS0 = 0x0,
|
||||
MCS1 = 0x1,
|
||||
MCS2 = 0x2,
|
||||
MCS3 = 0x3,
|
||||
MCS4 = 0x4,
|
||||
MCS5 = 0x5,
|
||||
MCS6 = 0x6,
|
||||
MCS7 = 0x7,
|
||||
MCS8 = 0x8,
|
||||
MCS9 = 0x9
|
||||
};
|
||||
|
||||
/*@--------------------------[Structure]-------------------------------------*/
|
||||
|
||||
struct bb_category_info {
|
||||
u8 total;
|
||||
u8 pkt_ok_num;
|
||||
u8 boost_pwr: 4;
|
||||
u8 rate_down_flag: 4;
|
||||
u8 rate_up_cnt;
|
||||
u16 initial_rate;
|
||||
u16 absolute_highest_mcs;
|
||||
u16 report_highest_success_mcs;
|
||||
u16 report_lowest_fail_mcs;
|
||||
u32 start_time;
|
||||
};
|
||||
|
||||
/*@--------------------------[Prptotype]-------------------------------------*/
|
||||
|
||||
void halbb_upt_mcs_table(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i, struct rtw_xpltfm_mcs_table *mcs_table);
|
||||
void halbb_category_init(bb, bb_category);
|
||||
void halbb_mcs_info_parsing(struct bb_info *bb, struct bb_category_info *category, struct rtw_phl_stainfo_t *phl_sta_i, struct rtw_xpltfm_mcs_table *mcs_table);
|
||||
void halbb_tx_report_parsing(struct bb_info *bb, struct bb_category_info *category, struct rtw_phl_stainfo_t *phl_sta_i);
|
||||
void halbb_rate_decision(struct bb_info *bb, struct bb_category_info *category, struct rtw_xpltfm_mcs_table *mcs_table);
|
||||
void halbb_rate_down(struct bb_info *bb, struct bb_category_info *category, struct rtw_xpltfm_mcs_table *mcs_table, u8 length_category);
|
||||
void halbb_rate_up(struct bb_info *bb, struct bb_category_info *category, struct rtw_xpltfm_mcs_table *mcs_table, u8 length_category);
|
||||
void halbb_modify_timer(struct bb_info *bb, struct bb_category_info *category, struct rtw_phl_stainfo_t *phl_sta_i);
|
||||
u8 halbb_arfr_table(struct bb_info *bb, u16 init_rate, u8 switch_table);
|
||||
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
@@ -0,0 +1,34 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2019 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef _HALBB_XBOX_RA_EX_H_
|
||||
#define _HALBB_XBOX_RA_EX_H_
|
||||
#ifdef BB_8852C_SUPPORT
|
||||
/*@--------------------------[Define] ---------------------------------------*/
|
||||
|
||||
|
||||
|
||||
/*@--------------------------[Enum]------------------------------------------*/
|
||||
|
||||
|
||||
|
||||
/*@--------------------------[Structure]-------------------------------------*/
|
||||
struct rtw_xpltfm_mcs_table;
|
||||
|
||||
/*@--------------------------[Prptotype]-------------------------------------*/
|
||||
|
||||
void halbb_upt_mcs_table(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i, struct rtw_xpltfm_mcs_table *mcs_table);
|
||||
u8 halbb_arfr_table(struct bb_info *bb, u16 init_rate, u8 switch_table);
|
||||
#endif
|
||||
#endif
|
||||
@@ -0,0 +1,62 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2020 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in the
|
||||
* file called LICENSE.
|
||||
*
|
||||
* Contact Information:
|
||||
* wlanfae <wlanfae@realtek.com>
|
||||
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
|
||||
* Hsinchu 300, Taiwan.
|
||||
*
|
||||
* Larry Finger <Larry.Finger@lwfinger.net>
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __HALBB_8852C_FWOFLD_API_H__
|
||||
#define __HALBB_8852C_FWOFLD_API_H__
|
||||
#ifdef BB_8852C_SUPPORT
|
||||
#ifdef HALBB_CONFIG_RUN_IN_DRV
|
||||
#include "../halbb_api.h"
|
||||
#include "../halbb_fwofld_ex.h"
|
||||
#endif
|
||||
|
||||
|
||||
/*@--------------------------[Define] ---------------------------------------*/
|
||||
|
||||
/*@--------------------------[Enum]------------------------------------------*/
|
||||
|
||||
/*@--------------------------[Structure]-------------------------------------*/
|
||||
|
||||
|
||||
struct bb_info;
|
||||
/*@--------------------------[Prptotype]-------------------------------------*/
|
||||
#ifdef HALBB_FW_OFLD_SUPPORT
|
||||
bool halbb_fwcfg_bb_phy_8852c(struct bb_info *bb, u32 addr, u32 data,
|
||||
enum phl_phy_idx phy_idx);
|
||||
bool halbb_fwofld_ctrl_ch_8852c(struct bb_info *bb, u8 central_ch, enum band_type band,
|
||||
enum phl_phy_idx phy_idx);
|
||||
bool halbb_fwofld_ctrl_bw_ch_8852c(struct bb_info *bb, u8 pri_ch, u8 central_ch,
|
||||
enum channel_width bw, enum band_type band,
|
||||
enum phl_phy_idx phy_idx);
|
||||
void halbb_fwofld_ctrl_cck_en_8852c(struct bb_info *bb, bool cck_en,
|
||||
enum phl_phy_idx phy_idx);
|
||||
void halbb_fwofld_set_hidden_efuse_8852c(struct bb_info *bb, u8 central_ch, enum band_type band_type, enum rf_path path);
|
||||
void halbb_fwofld_set_normal_efuse_8852c(struct bb_info *bb, u8 central_ch, enum band_type band_type, enum rf_path path);
|
||||
void halbb_fwofld_set_gain_error_8852c(struct bb_info *bb, u8 central_ch,
|
||||
enum band_type band_type,
|
||||
enum rf_path path);
|
||||
void halbb_fwofld_set_gain_cr_init_8852c(struct bb_info *bb);
|
||||
void halbb_fwofld_set_rxsc_rpl_comp_8852c(struct bb_info *bb, u8 central_ch, enum band_type band_type);
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,370 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in the
|
||||
* file called LICENSE.
|
||||
*
|
||||
* Contact Information:
|
||||
* wlanfae <wlanfae@realtek.com>
|
||||
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
|
||||
* Hsinchu 300, Taiwan.
|
||||
*
|
||||
* Larry Finger <Larry.Finger@lwfinger.net>
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#include "../halbb_precomp.h"
|
||||
#include "halbb_hwimg_raw_data_8852c.h"
|
||||
#include "halbb_hwimg_raw_data_8852d.h"
|
||||
#include "halbb_hwimg_raw_data_8842a.h"
|
||||
|
||||
#ifdef BB_8852C_SUPPORT
|
||||
|
||||
#if 0
|
||||
bool halbb_sel_headline_8852c(struct bb_info *bb, u32 *array, u32 array_len,
|
||||
u8 *headline_size, u8 *headline_idx)
|
||||
{
|
||||
bool case_match = false;
|
||||
u32 cut_drv = (u32)bb->hal_com->cv;
|
||||
u32 rfe_drv = (u32)bb->phl_com->dev_cap.rfe_type;
|
||||
u32 cut_para = 0, rfe_para = 0;
|
||||
u32 compare_target = 0;
|
||||
u32 cut_max = 0;
|
||||
u32 i = 0;
|
||||
|
||||
*headline_idx = 0;
|
||||
*headline_size = 0;
|
||||
|
||||
if (bb->bb_dbg_i.cr_dbg_mode_en) {
|
||||
rfe_drv = bb->bb_dbg_i.rfe_type_curr_dbg;
|
||||
cut_drv = bb->bb_dbg_i.cut_curr_dbg;
|
||||
}
|
||||
|
||||
BB_DBG(bb, DBG_INIT, "{RFE, Cart}={%d, %d}, dbg_en=%d\n",
|
||||
rfe_drv, cut_drv, bb->bb_dbg_i.cr_dbg_mode_en);
|
||||
|
||||
while ((i + 1) < array_len) {
|
||||
if ((array[i] >> 28) != 0xf) {
|
||||
*headline_size = (u8)i;
|
||||
break;
|
||||
}
|
||||
BB_DBG(bb, DBG_INIT, "array[%02d]=0x%08x, array[%02d]=0x%08x\n",
|
||||
i, array[i], i+1, array[i+1]);
|
||||
i += 2;
|
||||
}
|
||||
|
||||
BB_DBG(bb, DBG_INIT, "headline_size=%d\n", i);
|
||||
|
||||
if (i == 0)
|
||||
return true;
|
||||
|
||||
/*case_idx:1 {RFE:Match, CUT:Match}*/
|
||||
compare_target = ((rfe_drv & 0xff) << 16) | (cut_drv & 0xff);
|
||||
BB_DBG(bb, DBG_INIT, "[1] CHK {RFE:Match, CUT:Match}\n");
|
||||
for (i = 0; i < *headline_size; i += 2) {
|
||||
if ((array[i] & 0x0fffffff) == compare_target) {
|
||||
*headline_idx = (u8)(i >> 1);
|
||||
return true;
|
||||
}
|
||||
}
|
||||
BB_DBG(bb, DBG_INIT, "\t fail\n");
|
||||
|
||||
/*case_idx:2 {RFE:Match, CUT:Dont care}*/
|
||||
compare_target = ((rfe_drv & 0xff) << 16) | (DONT_CARE_8852C & 0xff);
|
||||
BB_DBG(bb, DBG_INIT, "[2] CHK {RFE:Match, CUT:Dont_Care}\n");
|
||||
for (i = 0; i < *headline_size; i += 2) {
|
||||
if ((array[i] & 0x0fffffff) == compare_target) {
|
||||
*headline_idx = (u8)(i >> 1);
|
||||
return true;
|
||||
}
|
||||
}
|
||||
BB_DBG(bb, DBG_INIT, "\t fail\n");
|
||||
|
||||
/*case_idx:3 {RFE:Match, CUT:Max_in_table}*/
|
||||
BB_DBG(bb, DBG_INIT, "[3] CHK {RFE:Match, CUT:Max_in_Table}\n");
|
||||
for (i = 0; i < *headline_size; i += 2) {
|
||||
rfe_para = (array[i] & 0x00ff0000) >> 16;
|
||||
cut_para = array[i] & 0x0ff;
|
||||
if (rfe_para == rfe_drv) {
|
||||
if (cut_para >= cut_max) {
|
||||
cut_max = cut_para;
|
||||
*headline_idx = (u8)(i >> 1);
|
||||
BB_DBG(bb, DBG_INIT, "cut_max:%d\n", cut_max);
|
||||
case_match = true;
|
||||
}
|
||||
}
|
||||
}
|
||||
if (case_match) {
|
||||
return true;
|
||||
}
|
||||
BB_DBG(bb, DBG_INIT, "\t fail\n");
|
||||
|
||||
/*case_idx:4 {RFE:Dont Care, CUT:Max_in_table}*/
|
||||
BB_DBG(bb, DBG_INIT, "[4] CHK {RFE:Dont_Care, CUT:Max_in_Table}\n");
|
||||
for (i = 0; i < *headline_size; i += 2) {
|
||||
rfe_para = (array[i] & 0x00ff0000) >> 16;
|
||||
cut_para = array[i] & 0x0ff;
|
||||
if (rfe_para == DONT_CARE_8852C) {
|
||||
if (cut_para >= cut_max) {
|
||||
cut_max = cut_para;
|
||||
*headline_idx = (u8)(i >> 1);
|
||||
BB_DBG(bb, DBG_INIT, "cut_max:%d\n", cut_max);
|
||||
case_match = true;
|
||||
}
|
||||
}
|
||||
}
|
||||
if (case_match) {
|
||||
return true;
|
||||
}
|
||||
BB_DBG(bb, DBG_INIT, "\t fail\n");
|
||||
|
||||
/*case_idx:5 {RFE:Not_Match, CUT:Not_Match}*/
|
||||
BB_DBG(bb, DBG_INIT, "[5] CHK {RFE:Not_Match, CUT:Not_Match}\n");
|
||||
BB_DBG(bb, DBG_INIT, "\t all fail\n");
|
||||
return false;
|
||||
}
|
||||
#endif
|
||||
|
||||
void halbb_flag_2_default_8852c(bool *is_matched, bool *find_target)
|
||||
{
|
||||
*is_matched = true;
|
||||
*find_target = false;
|
||||
}
|
||||
|
||||
bool halbb_cfg_bbcr_ax_8852c(struct bb_info *bb, bool is_form_folder,
|
||||
u32 folder_len, u32 *folder_array,
|
||||
enum phl_phy_idx phy_idx)
|
||||
{
|
||||
bool is_matched, find_target;
|
||||
u32 cfg_target = 0, cfg_para = 0;
|
||||
u32 i = 0;
|
||||
u32 array_len = 0;
|
||||
u32 *array = NULL;
|
||||
u32 v1 = 0, v2 = 0;
|
||||
u8 h_size = 0;
|
||||
u8 h_idx = 0;
|
||||
|
||||
BB_DBG(bb, DBG_INIT, "===> %s\n", __func__);
|
||||
|
||||
if (is_form_folder) {
|
||||
array_len = folder_len;
|
||||
array = folder_array;
|
||||
} else if (bb->ic_sub_type == BB_IC_SUB_TYPE_8852C_8852C) {
|
||||
array_len = sizeof(array_mp_8852c_phy_reg) / sizeof(u32);
|
||||
array = (u32 *)array_mp_8852c_phy_reg;
|
||||
} else if (bb->ic_sub_type == BB_IC_SUB_TYPE_8852C_8852D) {
|
||||
array_len = sizeof(array_mp_8852d_phy_reg) / sizeof(u32);
|
||||
array = (u32 *)array_mp_8852d_phy_reg;
|
||||
} else if ((bb->ic_sub_type == BB_IC_SUB_TYPE_8852C_8842A) ||
|
||||
(bb->ic_sub_type == BB_IC_SUB_TYPE_8852C_8842A_6967A)) {
|
||||
array_len = sizeof(array_mp_8842a_phy_reg) / sizeof(u32);
|
||||
array = (u32 *)array_mp_8842a_phy_reg;
|
||||
}
|
||||
|
||||
BB_DBG(bb, DBG_INIT, "form_folder=%d, len=%d, dbcc_en=%d, phy_idx=%d\n",
|
||||
is_form_folder, array_len, bb->hal_com->dbcc_en, phy_idx);
|
||||
|
||||
if (!array) {
|
||||
BB_WARNING("[%s]Invalid array\n", __func__);
|
||||
return false;
|
||||
}
|
||||
if (!halbb_sel_headline(bb, array, array_len, &h_size, &h_idx)) {
|
||||
BB_WARNING("[%s]Invalid BB CR Pkg\n", __func__);
|
||||
return false;
|
||||
}
|
||||
BB_DBG(bb, DBG_INIT, "h_size = %d, h_idx = %d\n", h_size, h_idx);
|
||||
|
||||
if (h_size != 0) {
|
||||
cfg_target = array[h_idx << 1] & 0x0fffffff;
|
||||
}
|
||||
|
||||
i += h_size;
|
||||
|
||||
BB_DBG(bb, DBG_INIT, "cfg_target = 0x%x\n", cfg_target);
|
||||
BB_DBG(bb, DBG_INIT, "array[i] = 0x%x, array[i+1] = 0x%x\n", array[i], array[i + 1]);
|
||||
|
||||
halbb_flag_2_default_8852c(&is_matched, &find_target);
|
||||
#ifdef HALBB_FW_OFLD_SUPPORT
|
||||
if (halbb_check_fw_ofld(bb))
|
||||
BB_DBG(bb, DBG_FW_INFO, "Becareful it is fwofld mode in BB init !!\n");
|
||||
#endif
|
||||
while ((i + 1) < array_len) {
|
||||
v1 = array[i];
|
||||
v2 = array[i + 1];
|
||||
i += 2;
|
||||
|
||||
switch (v1 >> 28) {
|
||||
case IF_8852C:
|
||||
case ELSE_IF_8852C:
|
||||
cfg_para = v1 & 0x0fffffff;
|
||||
BB_DBG(bb, DBG_INIT, "*if (rfe=%d, cart=%d)\n",
|
||||
(cfg_para & 0xff0000) >> 16, cfg_para & 0xff);
|
||||
break;
|
||||
case ELSE_8852C:
|
||||
BB_DBG(bb, DBG_INIT, "*else\n");
|
||||
is_matched = false;
|
||||
if (!find_target) {
|
||||
BB_WARNING("Init BBCR Fail in Reg 0x%x\n", array[i]);
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
case END_8852C:
|
||||
BB_DBG(bb, DBG_INIT, "*endif\n");
|
||||
halbb_flag_2_default_8852c(&is_matched, &find_target);
|
||||
break;
|
||||
case CHK_8852C:
|
||||
/*Check this para meets driver's requirement or not*/
|
||||
if (find_target) {
|
||||
BB_DBG(bb, DBG_INIT, "\t skip\n");
|
||||
is_matched = false;
|
||||
break;
|
||||
}
|
||||
|
||||
if (cfg_para == cfg_target) {
|
||||
is_matched = true;
|
||||
find_target = true;
|
||||
} else {
|
||||
is_matched = false;
|
||||
find_target = false;
|
||||
}
|
||||
BB_DBG(bb, DBG_INIT, "\t match=%d\n", is_matched);
|
||||
break;
|
||||
default:
|
||||
if (is_matched)
|
||||
#if 0//def HALBB_FW_OFLD_SUPPORT
|
||||
ret = halbb_fwcfg_bb_phy_8852c(bb, v1, v2, phy_idx);
|
||||
#else
|
||||
halbb_cfg_bb_phy_8852c(bb, v1, v2, phy_idx);
|
||||
#endif
|
||||
break;
|
||||
}
|
||||
}
|
||||
BB_DBG(bb, DBG_INIT, "BBCR Init Success\n\n");
|
||||
return true;
|
||||
}
|
||||
|
||||
bool halbb_cfg_bb_gain_ax_8852c(struct bb_info *bb, bool is_form_folder,
|
||||
u32 folder_len, u32 *folder_array)
|
||||
{
|
||||
bool is_matched, find_target;
|
||||
u32 cfg_target = 0, cfg_para = 0;
|
||||
u32 i = 0;
|
||||
u32 array_len = 0;
|
||||
u32 *array = NULL;
|
||||
u32 v1 = 0, v2 = 0;
|
||||
u8 h_size = 0;
|
||||
u8 h_idx = 0;
|
||||
|
||||
BB_DBG(bb, DBG_INIT, "===> %s\n", __func__);
|
||||
|
||||
if (is_form_folder) {
|
||||
array_len = folder_len;
|
||||
array = folder_array;
|
||||
} else {
|
||||
array_len = sizeof(array_mp_8852c_phy_reg_gain) / sizeof(u32);
|
||||
array = (u32 *)array_mp_8852c_phy_reg_gain;
|
||||
}
|
||||
|
||||
if (is_form_folder) {
|
||||
array_len = folder_len;
|
||||
array = folder_array;
|
||||
} else if (bb->ic_sub_type == BB_IC_SUB_TYPE_8852C_8852C) {
|
||||
array_len = sizeof(array_mp_8852c_phy_reg_gain) / sizeof(u32);
|
||||
array = (u32 *)array_mp_8852c_phy_reg_gain;
|
||||
} else if (bb->ic_sub_type == BB_IC_SUB_TYPE_8852C_8852D) {
|
||||
array_len = sizeof(array_mp_8852d_phy_reg_gain) / sizeof(u32);
|
||||
array = (u32 *)array_mp_8852d_phy_reg_gain;
|
||||
} else if ((bb->ic_sub_type == BB_IC_SUB_TYPE_8852C_8842A) ||
|
||||
(bb->ic_sub_type == BB_IC_SUB_TYPE_8852C_8842A_6967A)) {
|
||||
array_len = sizeof(array_mp_8842a_phy_reg_gain) / sizeof(u32);
|
||||
array = (u32 *)array_mp_8842a_phy_reg_gain;
|
||||
}
|
||||
|
||||
BB_DBG(bb, DBG_INIT, "GAIN_TABLE_form_folder=%d, len=%d\n",
|
||||
is_form_folder, array_len);
|
||||
|
||||
if (!halbb_sel_headline(bb, array, array_len, &h_size, &h_idx)) {
|
||||
BB_WARNING("[%s]Invalid BB CR Pkg\n", __func__);
|
||||
return false;
|
||||
}
|
||||
BB_DBG(bb, DBG_INIT, "h_size = %d, h_idx = %d\n", h_size, h_idx);
|
||||
|
||||
if (h_size != 0) {
|
||||
cfg_target = array[h_idx << 1] & 0x0fffffff;
|
||||
}
|
||||
|
||||
i += h_size;
|
||||
|
||||
BB_DBG(bb, DBG_INIT, "cfg_target = 0x%x\n", cfg_target);
|
||||
BB_DBG(bb, DBG_INIT, "array[i] = 0x%x, array[i+1] = 0x%x\n", array[i], array[i + 1]);
|
||||
|
||||
halbb_flag_2_default_8852c(&is_matched, &find_target);
|
||||
while ((i + 1) < array_len) {
|
||||
v1 = array[i];
|
||||
v2 = array[i + 1];
|
||||
i += 2;
|
||||
|
||||
switch (v1 >> 28) {
|
||||
case IF_8852C:
|
||||
case ELSE_IF_8852C:
|
||||
cfg_para = v1 & 0x0fffffff;
|
||||
BB_DBG(bb, DBG_INIT, "*if (rfe=%d, cart=%d)\n",
|
||||
(cfg_para & 0xff0000) >> 16, cfg_para & 0xff);
|
||||
break;
|
||||
case ELSE_8852C:
|
||||
BB_DBG(bb, DBG_INIT, "*else\n");
|
||||
is_matched = false;
|
||||
if (!find_target) {
|
||||
BB_WARNING("Init BBCR Fail in Reg 0x%x\n", array[i]);
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
case END_8852C:
|
||||
BB_DBG(bb, DBG_INIT, "*endif\n");
|
||||
halbb_flag_2_default_8852c(&is_matched, &find_target);
|
||||
break;
|
||||
case CHK_8852C:
|
||||
/*Check this para meets driver's requirement or not*/
|
||||
if (find_target) {
|
||||
BB_DBG(bb, DBG_INIT, "\t skip\n");
|
||||
is_matched = false;
|
||||
break;
|
||||
}
|
||||
|
||||
if (cfg_para == cfg_target) {
|
||||
is_matched = true;
|
||||
find_target = true;
|
||||
} else {
|
||||
is_matched = false;
|
||||
find_target = false;
|
||||
}
|
||||
BB_DBG(bb, DBG_INIT, "\t match=%d\n", is_matched);
|
||||
break;
|
||||
default:
|
||||
if (is_matched)
|
||||
halbb_cfg_bb_gain_8852c(bb, v1, v2);
|
||||
break;
|
||||
}
|
||||
}
|
||||
BB_DBG(bb, DBG_INIT, "BBCR gain Init Success\n\n");
|
||||
return true;
|
||||
}
|
||||
|
||||
u32
|
||||
halbb_get_8852c_phy_reg_ver(void)
|
||||
{
|
||||
return (u32)BB_REG_RELEASE_VERSION_8852C;
|
||||
}
|
||||
|
||||
#endif /* end of HWIMG_SUPPORT*/
|
||||
|
||||
@@ -0,0 +1,50 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in the
|
||||
* file called LICENSE.
|
||||
*
|
||||
* Contact Information:
|
||||
* wlanfae <wlanfae@realtek.com>
|
||||
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
|
||||
* Hsinchu 300, Taiwan.
|
||||
*
|
||||
* Larry Finger <Larry.Finger@lwfinger.net>
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef _HALBB_HW_IMG_8852C_H_
|
||||
#define _HALBB_HW_IMG_8852C_H_
|
||||
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
* phy_reg.TXT
|
||||
******************************************************************************/
|
||||
#define DONT_CARE_8852C 0xff
|
||||
|
||||
#define IF_8852C 0x8
|
||||
#define ELSE_IF_8852C 0x9
|
||||
#define ELSE_8852C 0xa
|
||||
#define END_8852C 0xb
|
||||
#define CHK_8852C 0x4
|
||||
|
||||
bool halbb_cfg_bbcr_ax_8852c(struct bb_info *bb, bool is_form_folder,
|
||||
u32 folder_len, u32 *folder_array,
|
||||
enum phl_phy_idx phy_idx);
|
||||
bool halbb_cfg_bb_gain_ax_8852c(struct bb_info *bb, bool is_form_folder,
|
||||
u32 folder_len, u32 *folder_array);
|
||||
u32 halbb_get_8852c_phy_reg_ver(void);
|
||||
|
||||
#endif /* end of HWIMG_SUPPORT*/
|
||||
|
||||
@@ -0,0 +1,116 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2020 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in the
|
||||
* file called LICENSE.
|
||||
*
|
||||
* Contact Information:
|
||||
* wlanfae <wlanfae@realtek.com>
|
||||
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
|
||||
* Hsinchu 300, Taiwan.
|
||||
*
|
||||
* Larry Finger <Larry.Finger@lwfinger.net>
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
/*Image2HeaderVersion: R3 2.0.2.0*/
|
||||
#ifndef _HALBB_HWIMG_BAND_SWH_8852d_H
|
||||
#define _HALBB_HWIMG_BAND_SWH_8852d_H
|
||||
|
||||
#ifdef HALBB_BAND_SWH_CR_SEQ_SUPPORT
|
||||
|
||||
const u32 array_mp_8852d_band_swh[] = {
|
||||
0x8100724, 0x00111200,
|
||||
0x81046AC, 0x60423537,
|
||||
0x81046BC, 0x5107C252,
|
||||
0x8104720, 0x3FFFFD63,
|
||||
0x8104724, 0xB58D11FF,
|
||||
0x8104730, 0xE0399201,
|
||||
0x8104738, 0x8325C500,
|
||||
0x8104798, 0x000001D3,
|
||||
0x81047C8, 0x56767578,
|
||||
0x810481C, 0x576DF814,
|
||||
0x810484C, 0x0000CA62,
|
||||
0x81048D4, 0x576DF814,
|
||||
0x8104A60, 0x60423537,
|
||||
0x8104A70, 0x5107C252,
|
||||
0x8104A74, 0x3FFFFD63,
|
||||
0x8104A78, 0xB58D11FF,
|
||||
0x8104A9C, 0xE0399201,
|
||||
0x8104AA4, 0x8325C500,
|
||||
0x8104BE4, 0xBAAC8000,
|
||||
0x8104CA8, 0xBAAC8000,
|
||||
0x8104D2C, 0x0008C0C1,
|
||||
0x8104D34, 0x7BB167AB,
|
||||
0x81058B0, 0x00000800,
|
||||
0x8105A24, 0x00050000,
|
||||
0x8105A44, 0x00000005,
|
||||
0x8105A60, 0x00050000,
|
||||
0x8105AB0, 0x00050005,
|
||||
0x8105AB4, 0x00050005,
|
||||
0x8105AB8, 0x00050005,
|
||||
0x8105ABC, 0x00050005,
|
||||
0x8105AC0, 0x00000005,
|
||||
0x81078B0, 0x00000800,
|
||||
0x8107A24, 0x00050000,
|
||||
0x8107A44, 0x00000005,
|
||||
0x8107A60, 0x00050000,
|
||||
0x8107AB0, 0x00050005,
|
||||
0x8107AB4, 0x00050005,
|
||||
0x8107AB8, 0x00050005,
|
||||
0x8107ABC, 0x00050005,
|
||||
0x8107AC0, 0x00000005,
|
||||
0x8600724, 0x01100100,
|
||||
0x86046AC, 0xA0423537,
|
||||
0x86046BC, 0x510FC252,
|
||||
0x8604720, 0x7FFFFD63,
|
||||
0x8604724, 0x758D11FF,
|
||||
0x8604730, 0xE0389201,
|
||||
0x8604738, 0x8F25C500,
|
||||
0x8604798, 0x000000D3,
|
||||
0x86047C8, 0x55757478,
|
||||
0x860481C, 0x5765F814,
|
||||
0x860484C, 0x00008A62,
|
||||
0x86048D4, 0x576BF814,
|
||||
0x8604A60, 0xA0423537,
|
||||
0x8604A70, 0x510FC252,
|
||||
0x8604A74, 0x7FFFFD63,
|
||||
0x8604A78, 0x758D11FF,
|
||||
0x8604A9C, 0xE0389201,
|
||||
0x8604AA4, 0x8F25C500,
|
||||
0x8604BE4, 0xD5640000,
|
||||
0x8604CA8, 0xD5640000,
|
||||
0x8604D2C, 0x0008C8C1,
|
||||
0x8604D34, 0x7BB1579A,
|
||||
0x86058B0, 0x00000000,
|
||||
0x8605A24, 0x00000000,
|
||||
0x8605A44, 0x00000000,
|
||||
0x8605A60, 0x00000000,
|
||||
0x8605AB0, 0x00000000,
|
||||
0x8605AB4, 0x00000000,
|
||||
0x8605AB8, 0x00000000,
|
||||
0x8605ABC, 0x00000000,
|
||||
0x8605AC0, 0x00000000,
|
||||
0x86078B0, 0x00000000,
|
||||
0x8607A24, 0x00000000,
|
||||
0x8607A44, 0x00000000,
|
||||
0x8607A60, 0x00000000,
|
||||
0x8607AB0, 0x00000000,
|
||||
0x8607AB4, 0x00000000,
|
||||
0x8607AB8, 0x00000000,
|
||||
0x8607ABC, 0x00000000,
|
||||
0x8607AC0, 0x00000000
|
||||
};
|
||||
#endif
|
||||
|
||||
#endif /* _HALBB_HWIMG_BAND_SWH_8852d_H */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,240 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in the
|
||||
* file called LICENSE.
|
||||
*
|
||||
* Contact Information:
|
||||
* wlanfae <wlanfae@realtek.com>
|
||||
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
|
||||
* Hsinchu 300, Taiwan.
|
||||
*
|
||||
* Larry Finger <Larry.Finger@lwfinger.net>
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#include "../halbb_precomp.h"
|
||||
#ifdef BB_8852C_SUPPORT
|
||||
|
||||
void halbb_cfg_rf_reg_8852c(struct bb_info *bb, u32 addr, u32 data,
|
||||
enum rf_path rf_path, u32 reg_addr)
|
||||
{
|
||||
}
|
||||
|
||||
void halbb_cfg_rf_radio_a_8852c(struct bb_info *bb, u32 addr, u32 data)
|
||||
{
|
||||
}
|
||||
|
||||
void halbb_cfg_rf_radio_b_8852c(struct bb_info *bb, u32 addr, u32 data)
|
||||
{
|
||||
}
|
||||
|
||||
void halbb_cfg_bb_phy_8852c(struct bb_info *bb, u32 addr, u32 data,
|
||||
enum phl_phy_idx phy_idx)
|
||||
{
|
||||
#ifdef HALBB_DBCC_SUPPORT
|
||||
u32 ofst = 0;
|
||||
#endif
|
||||
|
||||
if (addr == 0xfe) {
|
||||
halbb_delay_ms(bb, 50);
|
||||
BB_DBG(bb, DBG_INIT, "Delay 50 ms\n");
|
||||
} else if (addr == 0xfd) {
|
||||
halbb_delay_ms(bb, 5);
|
||||
BB_DBG(bb, DBG_INIT, "Delay 5 ms\n");
|
||||
} else if (addr == 0xfc) {
|
||||
halbb_delay_ms(bb, 1);
|
||||
BB_DBG(bb, DBG_INIT, "Delay 1 ms\n");
|
||||
} else if (addr == 0xfb) {
|
||||
halbb_delay_us(bb, 50);
|
||||
BB_DBG(bb, DBG_INIT, "Delay 50 us\n");
|
||||
} else if (addr == 0xfa) {
|
||||
halbb_delay_us(bb, 5);
|
||||
BB_DBG(bb, DBG_INIT, "Delay 5 us\n");
|
||||
} else if (addr == 0xf9) {
|
||||
halbb_delay_us(bb, 1);
|
||||
BB_DBG(bb, DBG_INIT, "Delay 1 us\n");
|
||||
} else {
|
||||
#ifdef HALBB_DBCC_SUPPORT
|
||||
if ((bb->hal_com->dbcc_en || bb->bb_dbg_i.cr_dbg_mode_en) &&
|
||||
phy_idx == HW_PHY_1) {
|
||||
ofst = halbb_phy0_to_phy1_ofst(bb, addr, phy_idx);
|
||||
if (ofst == 0)
|
||||
return;
|
||||
addr += ofst;
|
||||
} else {
|
||||
phy_idx = HW_PHY_0;
|
||||
}
|
||||
//if (phy_idx == HW_PHY_1)
|
||||
// BB_DBG(bb, DBG_DBCC, "[REG][%d]0x%04X = 0x%08X\n", phy_idx, addr, data);
|
||||
#else
|
||||
BB_DBG(bb, DBG_INIT, "[REG]0x%04X = 0x%08X\n", addr, data);
|
||||
#endif
|
||||
|
||||
halbb_set_reg(bb, addr, MASKDWORD, data);
|
||||
}
|
||||
}
|
||||
|
||||
void halbb_cfg_bb_gain_8852c(struct bb_info *bb, u32 addr, u32 data)
|
||||
{
|
||||
struct bb_gain_info *gain = &bb->bb_gain_i;
|
||||
u8 cfg_type = (u8)((addr & 0xff000000) >> 24);
|
||||
enum bb_band_t band_idx = (enum bb_band_t)((addr & 0xff0000) >> 16);
|
||||
u8 path = (u8)((addr & 0xff00) >> 8);
|
||||
u8 type;
|
||||
u8 i = 0;
|
||||
|
||||
if (band_idx >= BB_GAIN_BAND_NUM)
|
||||
return;
|
||||
|
||||
if (path >= HALBB_MAX_PATH)
|
||||
return;
|
||||
|
||||
if (addr == 0xfe) {
|
||||
halbb_delay_ms(bb, 50);
|
||||
BB_DBG(bb, DBG_INIT, "Delay 50 ms\n");
|
||||
} else if (addr == 0xfd) {
|
||||
halbb_delay_ms(bb, 5);
|
||||
BB_DBG(bb, DBG_INIT, "Delay 5 ms\n");
|
||||
} else if (addr == 0xfc) {
|
||||
halbb_delay_ms(bb, 1);
|
||||
BB_DBG(bb, DBG_INIT, "Delay 1 ms\n");
|
||||
} else if (addr == 0xfb) {
|
||||
halbb_delay_us(bb, 50);
|
||||
BB_DBG(bb, DBG_INIT, "Delay 50 us\n");
|
||||
} else if (addr == 0xfa) {
|
||||
halbb_delay_us(bb, 5);
|
||||
BB_DBG(bb, DBG_INIT, "Delay 5 us\n");
|
||||
} else if (addr == 0xf9) {
|
||||
halbb_delay_us(bb, 1);
|
||||
BB_DBG(bb, DBG_INIT, "Delay 1 us\n");
|
||||
} else if (cfg_type == 0) { /*GAIN ERROR*/
|
||||
type = (u8)(addr & 0xff);
|
||||
if (type == 0) {
|
||||
for (i = 0; i < 4; i++)
|
||||
gain->lna_gain[band_idx][path][i] = (data >> (8 * i)) & 0xff;
|
||||
} else if (type == 1) {
|
||||
for (i = 0; i < 3; i++)
|
||||
gain->lna_gain[band_idx][path][4 + i] = (data >> (8 * i)) & 0xff;
|
||||
} else if (type == 2) {
|
||||
for (i = 0; i < 2; i++)
|
||||
gain->tia_gain[band_idx][path][i] = (data >> (8 * i)) & 0xff;
|
||||
}
|
||||
|
||||
if ((band_idx >= 4) && (band_idx <= 7)) { /*Avoid phy_reg_gain does not support band_idx 8~11*/
|
||||
if (type == 0) {
|
||||
for (i = 0; i < 4; i++)
|
||||
gain->lna_gain[band_idx + 4][path][i] = (data >> (8 * i)) & 0xff;
|
||||
} else if (type == 1) {
|
||||
for (i = 0; i < 3; i++)
|
||||
gain->lna_gain[band_idx + 4][path][4 + i] = (data >> (8 * i)) & 0xff;
|
||||
} else if (type == 2) {
|
||||
for (i = 0; i < 2; i++)
|
||||
gain->tia_gain[band_idx + 4][path][i] = (data >> (8 * i)) & 0xff;
|
||||
}
|
||||
}
|
||||
} else if (cfg_type == 1) { /*RPL Offset*/
|
||||
halbb_cfg_bb_rpl_ofst(bb, band_idx, path, addr, data);
|
||||
if ((band_idx >= 4) && (band_idx <= 7)) /*Avoid phy_reg_gain does not support band_idx 8~11*/
|
||||
halbb_cfg_bb_rpl_ofst(bb, band_idx + 4, path, addr, data);
|
||||
} else if (cfg_type == 2) { /*Bypass Mode GAIN ERROR*/
|
||||
type = (u8)(addr & 0xff);
|
||||
if (type == 0) {
|
||||
for (i = 0; i < 4; i++)
|
||||
gain->lna_gain_bypass[band_idx][path][i] = (data >> (8 * i)) & 0xff;
|
||||
} else if (type == 1) {
|
||||
for (i = 0; i < 3; i++)
|
||||
gain->lna_gain_bypass[band_idx][path][4 + i] = (data >> (8 * i)) & 0xff;
|
||||
}
|
||||
|
||||
if ((band_idx >= 4) && (band_idx <= 7)) { /*Avoid phy_reg_gain does not support band_idx 8~11*/
|
||||
if (type == 0) {
|
||||
for (i = 0; i < 4; i++)
|
||||
gain->lna_gain_bypass[band_idx + 4][path][i] = (data >> (8 * i)) & 0xff;
|
||||
} else if (type == 1) {
|
||||
for (i = 0; i < 3; i++)
|
||||
gain->lna_gain_bypass[band_idx + 4][path][4 + i] = (data >> (8 * i)) & 0xff;
|
||||
}
|
||||
}
|
||||
} else if (cfg_type == 3) { /*op1dB values*/
|
||||
type = (u8)(addr & 0xff);
|
||||
if (type == 0) {
|
||||
for (i = 0; i < 4; i++)
|
||||
gain->lna_op1db[band_idx][path][i] = (data >> (8 * i)) & 0xff;
|
||||
} else if (type == 1) {
|
||||
for (i = 0; i < 3; i++)
|
||||
gain->lna_op1db[band_idx][path][4 + i] = (data >> (8 * i)) & 0xff;
|
||||
} else if (type == 2) {
|
||||
for (i = 0; i < 4; i++)
|
||||
gain->tia_lna_op1db[band_idx][path][i] = (data >> (8 * i)) & 0xff;
|
||||
} else if (type == 3) {
|
||||
for (i = 0; i < 4; i++)
|
||||
gain->tia_lna_op1db[band_idx][path][4 + i] = (data >> (8 * i)) & 0xff;
|
||||
}
|
||||
|
||||
if ((band_idx >= 4) && (band_idx <= 7)) { /*Avoid phy_reg_gain does not support band_idx 8~11*/
|
||||
if (type == 0) {
|
||||
for (i = 0; i < 4; i++)
|
||||
gain->lna_op1db[band_idx + 4][path][i] = (data >> (8 * i)) & 0xff;
|
||||
} else if (type == 1) {
|
||||
for (i = 0; i < 3; i++)
|
||||
gain->lna_op1db[band_idx + 4][path][4 + i] = (data >> (8 * i)) & 0xff;
|
||||
} else if (type == 2) {
|
||||
for (i = 0; i < 4; i++)
|
||||
gain->tia_lna_op1db[band_idx + 4][path][i] = (data >> (8 * i)) & 0xff;
|
||||
} else if (type == 3) {
|
||||
for (i = 0; i < 4; i++)
|
||||
gain->tia_lna_op1db[band_idx + 4][path][4 + i] = (data >> (8 * i)) & 0xff;
|
||||
}
|
||||
}
|
||||
} else if (cfg_type == 4) { /*WB_GIDX & GS IDX*/
|
||||
type = (u8)(addr & 0xff);
|
||||
if (type == 0)
|
||||
gain->wb_gidx_elna[band_idx][path] = data;
|
||||
else if (type == 1)
|
||||
for (i = 0; i < 8; i++)
|
||||
gain->wb_gidx_lna_tia[band_idx][path][i] = (data >> (4 * i)) & 0x7;
|
||||
else if (type == 2)
|
||||
for (i = 0; i < 8; i++)
|
||||
gain->wb_gidx_lna_tia[band_idx][path][i + 8] = (data >> (4 * i)) & 0x7;
|
||||
else if (type == 3)
|
||||
gain->gs_idx[band_idx][path][0] = data;
|
||||
else if (type == 4)
|
||||
gain->gs_idx[band_idx][path][1] = data;
|
||||
else if (type == 5)
|
||||
for (i = 0; i < 2; i++)
|
||||
gain->g_elna[band_idx][path][i] = (data >> (8 * i)) & 0xff;
|
||||
|
||||
if ((band_idx >= 4) && (band_idx <= 7)) { /*Avoid phy_reg_gain does not support band_idx 8~11*/
|
||||
if (type == 0)
|
||||
gain->wb_gidx_elna[band_idx + 4][path] = data;
|
||||
else if (type == 1)
|
||||
for (i = 0; i < 8; i++)
|
||||
gain->wb_gidx_lna_tia[band_idx + 4][path][i] = (data >> (4 * i)) & 0x7;
|
||||
else if (type == 2)
|
||||
for (i = 0; i < 8; i++)
|
||||
gain->wb_gidx_lna_tia[band_idx + 4][path][i + 8] = (data >> (4 * i)) & 0x7;
|
||||
else if (type == 3)
|
||||
gain->gs_idx[band_idx + 4][path][0] = data;
|
||||
else if (type == 4)
|
||||
gain->gs_idx[band_idx + 4][path][1] = data;
|
||||
else if (type == 5)
|
||||
for (i = 0; i < 2; i++)
|
||||
gain->g_elna[band_idx + 4][path][i] = (data >> (8 * i)) & 0xff;
|
||||
}
|
||||
} else {
|
||||
BB_WARNING("cfg_type=%d\n", cfg_type);
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,36 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in the
|
||||
* file called LICENSE.
|
||||
*
|
||||
* Contact Information:
|
||||
* wlanfae <wlanfae@realtek.com>
|
||||
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
|
||||
* Hsinchu 300, Taiwan.
|
||||
*
|
||||
* Larry Finger <Larry.Finger@lwfinger.net>
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef _HALBB_REG_CFG_8852C_H_
|
||||
#define _HALBB_REG_CFG_8852C_H_
|
||||
|
||||
#ifdef BB_8852C_SUPPORT
|
||||
|
||||
void halbb_cfg_bb_phy_8852c(struct bb_info *bb, u32 addr, u32 data,
|
||||
enum phl_phy_idx phy_idx);
|
||||
|
||||
void halbb_cfg_bb_gain_8852c(struct bb_info *bb, u32 addr, u32 data);
|
||||
|
||||
#endif
|
||||
#endif /* RTL8822C_SUPPORT*/
|
||||
@@ -0,0 +1,30 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in the
|
||||
* file called LICENSE.
|
||||
*
|
||||
* Contact Information:
|
||||
* wlanfae <wlanfae@realtek.com>
|
||||
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
|
||||
* Hsinchu 300, Taiwan.
|
||||
*
|
||||
* Larry Finger <Larry.Finger@lwfinger.net>
|
||||
*
|
||||
*****************************************************************************/
|
||||
/*RTL8842A BB Parameters*/
|
||||
#ifndef _HALBB_VERSION_8842A_H_
|
||||
#define _HALBB_VERSION_8842A_H_
|
||||
#define BB_REG_RELEASE_DATE_8842A 20240201
|
||||
#define BB_REG_RELEASE_VERSION_8842A 01
|
||||
#endif
|
||||
@@ -0,0 +1,30 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in the
|
||||
* file called LICENSE.
|
||||
*
|
||||
* Contact Information:
|
||||
* wlanfae <wlanfae@realtek.com>
|
||||
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
|
||||
* Hsinchu 300, Taiwan.
|
||||
*
|
||||
* Larry Finger <Larry.Finger@lwfinger.net>
|
||||
*
|
||||
*****************************************************************************/
|
||||
/*RTL8852C BB Parameters*/
|
||||
#ifndef _HALBB_VERSION_8852C_H_
|
||||
#define _HALBB_VERSION_8852C_H_
|
||||
#define BB_REG_RELEASE_DATE_8852C 20241113
|
||||
#define BB_REG_RELEASE_VERSION_8852C 62
|
||||
#endif
|
||||
@@ -0,0 +1,30 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in the
|
||||
* file called LICENSE.
|
||||
*
|
||||
* Contact Information:
|
||||
* wlanfae <wlanfae@realtek.com>
|
||||
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
|
||||
* Hsinchu 300, Taiwan.
|
||||
*
|
||||
* Larry Finger <Larry.Finger@lwfinger.net>
|
||||
*
|
||||
*****************************************************************************/
|
||||
/*RTL8852D BB Parameters*/
|
||||
#ifndef _HALBB_VERSION_8852D_H_
|
||||
#define _HALBB_VERSION_8852D_H_
|
||||
#define BB_REG_RELEASE_DATE_8852D 20250424
|
||||
#define BB_REG_RELEASE_VERSION_8852D 28
|
||||
#endif
|
||||
+402
@@ -0,0 +1,402 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2020 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in the
|
||||
* file called LICENSE.
|
||||
*
|
||||
* Contact Information:
|
||||
* wlanfae <wlanfae@realtek.com>
|
||||
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
|
||||
* Hsinchu 300, Taiwan.
|
||||
*
|
||||
* Larry Finger <Larry.Finger@lwfinger.net>
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __HALBB_ANT_DIV_H__
|
||||
#define __HALBB_ANT_DIV_H__
|
||||
|
||||
/*@--------------------------[Define] ---------------------------------------*/
|
||||
#define EVM_BASED_ANTDIV 0
|
||||
#define CN_BASED_ANTDIV 1
|
||||
|
||||
#define TP_MAX_DOMINATION 0
|
||||
#define TP_HIGHEST_DOMINATION 1
|
||||
#define TP_AVG_DOMINATION 2
|
||||
|
||||
#define ANTDIV_INIT 0xff
|
||||
#define MAIN_ANT 1 /*@ant A or ant Main or S1*/
|
||||
#define AUX_ANT 2 /*@AntB or ant Aux or S0*/
|
||||
#define MAX_ANT 3 /* @3 for AP using*/
|
||||
|
||||
#define ANT1_2G 0
|
||||
/* @= ANT2_5G for 8723D BTG S1 RX S0S1 diversity for 8723D, TX fixed at S1 */
|
||||
#define ANT2_2G 1
|
||||
/* @= ANT1_5G for 8723D BTG S0 RX S0S1 diversity for 8723D, TX fixed at S1 */
|
||||
|
||||
#define ANTDIV_MAX_STA_NUM PHL_MAX_STA_NUM
|
||||
#define ANTDIV_RSSI_TH_HIGH 30
|
||||
#define ANTDIV_RSSI_TH_LOW 20
|
||||
#define ANTDIV_PERIOD 1
|
||||
#define ANTDIV_TRAINING_NUM 2
|
||||
#define ANTDIV_NOTRAINING_NUM 3
|
||||
|
||||
#define FORCE_RSSI_DIFF 10
|
||||
|
||||
#define ANTDIV_DELAY 110
|
||||
#define ANTDIV_INTVL 30
|
||||
|
||||
#define ANTDIV_DEC_TP_HIGH 100
|
||||
#define ANTDIV_DEC_TP_LOW 5
|
||||
#define ANTDIV_DEC_EVM 8
|
||||
#define ANTDIV_DEC_EVM_1SS 8
|
||||
#define TP_LOWER_BOUND 1
|
||||
|
||||
/*parameter for 1ss rssi-based antdiv*/
|
||||
#define ANTDIV_PERIOD_1SS 1
|
||||
#define ANTDIV_TRAINING_NUM_1SS 2
|
||||
#define ANTDIV_DELAY_1SS 1
|
||||
#define ANTDIV_INTVL_1SS 10
|
||||
#define ANTDIV_DEC_RSSI 3
|
||||
#define ANTDIV_FIXANT_RSSI 2
|
||||
|
||||
/* @Antenna Diversty Control type */
|
||||
#define ODM_AUTO_ANT 0
|
||||
#define ODM_FIX_MAIN_ANT 1
|
||||
#define ODM_FIX_AUX_ANT 2
|
||||
|
||||
#define ANTDIV_ON 1
|
||||
#define ANTDIV_OFF 0
|
||||
|
||||
#define ANT_PATH_A 0
|
||||
#define ANT_PATH_B 1
|
||||
#define ANT_PATH_AB 2
|
||||
|
||||
/*@--------------------------[Enum]------------------------------------------*/
|
||||
enum bb_antdiv_mode_t {
|
||||
AUTO_ANT = 0,
|
||||
FIX_MAIN_ANT = 1,
|
||||
FIX_AUX_ANT = 2,
|
||||
};
|
||||
|
||||
enum bb_tp_method_t {
|
||||
TP_MAX = 0,
|
||||
TP_HIGHEST = 1,
|
||||
TP_AVG = 2,
|
||||
};
|
||||
|
||||
enum bb_evm_method_t {
|
||||
EVM_LINEAR_AVG = 0,
|
||||
EVM_DB_AVG = 1,
|
||||
};
|
||||
|
||||
enum bb_antdiv_method_t {
|
||||
EVM_BASED = 0,
|
||||
CN_BASED = 1,
|
||||
};
|
||||
|
||||
|
||||
/*@--------------------------[Structure]-------------------------------------*/
|
||||
|
||||
struct bb_antdiv_rssi_info { /*all in U(8,1)*/
|
||||
/*acc value*/
|
||||
u32 rssi_cck_avg_acc;
|
||||
u32 rssi_ofdm_avg_acc;
|
||||
u32 rssi_t_avg_acc;
|
||||
u8 rssi_cck_avg;
|
||||
u8 rssi_ofdm_avg;
|
||||
u8 rssi_t_avg;
|
||||
u8 rssi_final;
|
||||
u16 pkt_cnt_t;
|
||||
u16 pkt_cnt_cck;
|
||||
u16 pkt_cnt_ofdm;
|
||||
|
||||
u32 main_rssi_cck_avg_acc;
|
||||
u32 main_rssi_ofdm_avg_acc;
|
||||
u32 main_rssi_t_avg_acc;
|
||||
u8 main_rssi_cck_avg;
|
||||
u8 main_rssi_ofdm_avg;
|
||||
u8 main_rssi_t_avg;
|
||||
u8 main_rssi_final;
|
||||
u16 main_pkt_cnt_t;
|
||||
u16 main_pkt_cnt_cck;
|
||||
u16 main_pkt_cnt_ofdm;
|
||||
|
||||
u32 aux_rssi_cck_avg_acc;
|
||||
u32 aux_rssi_ofdm_avg_acc;
|
||||
u32 aux_rssi_t_avg_acc;
|
||||
u8 aux_rssi_cck_avg;
|
||||
u8 aux_rssi_ofdm_avg;
|
||||
u8 aux_rssi_t_avg;
|
||||
u8 aux_rssi_final;
|
||||
u16 aux_pkt_cnt_t;
|
||||
u16 aux_pkt_cnt_cck;
|
||||
u16 aux_pkt_cnt_ofdm;
|
||||
|
||||
u8 rssi_diff;
|
||||
bool no_change_flag;
|
||||
};
|
||||
|
||||
struct bb_antdiv_cn_info {
|
||||
u32 main_cn_avg_acc; /*U(7,1)*/
|
||||
u32 aux_cn_avg_acc; /*U(7,1)*/
|
||||
};
|
||||
|
||||
struct bb_antdiv_evm_info {
|
||||
u32 main_evm_1ss;/*U(8,2)*/ /*only for 1SS & L-OFDM*/
|
||||
u32 main_evm_min_acc; /*U(8,2)*/ /*only for >= 2SS*/
|
||||
u32 main_evm_max_acc; /*U(8,2)*/ /*only for >= 2SS*/
|
||||
u32 aux_evm_1ss;/*U(8,2)*/ /*only for 1SS & L-OFDM*/
|
||||
u32 aux_evm_min_acc; /*U(8,2)*/ /*only for >= 2SS*/
|
||||
u32 aux_evm_max_acc; /*U(8,2)*/ /*only for >= 2SS*/
|
||||
u8 evm_diff;
|
||||
bool no_change_flag;
|
||||
};
|
||||
|
||||
struct bb_antdiv_rate_info {
|
||||
/*====[Phy rate counter main ant]=============================================*/
|
||||
u16 main_pkt_cnt_cck;
|
||||
u16 main_pkt_cnt_ofdm; /*L-OFDM*/
|
||||
u16 main_pkt_cnt_t; /*HT, VHT, HE = pkt_cnt_1ss + pkt_cnt_2ss*/
|
||||
u16 main_pkt_cnt_1ss; /*HT, VHT, HE*/
|
||||
u16 main_pkt_cnt_2ss; /*HT, VHT, HE*/
|
||||
/*Legacy*/
|
||||
u16 main_pkt_cnt_legacy[LEGACY_RATE_NUM];
|
||||
/*HT*/
|
||||
u16 main_pkt_cnt_ht[HT_RATE_NUM];
|
||||
/*VHT*/
|
||||
u16 main_pkt_cnt_vht[VHT_RATE_NUM];
|
||||
/*HE*/
|
||||
u16 main_pkt_cnt_he[HE_RATE_NUM];
|
||||
/*Rxsc case*/
|
||||
u16 main_pkt_cnt_ht_sc20[HT_RATE_NUM];
|
||||
|
||||
u16 main_pkt_cnt_vht_sc20[VHT_RATE_NUM];
|
||||
u16 main_pkt_cnt_vht_sc40[VHT_RATE_NUM];
|
||||
u16 main_pkt_cnt_vht_sc80[VHT_RATE_NUM];
|
||||
|
||||
u16 main_pkt_cnt_he_sc20[HE_RATE_NUM];
|
||||
u16 main_pkt_cnt_he_sc40[HE_RATE_NUM];
|
||||
u16 main_pkt_cnt_he_sc80[HE_RATE_NUM];
|
||||
|
||||
u16 main_max_cnt;
|
||||
u16 main_max_idx;
|
||||
/*====[Phy rate counter] aux ant=============================================*/
|
||||
u16 aux_pkt_cnt_cck;
|
||||
u16 aux_pkt_cnt_ofdm; /*L-OFDM*/
|
||||
u16 aux_pkt_cnt_t; /*HT, VHT, HE = pkt_cnt_1ss + pkt_cnt_2ss*/
|
||||
u16 aux_pkt_cnt_1ss; /*HT, VHT, HE*/
|
||||
u16 aux_pkt_cnt_2ss; /*HT, VHT, HE*/
|
||||
/*Legacy*/
|
||||
u16 aux_pkt_cnt_legacy[LEGACY_RATE_NUM];
|
||||
/*HT*/
|
||||
u16 aux_pkt_cnt_ht[HT_RATE_NUM];
|
||||
/*VHT*/
|
||||
u16 aux_pkt_cnt_vht[VHT_RATE_NUM];
|
||||
/*HE*/
|
||||
u16 aux_pkt_cnt_he[HE_RATE_NUM];
|
||||
/*Rxsc case*/
|
||||
u16 aux_pkt_cnt_ht_sc20[HT_RATE_NUM];
|
||||
|
||||
u16 aux_pkt_cnt_vht_sc20[VHT_RATE_NUM];
|
||||
u16 aux_pkt_cnt_vht_sc40[VHT_RATE_NUM];
|
||||
u16 aux_pkt_cnt_vht_sc80[VHT_RATE_NUM];
|
||||
|
||||
u16 aux_pkt_cnt_he_sc20[HE_RATE_NUM];
|
||||
u16 aux_pkt_cnt_he_sc40[HE_RATE_NUM];
|
||||
u16 aux_pkt_cnt_he_sc80[HE_RATE_NUM];
|
||||
|
||||
u16 aux_max_cnt;
|
||||
u16 aux_max_idx;
|
||||
u16 main_cnt_all;
|
||||
u16 aux_cnt_all;
|
||||
|
||||
u32 main_tp;
|
||||
u32 aux_tp;
|
||||
u32 tp_diff;
|
||||
|
||||
bool no_change_flag;
|
||||
bool main_ht_pkt_not_zero;
|
||||
bool main_vht_pkt_not_zero;
|
||||
bool main_he_pkt_not_zero;
|
||||
bool aux_ht_pkt_not_zero;
|
||||
bool aux_vht_pkt_not_zero;
|
||||
bool aux_he_pkt_not_zero;
|
||||
|
||||
bool main_sc20_occur;
|
||||
bool main_sc40_occur;
|
||||
bool main_sc80_occur;
|
||||
bool aux_sc20_occur;
|
||||
bool aux_sc40_occur;
|
||||
bool aux_sc80_occur;
|
||||
};
|
||||
|
||||
struct bb_antdiv_cr_info {
|
||||
u32 path0_r_ant_train_en;
|
||||
u32 path0_r_ant_train_en_m;
|
||||
u32 path0_r_tx_ant_sel;
|
||||
u32 path0_r_tx_ant_sel_m;
|
||||
u32 path0_r_rfe_buf_en;
|
||||
u32 path0_r_rfe_buf_en_m;
|
||||
u32 path0_r_lnaon_agc;
|
||||
u32 path0_r_lnaon_agc_m;
|
||||
u32 path0_r_trsw_bit_bt;
|
||||
u32 path0_r_trsw_bit_bt_m;
|
||||
u32 path0_r_trsw_s;
|
||||
u32 path0_r_trsw_s_m;
|
||||
u32 path0_r_trsw_o;
|
||||
u32 path0_r_trsw_o_m;
|
||||
u32 path0_r_trswb_o;
|
||||
u32 path0_r_trswb_o_m;
|
||||
u32 path0_r_bt_force_antidx;
|
||||
u32 path0_r_bt_force_antidx_m;
|
||||
u32 path0_r_bt_force_antidx_en;
|
||||
u32 path0_r_bt_force_antidx_en_m;
|
||||
u32 path0_r_ant_module_rfe_opt;
|
||||
u32 path0_r_ant_module_rfe_opt_m;
|
||||
u32 path0_r_rfsw_tr;
|
||||
u32 path0_r_rfsw_tr_m;
|
||||
u32 path0_r_antsel;
|
||||
u32 path0_r_antsel_m;
|
||||
u32 path0_r_rfsw_ant_31_0;
|
||||
u32 path0_r_rfsw_ant_31_0_m;
|
||||
u32 path0_r_rfsw_ant_63_32;
|
||||
u32 path0_r_rfsw_ant_63_32_m;
|
||||
u32 path0_r_rfsw_ant_95_64;
|
||||
u32 path0_r_rfsw_ant_95_64_m;
|
||||
u32 path0_r_rfsw_ant_127_96;
|
||||
u32 path0_r_rfsw_ant_127_96_m;
|
||||
};
|
||||
|
||||
struct bb_sub_bw_tp_info {
|
||||
u32 main_max_tp_160;
|
||||
u32 main_max_tp_80;
|
||||
u32 main_max_tp_40;
|
||||
u32 main_max_tp_20;
|
||||
u32 aux_max_tp_160;
|
||||
u32 aux_max_tp_80;
|
||||
u32 aux_max_tp_40;
|
||||
u32 aux_max_tp_20;
|
||||
u16 main_max_cnt_160;
|
||||
u16 main_max_cnt_80;
|
||||
u16 main_max_cnt_40;
|
||||
u16 main_max_cnt_20;
|
||||
u16 aux_max_cnt_160;
|
||||
u16 aux_max_cnt_80;
|
||||
u16 aux_max_cnt_40;
|
||||
u16 aux_max_cnt_20;
|
||||
u16 main_max_idx_160;
|
||||
u16 main_max_idx_80;
|
||||
u16 main_max_idx_40;
|
||||
u16 main_max_idx_20;
|
||||
u16 aux_max_idx_160;
|
||||
u16 aux_max_idx_80;
|
||||
u16 aux_max_idx_40;
|
||||
u16 aux_max_idx_20;
|
||||
|
||||
u16 COUNT_MAIN_HE[4][HE_RATE_NUM];
|
||||
u16 COUNT_AUX_HE[4][HE_RATE_NUM];
|
||||
u16 COUNT_MAIN_VHT[4][VHT_RATE_NUM];
|
||||
u16 COUNT_AUX_VHT[4][VHT_RATE_NUM];
|
||||
u16 COUNT_MAIN_HT[2][HT_RATE_NUM];
|
||||
u16 COUNT_AUX_HT[2][HT_RATE_NUM];
|
||||
};
|
||||
|
||||
struct bb_antdiv_info {
|
||||
/* For CN cacluation */
|
||||
struct bb_antdiv_cn_info bb_cn_i;
|
||||
/* For EVM cacluation */
|
||||
struct bb_antdiv_evm_info bb_evm_i;
|
||||
/* For MCS cacluation */
|
||||
struct bb_antdiv_rate_info bb_rate_i;
|
||||
/* For RSSI */
|
||||
struct bb_antdiv_rssi_info bb_rssi_i;
|
||||
/* For sub BW TP */
|
||||
struct bb_sub_bw_tp_info bb_sub_bw_tp_i;
|
||||
|
||||
enum bb_antdiv_mode_t antdiv_mode;
|
||||
enum bb_antdiv_method_t antdiv_method;
|
||||
enum bb_antdiv_mode_t pre_antdiv_mode;
|
||||
enum bb_tp_method_t tp_decision_method;
|
||||
enum bb_evm_method_t evm_decision_method;
|
||||
bool tx_by_ext_pwr_lmt;
|
||||
|
||||
/* Training state & period related*/
|
||||
u8 antdiv_wd_cnt;
|
||||
u8 antdiv_training_state_cnt;
|
||||
u32 antdiv_intvl;
|
||||
u32 antdiv_delay;
|
||||
u32 antdiv_train_num;
|
||||
u8 antdiv_period;
|
||||
u8 tp_lb;
|
||||
u8 rssi_pre;
|
||||
u8 antdiv_notrain_cnt;
|
||||
u8 antdiv_notrain_num;
|
||||
u8 fixant_rssi_diff;
|
||||
|
||||
/* antenna setting */
|
||||
u8 pre_target_ant;
|
||||
u8 training_ant;
|
||||
u8 target_ant;
|
||||
u8 target_ant_cn;
|
||||
u8 target_ant_evm;
|
||||
u8 target_ant_tp;
|
||||
u8 target_ant_rssi;
|
||||
|
||||
/* Decision*/
|
||||
u16 tp_diff_th_high;
|
||||
u16 tp_diff_th_low;
|
||||
u8 evm_diff_th;
|
||||
u8 rssi_diff_th;
|
||||
|
||||
/*Phy-sts related */
|
||||
bool get_stats;
|
||||
bool antdiv_use_ctrl_frame;
|
||||
struct halbb_timer_info antdiv_timer_i;
|
||||
u32 rvrt_val; /*all rvrt_val for pause API must set to u32*/
|
||||
/* ant_div new code : extend to sub BW */
|
||||
bool ant_div_new;
|
||||
};
|
||||
|
||||
typedef struct {
|
||||
u32* sub_main_max_tp;
|
||||
u32* sub_aux_max_tp;
|
||||
u16* sub_main_max_cnt;
|
||||
u16* sub_aux_max_cnt;
|
||||
u16* sub_main_max_idx;
|
||||
u16* sub_aux_max_idx;
|
||||
} Cnt_info;
|
||||
|
||||
struct bb_info;
|
||||
/*@--------------------------[Prptotype]-------------------------------------*/
|
||||
void halbb_antdiv_io_en(struct bb_info *bb);
|
||||
void halbb_antdiv_timer_init(struct bb_info *bb);
|
||||
void halbb_cr_cfg_antdiv_init(struct bb_info *bb);
|
||||
void halbb_antdiv_reg_init(struct bb_info *bb);
|
||||
void halbb_antdiv_init(struct bb_info *bb);
|
||||
void halbb_antdiv_reset(struct bb_info *bb);
|
||||
void halbb_antdiv_reset_training_stat(struct bb_info *bb);
|
||||
void halbb_antdiv_set_ant(struct bb_info *bb, u8 ant);
|
||||
void halbb_antdiv_get_highest_mcs(struct bb_info *bb);
|
||||
void halbb_antdiv_get_evm_target_ant(struct bb_info *bb);
|
||||
void halbb_antdiv_training_state(struct bb_info *bb);
|
||||
void halbb_antdiv_decision_state(struct bb_info *bb);
|
||||
void halbb_antdiv_1ss_decision_state(struct bb_info *bb);
|
||||
void halbb_evm_based_antdiv(struct bb_info *bb);
|
||||
void halbb_antenna_diversity(struct bb_info *bb);
|
||||
void halbb_antdiv_phy_sts(struct bb_info *bb, u32 physts_bitmap,
|
||||
struct physts_rxd *desc);
|
||||
void halbb_antdiv_dbg(struct bb_info *bb, char input[][16], u32 *_used,
|
||||
char *output, u32 *_out_len);
|
||||
void halbb_set_antdiv_pause_val(struct bb_info *bb, u32 *val_buf, u8 val_len);
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,34 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2020 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in the
|
||||
* file called LICENSE.
|
||||
*
|
||||
* Contact Information:
|
||||
* wlanfae <wlanfae@realtek.com>
|
||||
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
|
||||
* Hsinchu 300, Taiwan.
|
||||
*
|
||||
* Larry Finger <Larry.Finger@lwfinger.net>
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __HALBB_ANT_DIV_EX_H__
|
||||
#define __HALBB_ANT_DIV_EX_H__
|
||||
/*@--------------------------[Define] ---------------------------------------*/
|
||||
/*@--------------------------[Enum]------------------------------------------*/
|
||||
/*@--------------------------[Structure]-------------------------------------*/
|
||||
struct bb_info;
|
||||
/*@--------------------------[Prptotype]-------------------------------------*/
|
||||
u8 halbb_antdiv_get_targetant(struct bb_info *bb);
|
||||
void halbb_antdiv_fix_ant(struct bb_info *bb, u8 ant);
|
||||
#endif
|
||||
+5323
File diff suppressed because it is too large
Load Diff
+111
@@ -0,0 +1,111 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2019 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef _HALBB_API_H_
|
||||
#define _HALBB_API_H_
|
||||
|
||||
#include "halbb_ic_hw_info.h"
|
||||
#include "halbb_dbcc_ex.h"
|
||||
|
||||
/*@--------------------------[Define] ---------------------------------------*/
|
||||
#define IGI_2_RSSI(igi) (igi - 10)
|
||||
|
||||
#define FUNC_ENABLE 1
|
||||
#define FUNC_DISABLE 2
|
||||
|
||||
#define BB_CH_SWH_HISTORY_SIZE 50
|
||||
/*@--------------------------[Enum]------------------------------------------*/
|
||||
enum bb_rfe_src_sel {
|
||||
PAPE_RFM = 0,
|
||||
GNT_BT_INV = 1,
|
||||
LNA0N = 2,
|
||||
LNAON_RFM = 3,
|
||||
TRSW_RFM = 4,
|
||||
TRSW_RFM_B = 5,
|
||||
GNT_BT = 6,
|
||||
ZERO = 7,
|
||||
ANTSEL_0 = 8,
|
||||
ANTSEL_1 = 9,
|
||||
ANTSEL_2 = 0xa,
|
||||
ANTSEL_3 = 0xb,
|
||||
ANTSEL_4 = 0xc,
|
||||
ANTSEL_5 = 0xd,
|
||||
ANTSEL_6 = 0xe,
|
||||
ANTSEL_7 = 0xf
|
||||
};
|
||||
|
||||
enum bb_mlo {
|
||||
MLO_OFF_BB0,
|
||||
MLO_OFF_BB1,
|
||||
MLO_ON
|
||||
};
|
||||
|
||||
enum bb_scan_mode{
|
||||
BB_SCAN_DISABLE = 0,
|
||||
BB_DRV_SCAN = 1,
|
||||
BB_P2P_SCAN = 2,
|
||||
BB_MRDM_SCAN = 3,
|
||||
BB_MAX_SCAN
|
||||
};
|
||||
/*@--------------------------[Structure]-------------------------------------*/
|
||||
struct bb_api_info {
|
||||
u32 rxiqc_reg1; /*N-mode: for pathA REG0xc14*/
|
||||
u32 rxiqc_reg2; /*N-mode: for pathB REG0xc1c*/
|
||||
u8 tx_queue_bitmap; /*REG0x520[23:16]*/
|
||||
u8 ccktx_path;
|
||||
u8 pri_ch_idx;
|
||||
u8 central_ch;
|
||||
u8 bw;
|
||||
u16 ch_switch_cnt;
|
||||
u8 ch_switch_history[BB_CH_SWH_HISTORY_SIZE]; /*fc CH*/
|
||||
u8 ch_switch_ptr;
|
||||
enum band_type band;
|
||||
};
|
||||
/*@--------------------------[Prptotype]-------------------------------------*/
|
||||
struct bb_info;
|
||||
enum bb_band_gt2_t halbb_get_band_gen2(struct bb_info *bb, u8 fc_ch,
|
||||
enum band_type band_in);
|
||||
enum bb_bw_type halbb_phl_2_bb_bw(struct bb_info *bb, enum channel_width phl_bw);
|
||||
u8 halbb_dbcc_get_valid_rf_path_mask(struct bb_info *bb);
|
||||
u8 halbb_ch_2_band(struct bb_info *bb, u8 fc_ch);
|
||||
u16 halbb_get_csi_buf_idx(struct bb_info *bb, u8 buf_idx, u8 txsc_idx);
|
||||
|
||||
void halbb_reset_bb_phy(struct bb_info *bb, enum phl_phy_idx phy_idx);
|
||||
void halbb_gpio_setting_init(struct bb_info *bb);
|
||||
void halbb_pre_agc_en(struct bb_info *bb, bool enable);
|
||||
void halbb_set_gain_error(struct bb_info *bb, u8 central_ch, enum band_type band, enum rf_path path);
|
||||
u8 halbb_stop_ic_trx(struct bb_info *bb, u8 set_type);
|
||||
void halbb_ic_api_dbg(struct bb_info *bb, char input[][16], u32 *_used,
|
||||
char *output, u32 *_out_len);
|
||||
u16 halbb_fc_mapping(struct bb_info *bb, enum band_type band, u8 central_ch);
|
||||
u8 halbb_gain_band_determine(struct bb_info *bb, u8 central_ch,
|
||||
enum band_type band_type);
|
||||
void halbb_ic_hw_setting_non_io(struct bb_info *bb);
|
||||
void halbb_ic_hw_setting_low_io(struct bb_info *bb);
|
||||
void halbb_ic_hw_setting_dbcc(struct bb_info *bb);
|
||||
void halbb_ic_hw_setting(struct bb_info *bb);
|
||||
void halbb_ic_hw_setting_dbg(struct bb_info *bb, char input[][16],
|
||||
u32 *_used, char *output, u32 *_out_len);
|
||||
#ifdef HALBB_PATH_DIV_SUPPORT
|
||||
void halbb_ctrl_tx_path_div(struct bb_info * bb, enum bb_path tx_path_1ss);
|
||||
void halbb_ctrl_path_div_6g(struct bb_info *bb, bool is_disable_6g);
|
||||
#endif
|
||||
void halbb_pwr_diff_wa_enable(struct bb_info *bb, enum phl_phy_idx phy_idx);
|
||||
void halbb_pwr_diff_wa_disable(struct bb_info *bb, enum phl_phy_idx phy_idx);
|
||||
void halbb_per_macid_tx_path_init(struct bb_info *bb, u16 macid);
|
||||
void halbb_set_cctrl_tbl(struct bb_info *bb, u16 macid, u16 cfg);
|
||||
enum rf_path halbb_bb_path_2_rf_path(struct bb_info *bb, enum bb_path path_in);
|
||||
void halbb_api_init(struct bb_info *bb);
|
||||
void halbb_cfg_scan_mode(struct bb_info *bb, enum phl_msg_evt_id event, bool is_start, enum phl_phy_idx phy_idx);
|
||||
#endif
|
||||
+30
@@ -0,0 +1,30 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2020 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef _HALBB_API_BE_H_
|
||||
#define _HALBB_API_BE_H_
|
||||
|
||||
/*@--------------------------[Define] ---------------------------------------*/
|
||||
|
||||
/*@--------------------------[Enum]------------------------------------------*/
|
||||
|
||||
/*@--------------------------[Structure]-------------------------------------*/
|
||||
|
||||
/*@--------------------------[Prptotype]-------------------------------------*/
|
||||
struct bb_info;
|
||||
|
||||
u8 halbb_get_prim_sb(struct bb_info *bb, u8 central_ch, u8 pri_ch,
|
||||
enum channel_width bw);
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,34 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2020 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef _HALBB_API_BE_EX_H_
|
||||
#define _HALBB_API_BE_EX_H_
|
||||
|
||||
/*@--------------------------[Define] ---------------------------------------*/
|
||||
|
||||
/*@--------------------------[Enum]------------------------------------------*/
|
||||
|
||||
/*@--------------------------[Structure]-------------------------------------*/
|
||||
|
||||
/*@--------------------------[Prptotype]-------------------------------------*/
|
||||
struct bb_info;
|
||||
|
||||
u16 halbb_pri20_bitmap(struct bb_info *bb, u8 central_ch, u8 pri_ch,
|
||||
enum channel_width bw);
|
||||
|
||||
u16 halbb_preamble_puncture(struct bb_info *bb, u8 central_ch, u8 pri_ch,
|
||||
enum channel_width cbw, enum channel_width dbw,
|
||||
u8 punc_ch_info);
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,39 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2020 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef _HALBB_API_BE_HW_H_
|
||||
#define _HALBB_API_BE_HW_H_
|
||||
|
||||
/*@--------------------------[Define] ---------------------------------------*/
|
||||
|
||||
/*@--------------------------[Enum]------------------------------------------*/
|
||||
|
||||
/*@--------------------------[Structure]-------------------------------------*/
|
||||
|
||||
/*@--------------------------[Prptotype]-------------------------------------*/
|
||||
struct bb_info;
|
||||
u8 halbb_get_prim_sb_be(struct bb_info *bb, u8 central_ch, u8 pri_ch,
|
||||
enum channel_width bw);
|
||||
|
||||
u16 halbb_pri20_bitmap_be(struct bb_info *bb, u8 central_ch, u8 pri_ch,
|
||||
enum channel_width bw);
|
||||
|
||||
u16 halbb_ch20_with_data_lut_be(struct bb_info *bb, enum channel_width dbw,
|
||||
u8 punc_ch_info);
|
||||
|
||||
u16 halbb_preamble_puncture_be(struct bb_info *bb, u8 central_ch, u8 pri_ch,
|
||||
enum channel_width cbw, enum channel_width dbw,
|
||||
u8 punc_ch_info);
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,27 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2020 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef _HALBB_API_BE_INTG_H_
|
||||
#define _HALBB_API_BE_INTG_H_
|
||||
|
||||
/*@--------------------------[Define] ---------------------------------------*/
|
||||
|
||||
/*@--------------------------[Enum]------------------------------------------*/
|
||||
|
||||
/*@--------------------------[Structure]-------------------------------------*/
|
||||
|
||||
/*@--------------------------[Prptotype]-------------------------------------*/
|
||||
struct bb_info;
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,27 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2020 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef _HALBB_API_BE_SW_H_
|
||||
#define _HALBB_API_BE_SW_H_
|
||||
|
||||
/*@--------------------------[Define] ---------------------------------------*/
|
||||
|
||||
/*@--------------------------[Enum]------------------------------------------*/
|
||||
|
||||
/*@--------------------------[Structure]-------------------------------------*/
|
||||
|
||||
/*@--------------------------[Prptotype]-------------------------------------*/
|
||||
struct bb_info;
|
||||
|
||||
#endif
|
||||
+232
@@ -0,0 +1,232 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2020 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef _HALBB_API_EX_H_
|
||||
#define _HALBB_API_EX_H_
|
||||
#include "halbb_ic_hw_info.h"
|
||||
#include "halbb_api.h"
|
||||
/*@--------------------------[Prptotype]-------------------------------------*/
|
||||
struct bb_info;
|
||||
#define MAX_MR_NUM 3
|
||||
struct bb_mcc_i {
|
||||
enum role_type type;
|
||||
struct rtw_chan_def *chandef;
|
||||
u32 *macid_bitmap;
|
||||
u8 macid_map_len;
|
||||
u8 self_macid;
|
||||
};
|
||||
|
||||
struct bb_mr_i {
|
||||
struct rtw_chan_def chandef;
|
||||
u8 *all_macid; /* all used macid bitmap */
|
||||
u8 all_macid_len;
|
||||
};
|
||||
|
||||
struct bb_mrdm_i {
|
||||
enum phl_phy_idx phy_idx;
|
||||
struct bb_mr_i mr_info[MAX_MR_NUM];
|
||||
u8 mr_num;
|
||||
};
|
||||
|
||||
u8 halbb_ex_cn_report(struct bb_info * bb);
|
||||
u8 halbb_ex_evm_1ss_report(struct bb_info *bb);
|
||||
u8 halbb_ex_evm_max_report(struct bb_info *bb);
|
||||
u8 halbb_ex_evm_min_report(struct bb_info *bb);
|
||||
|
||||
bool halbb_tx_cfr_byrate_sup(struct bb_info *bb);
|
||||
u16 halbb_cfg_cmac_tx_ant(struct bb_info *bb, enum rf_path tx_path);
|
||||
void halbb_gpio_setting_all(struct bb_info *bb, u8 rfe_idx);
|
||||
void halbb_gpio_setting(struct bb_info *bb, u8 gpio_idx, enum bb_path path,
|
||||
bool inv, enum bb_rfe_src_sel src);
|
||||
u8 halbb_get_txsc(struct bb_info *bb, u8 pri_ch, u8 central_ch,
|
||||
enum channel_width cbw, enum channel_width dbw);
|
||||
u8 halbb_get_txsb(struct bb_info *bb, u8 pri_ch, u8 central_ch,
|
||||
enum channel_width cbw, enum channel_width dbw);
|
||||
void halbb_bb_reset_all(struct bb_info *bb, enum phl_phy_idx phy_idx);
|
||||
bool halbb_bb_reset_cmn(struct bb_info *bb, bool en, enum phl_phy_idx phy_idx);
|
||||
void halbb_reset_bb(struct bb_info *bb);
|
||||
|
||||
u32 halbb_read_rf_reg_dbg(struct bb_info *bb, enum rf_path path, u32 addr);
|
||||
|
||||
u32 halbb_read_rf_reg(struct bb_info *bb, enum rf_path path, u32 addr, u32 mask);
|
||||
|
||||
bool halbb_write_rf_reg(struct bb_info *bb, enum rf_path path, u32 addr, u32 mask,
|
||||
u32 data);
|
||||
bool halbb_rf_set_bb_reg(struct bb_info *bb, u32 addr, u32 bit_mask, u32 data);
|
||||
u32 halbb_rf_get_bb_reg(struct bb_info *bb, u32 addr, u32 mask);
|
||||
void halbb_ctrl_rf_mode(struct bb_info *bb, enum phl_rf_mode mode);
|
||||
|
||||
void halbb_ctrl_rf_mode_rx_path(struct bb_info *bb, enum rf_path rx_path);
|
||||
|
||||
bool halbb_ctrl_tx_path_bb_afe_map(struct bb_info *bb, u8 mapping_idx);
|
||||
|
||||
bool halbb_ctrl_rx_path(struct bb_info *bb, enum rf_path rx_path,
|
||||
enum phl_phy_idx phy_idx);
|
||||
|
||||
bool halbb_ctrl_tx_path_pmac(struct bb_info *bb, enum rf_path tx_path,
|
||||
enum phl_phy_idx phy_idx);
|
||||
|
||||
bool halbb_cfg_rx_path(struct bb_info *bb, enum bb_path rx_path,
|
||||
enum phl_phy_idx phy_idx);
|
||||
|
||||
bool halbb_cfg_tx_path_pmac(struct bb_info *bb, enum bb_path tx_path,
|
||||
enum phl_phy_idx phy_idx);
|
||||
|
||||
bool halbb_cfg_tx_path(struct bb_info *bb, enum bb_path tx_path,
|
||||
enum phl_phy_idx phy_idx);
|
||||
|
||||
void halbb_ctrl_trx_path(struct bb_info *bb, enum rf_path tx_path, u8 tx_nss,
|
||||
enum rf_path rx_path, u8 rx_nss);
|
||||
|
||||
void halbb_cfg_trx_path(struct bb_info *bb, struct bb_tx_path_en_info tx_path_i,
|
||||
struct bb_rx_path_en_info rx_path_i, enum mlo_dbcc_mode_type mode);
|
||||
|
||||
void halbb_tssi_bb_reset(struct bb_info *bb);
|
||||
|
||||
void halbb_dfs_en(struct bb_info *bb, bool en);
|
||||
void halbb_adc_ctrl_en(struct bb_info *bb, bool en, enum phl_phy_idx phy_idx);
|
||||
void halbb_adc_en(struct bb_info *bb, bool en);
|
||||
bool halbb_adc_cfg(struct bb_info *bb, enum channel_width bw, enum rf_path path,
|
||||
enum phl_phy_idx phy_idx);
|
||||
|
||||
void halbb_tssi_cont_en(struct bb_info *bb, bool en, enum rf_path path);
|
||||
|
||||
void halbb_bb_reset_en(struct bb_info *bb, bool en, enum phl_phy_idx phy_idx);
|
||||
|
||||
bool halbb_ctrl_bw(struct bb_info *bb, u8 pri_ch, enum band_type band, enum channel_width bw,
|
||||
enum phl_phy_idx phy_idx);
|
||||
|
||||
bool halbb_ctrl_bw_ch(struct bb_info *bb, u8 pri_ch, u8 central_ch_seg0,
|
||||
u8 central_ch_seg1, enum band_type band,
|
||||
enum channel_width bw, enum phl_phy_idx phy_idx);
|
||||
|
||||
bool halbb_ctrl_op_ch_pd(struct bb_info *bb_0, bool is_op_ch, u8 central_ch,
|
||||
enum band_type band, enum channel_width bw,
|
||||
enum phl_phy_idx phy_idx);
|
||||
|
||||
void halbb_op_ch_info_update(struct bb_info *bb, bool enable,
|
||||
enum phl_phy_idx phy_idx);
|
||||
#if (HLABB_CODE_BASE_NUM >= 32)
|
||||
bool halbb_pre_ctrl_bw_ch(struct bb_info *bb, enum phl_phy_idx phy_idx);
|
||||
|
||||
bool halbb_post_ctrl_bw_ch(struct bb_info *bb, enum phl_phy_idx phy_idx);
|
||||
#endif
|
||||
void halbb_ctrl_rx_cca(struct bb_info *bb, bool cca_en, enum phl_phy_idx phy_idx);
|
||||
|
||||
bool halbb_query_cck_en(struct bb_info *bb, enum phl_phy_idx phy_idx);
|
||||
|
||||
void halbb_ctrl_cck_en(struct bb_info *bb, bool cck_enable,
|
||||
enum phl_phy_idx phy_idx);
|
||||
|
||||
void halbb_ctrl_ofdm_en(struct bb_info *bb, bool ofdm_enable,
|
||||
enum phl_phy_idx phy_idx);
|
||||
|
||||
void halbb_ctrl_btg(struct bb_info *bb, bool btg);
|
||||
|
||||
void halbb_ctrl_btc_preagc(struct bb_info *bb, bool bt_en);
|
||||
|
||||
void halbb_btg_bt_rx(struct bb_info *bb, bool en, enum phl_phy_idx phy_idx);
|
||||
|
||||
void halbb_nbtg_bt_tx(struct bb_info *bb, bool en, enum phl_phy_idx phy_idx);
|
||||
|
||||
void halbb_bt_btg_trx_cmn(struct bb_info *bb, bool btg, bool bt_en, bool is_2g,
|
||||
enum phl_phy_idx phy_idx);
|
||||
|
||||
void halbb_pop_en(struct bb_info *bb, bool en, enum phl_phy_idx phy_idx);
|
||||
|
||||
bool halbb_querry_pop_en(struct bb_info *bb, enum phl_phy_idx phy_idx);
|
||||
|
||||
bool halbb_set_pd_lower_bound(struct bb_info *bb, u8 bound,
|
||||
enum channel_width bw, enum phl_phy_idx phy_idx);
|
||||
|
||||
bool halbb_set_pd_lower_bound_cck(struct bb_info *bb, u8 bound,
|
||||
enum channel_width bw, enum phl_phy_idx phy_idx);
|
||||
|
||||
u8 halbb_querry_pd_lower_bound(struct bb_info *bb, bool get_en_info,
|
||||
enum phl_phy_idx phy_idx);
|
||||
|
||||
u8 halbb_get_losel(struct bb_info *bb);
|
||||
|
||||
void halbb_set_ant(struct bb_info *bb, u8 ant);
|
||||
|
||||
void halbb_syn_sel(struct bb_info *bb, enum rf_path path, bool val,
|
||||
enum phl_phy_idx phy_idx);
|
||||
|
||||
void halbb_bb_wrap_set_pow_by_rate_all(struct bb_info *bb, enum phl_phy_idx phy_idx);
|
||||
|
||||
void halbb_bb_wrap_set_pwr_limit_rua_all(struct bb_info *bb, enum phl_phy_idx phy_idx);
|
||||
|
||||
void halbb_bb_wrap_set_pwr_limit_all(struct bb_info *bb, enum phl_phy_idx phy_idx);
|
||||
|
||||
void halbb_bb_wrap_set_pwr_ofst_mode_all(struct bb_info *bb, enum phl_phy_idx phy_idx);
|
||||
|
||||
void halbb_bb_wrap_set_pwr_ofst_bw_all(struct bb_info *bb, enum phl_phy_idx phy_idx);
|
||||
|
||||
void halbb_bb_wrap_set_pwr_limit_en(struct bb_info *bb, enum phl_phy_idx phy_idx);
|
||||
|
||||
void halbb_bb_wrap_set_max_pwr_limit(struct bb_info *bb, enum phl_phy_idx phy_idx, s16 max_limit);
|
||||
enum rtw_hal_status halbb_emlsr_en(struct bb_info *bb, bool en);
|
||||
|
||||
#if (HLABB_CODE_BASE_NUM >= 32)
|
||||
bool halbb_ctrl_mlo(struct bb_info *bb, enum mlo_dbcc_mode_type mode);
|
||||
#endif
|
||||
|
||||
void halbb_set_igi(struct bb_info *bb, u8 lna_idx, bool tia_idx, u8 rxbb_idx,
|
||||
enum rf_path path);
|
||||
void halbb_set_tx_pow_pattern_shap(struct bb_info *bb, u8 ch,
|
||||
bool is_ofdm, enum phl_phy_idx phy_idx);
|
||||
void halbb_set_tx_pow_per_path_lmt(struct bb_info *bb, s16 pwr_lmt_a, s16 pwr_lmt_b);
|
||||
void halbb_set_tx_pow_ref(struct bb_info *bb, enum phl_phy_idx phy_idx);
|
||||
|
||||
void halbb_normal_efuse_verify(struct bb_info *bb, s8 rx_gain_offset,
|
||||
enum rf_path rx_path, enum phl_phy_idx phy_idx);
|
||||
|
||||
u8 halbb_upd_mcc_macid(struct bb_info *bb, struct bb_mcc_i *mi);
|
||||
|
||||
void halbb_mcc_stop(struct bb_info *bb);
|
||||
|
||||
u8 halbb_mcc_start(struct bb_info *bb, struct bb_mcc_i *mi_1,
|
||||
struct bb_mcc_i *mi_2);
|
||||
|
||||
u8 halbb_mrdm_start(struct bb_info *bb, u8 phy_type, struct bb_mrdm_i *mrdm);
|
||||
|
||||
void halbb_mrdm_stop(struct bb_info *bb, u8 phy_type);
|
||||
|
||||
u8 halbb_upd_mrdm_macid(struct bb_info *bb, struct bb_mrdm_i *mrdm);
|
||||
|
||||
void halbb_normal_efuse_verify_cck(struct bb_info *bb, s8 rx_gain_offset,
|
||||
enum rf_path rx_path,
|
||||
enum phl_phy_idx phy_idx);
|
||||
enum rtw_hal_status halbb_config_cmac_tbl(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i,
|
||||
void *cctrl,
|
||||
void *cctl_info_mask);
|
||||
extern bool halbb_lps_info(struct bb_info *bb, u16 mac_id);
|
||||
|
||||
extern bool halbb_lps_save_ch_info(struct bb_info *bb);
|
||||
|
||||
extern bool halbb_lps_info_status_chk(struct bb_info *bb);
|
||||
|
||||
void halbb_agc_fix_gain(struct bb_info *bb, bool enable, enum rf_path path,
|
||||
enum phl_phy_idx phy_idx);
|
||||
void halbb_agc_elna_idx(struct bb_info *bb, bool elna_idx, enum rf_path path,
|
||||
enum phl_phy_idx phy_idx);
|
||||
void halbb_agc_tia_shrink(struct bb_info *bb, bool shrink_en, bool shrink_init,
|
||||
enum rf_path path, enum phl_phy_idx phy_idx);
|
||||
void halbb_npath_en_update(struct bb_info *bb, bool npath_en);
|
||||
void halbb_update_tx_path_div(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i);
|
||||
void halbb_nvar_src_sel(struct bb_info *bb, bool is_BF);
|
||||
void halbb_1ss_4tx_csd_set(struct bb_info *bb, bool is_no_csd, enum phl_phy_idx phy_idx);
|
||||
void halbb_force_cfo_one_shot_comp_en(struct bb_info *bb, bool en, enum phl_phy_idx phy_idx);
|
||||
void halbb_extra_rx_path(struct bb_info *bb, bool en, enum bb_path rx_path, enum phl_phy_idx phy_idx);
|
||||
#endif
|
||||
@@ -0,0 +1,60 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2020 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in the
|
||||
* file called LICENSE.
|
||||
*
|
||||
* Contact Information:
|
||||
* wlanfae <wlanfae@realtek.com>
|
||||
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
|
||||
* Hsinchu 300, Taiwan.
|
||||
*
|
||||
* Larry Finger <Larry.Finger@lwfinger.net>
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __HALBB_AUTO_DBG_H__
|
||||
#define __HALBB_AUTO_DBG_H__
|
||||
#ifdef HALBB_AUTO_DBG_SUPPORT
|
||||
/*@--------------------------[Define] ---------------------------------------*/
|
||||
|
||||
/*@--------------------------[Enum]------------------------------------------*/
|
||||
|
||||
/*@--------------------------[Structure]-------------------------------------*/
|
||||
|
||||
struct bb_chk_hang_info {
|
||||
u32 table_size;
|
||||
u32 *dbg_port_table;
|
||||
u32 *dbg_port_val;
|
||||
};
|
||||
|
||||
struct bb_auto_dbg_info {
|
||||
u32 auto_dbg_type; /*enum bb_auto_dbg_t*/
|
||||
struct bb_chk_hang_info bb_chk_hang_i;
|
||||
struct bb_bkp_pmac_info bb_bkp_pmac_i;
|
||||
struct bb_bkp_phy_utility_info bb_bkp_phy_utility_i;
|
||||
struct bb_stat_hang_info bb_bkp_stat_hang_i;
|
||||
};
|
||||
|
||||
struct bb_info;
|
||||
/*@--------------------------[Prptotype]-------------------------------------*/
|
||||
void halbb_auto_debug_watchdog(struct bb_info *bb);
|
||||
void halbb_auto_debug_init(struct bb_info *bb);
|
||||
void halbb_auto_debug_dbg(struct bb_info *bb, char input[][16],
|
||||
u32 *_used, char *output, u32 *_out_len);
|
||||
#ifdef HALBB_SELF_DIAG_SUPPORT
|
||||
void halbb_diagnostic_event_notify(struct bb_info *bb, enum habb_fun_t type, u8 sub_type);
|
||||
#endif
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user